2 * Copyright (c) 2016 Andreas Färber
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 * Copyright (c) 2016 Endless Computers, Inc.
8 * Author: Carlo Caione <carlo@endlessm.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
15 * a) This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
49 #include <dt-bindings/gpio/gpio.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 interrupt-parent = <&gic>;
63 /* 16 MiB reserved for Hardware ROM Firmware */
64 hwrom_reserved: hwrom@0 {
65 reg = <0x0 0x0 0x0 0x1000000>;
69 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
70 secmon_reserved: secmon@10000000 {
71 reg = <0x0 0x10000000 0x0 0x200000>;
77 #address-cells = <0x2>;
82 compatible = "arm,cortex-a53", "arm,armv8";
84 enable-method = "psci";
85 next-level-cache = <&l2>;
86 clocks = <&scpi_dvfs 0>;
91 compatible = "arm,cortex-a53", "arm,armv8";
93 enable-method = "psci";
94 next-level-cache = <&l2>;
95 clocks = <&scpi_dvfs 0>;
100 compatible = "arm,cortex-a53", "arm,armv8";
102 enable-method = "psci";
103 next-level-cache = <&l2>;
104 clocks = <&scpi_dvfs 0>;
109 compatible = "arm,cortex-a53", "arm,armv8";
111 enable-method = "psci";
112 next-level-cache = <&l2>;
113 clocks = <&scpi_dvfs 0>;
117 compatible = "cache";
122 compatible = "arm,cortex-a53-pmu";
123 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
131 compatible = "arm,psci-0.2";
136 compatible = "arm,armv8-timer";
137 interrupts = <GIC_PPI 13
138 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
140 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
142 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
144 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
148 compatible = "fixed-clock";
149 clock-frequency = <24000000>;
150 clock-output-names = "xtal";
156 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
161 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
162 #address-cells = <1>;
169 eth_mac: eth_mac@34 {
179 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
180 mboxes = <&mailbox 1 &mailbox 2>;
181 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
183 scpi_clocks: clocks {
184 compatible = "arm,scpi-clocks";
186 scpi_dvfs: scpi_clocks@0 {
187 compatible = "arm,scpi-dvfs-clocks";
190 clock-output-names = "vcpu";
194 scpi_sensors: sensors {
195 compatible = "arm,scpi-sensors";
196 #thermal-sensor-cells = <1>;
201 compatible = "simple-bus";
202 #address-cells = <2>;
206 cbus: cbus@c1100000 {
207 compatible = "simple-bus";
208 reg = <0x0 0xc1100000 0x0 0x100000>;
209 #address-cells = <2>;
211 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
213 reset: reset-controller@4404 {
214 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
215 reg = <0x0 0x04404 0x0 0x20>;
219 uart_A: serial@84c0 {
220 compatible = "amlogic,meson-uart";
221 reg = <0x0 0x84c0 0x0 0x14>;
222 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
227 uart_B: serial@84dc {
228 compatible = "amlogic,meson-uart";
229 reg = <0x0 0x84dc 0x0 0x14>;
230 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
236 compatible = "amlogic,meson-gxbb-i2c";
237 reg = <0x0 0x08500 0x0 0x20>;
238 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
239 #address-cells = <1>;
245 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
246 reg = <0x0 0x08550 0x0 0x10>;
252 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
253 reg = <0x0 0x08650 0x0 0x10>;
259 compatible = "amlogic,meson-saradc";
260 reg = <0x0 0x8680 0x0 0x34>;
261 #io-channel-cells = <1>;
262 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
267 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
268 reg = <0x0 0x086c0 0x0 0x10>;
273 uart_C: serial@8700 {
274 compatible = "amlogic,meson-uart";
275 reg = <0x0 0x8700 0x0 0x14>;
276 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
282 compatible = "amlogic,meson-gxbb-i2c";
283 reg = <0x0 0x087c0 0x0 0x20>;
284 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
285 #address-cells = <1>;
291 compatible = "amlogic,meson-gxbb-i2c";
292 reg = <0x0 0x087e0 0x0 0x20>;
293 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
294 #address-cells = <1>;
300 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
301 reg = <0x0 0x098d0 0x0 0x10>;
306 gic: interrupt-controller@c4301000 {
307 compatible = "arm,gic-400";
308 reg = <0x0 0xc4301000 0 0x1000>,
309 <0x0 0xc4302000 0 0x2000>,
310 <0x0 0xc4304000 0 0x2000>,
311 <0x0 0xc4306000 0 0x2000>;
312 interrupt-controller;
313 interrupts = <GIC_PPI 9
314 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
315 #interrupt-cells = <3>;
316 #address-cells = <0>;
319 sram: sram@c8000000 {
320 compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
321 reg = <0x0 0xc8000000 0x0 0x14000>;
323 #address-cells = <1>;
325 ranges = <0 0x0 0xc8000000 0x14000>;
327 cpu_scp_lpri: scp-shmem@0 {
328 compatible = "amlogic,meson-gxbb-scp-shmem";
329 reg = <0x13000 0x400>;
332 cpu_scp_hpri: scp-shmem@200 {
333 compatible = "amlogic,meson-gxbb-scp-shmem";
334 reg = <0x13400 0x400>;
338 aobus: aobus@c8100000 {
339 compatible = "simple-bus";
340 reg = <0x0 0xc8100000 0x0 0x100000>;
341 #address-cells = <2>;
343 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
345 uart_AO: serial@4c0 {
346 compatible = "amlogic,meson-uart";
347 reg = <0x0 0x004c0 0x0 0x14>;
348 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
353 uart_AO_B: serial@4e0 {
354 compatible = "amlogic,meson-uart";
355 reg = <0x0 0x004e0 0x0 0x14>;
356 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
362 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
363 reg = <0x0 0x00550 0x0 0x10>;
369 compatible = "amlogic,meson-gxbb-ir";
370 reg = <0x0 0x00580 0x0 0x40>;
371 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
376 periphs: periphs@c8834000 {
377 compatible = "simple-bus";
378 reg = <0x0 0xc8834000 0x0 0x2000>;
379 #address-cells = <2>;
381 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
384 compatible = "amlogic,meson-rng";
385 reg = <0x0 0x0 0x0 0x4>;
390 hiubus: hiubus@c883c000 {
391 compatible = "simple-bus";
392 reg = <0x0 0xc883c000 0x0 0x2000>;
393 #address-cells = <2>;
395 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
397 mailbox: mailbox@404 {
398 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
399 reg = <0 0x404 0 0x4c>;
400 interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
401 <0 209 IRQ_TYPE_EDGE_RISING>,
402 <0 210 IRQ_TYPE_EDGE_RISING>;
407 ethmac: ethernet@c9410000 {
408 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
409 reg = <0x0 0xc9410000 0x0 0x10000
410 0x0 0xc8834540 0x0 0x4>;
411 interrupts = <0 8 1>;
412 interrupt-names = "macirq";
417 compatible = "simple-bus";
418 reg = <0x0 0xd0000000 0x0 0x200000>;
419 #address-cells = <2>;
421 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
423 sd_emmc_a: mmc@70000 {
424 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
425 reg = <0x0 0x70000 0x0 0x2000>;
426 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
430 sd_emmc_b: mmc@72000 {
431 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
432 reg = <0x0 0x72000 0x0 0x2000>;
433 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
437 sd_emmc_c: mmc@74000 {
438 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
439 reg = <0x0 0x74000 0x0 0x2000>;
440 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
446 compatible = "amlogic,meson-gx-vpu";
447 reg = <0x0 0xd0100000 0x0 0x100000>,
448 <0x0 0xc883c000 0x0 0x1000>,
449 <0x0 0xc8838000 0x0 0x1000>;
450 reg-names = "vpu", "hhi", "dmc";
451 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
452 #address-cells = <1>;
455 /* CVBS VDAC output port */
456 cvbs_vdac_port: port@0 {