arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

   1 /*
   2  * Copyright (c) 2016 Andreas Färber
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
  47 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  48 #include <dt-bindings/clock/gxbb-clkc.h>
  49 #include <dt-bindings/clock/gxbb-aoclkc.h>
  50 #include <dt-bindings/reset/gxbb-aoclkc.h>
  51
  52 / {
  53         compatible = "amlogic,meson-gxbb";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         cpus {
  59                 #address-cells = <0x2>;
  60                 #size-cells = <0x0>;
  61
  62                 cpu0: cpu@0 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x0 0x0>;
  66                         enable-method = "psci";
  67                 };
  68
  69                 cpu1: cpu@1 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53", "arm,armv8";
  72                         reg = <0x0 0x1>;
  73                         enable-method = "psci";
  74                 };
  75
  76                 cpu2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         reg = <0x0 0x2>;
  80                         enable-method = "psci";
  81                 };
  82
  83                 cpu3: cpu@3 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x3>;
  87                         enable-method = "psci";
  88                 };
  89         };
  90
  91         arm-pmu {
  92                 compatible = "arm,cortex-a53-pmu";
  93                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  94                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  95                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  96                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  97                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  98         };
  99
 100         psci {
 101                 compatible = "arm,psci-0.2";
 102                 method = "smc";
 103         };
 104
 105         firmware {
 106                 sm: secure-monitor {
 107                         compatible = "amlogic,meson-gxbb-sm";
 108                 };
 109         };
 110
 111         timer {
 112                 compatible = "arm,armv8-timer";
 113                 interrupts = <GIC_PPI 13
 114                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
 115                              <GIC_PPI 14
 116                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
 117                              <GIC_PPI 11
 118                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
 119                              <GIC_PPI 10
 120                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
 121         };
 122
 123         xtal: xtal-clk {
 124                 compatible = "fixed-clock";
 125                 clock-frequency = <24000000>;
 126                 clock-output-names = "xtal";
 127                 #clock-cells = <0>;
 128         };
 129
 130         soc {
 131                 compatible = "simple-bus";
 132                 #address-cells = <2>;
 133                 #size-cells = <2>;
 134                 ranges;
 135
 136                 cbus: cbus@c1100000 {
 137                         compatible = "simple-bus";
 138                         reg = <0x0 0xc1100000 0x0 0x100000>;
 139                         #address-cells = <2>;
 140                         #size-cells = <2>;
 141                         ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
 142
 143                         reset: reset-controller@4404 {
 144                                 compatible = "amlogic,meson-gxbb-reset";
 145                                 reg = <0x0 0x04404 0x0 0x20>;
 146                                 #reset-cells = <1>;
 147                         };
 148
 149                         uart_A: serial@84c0 {
 150                                 compatible = "amlogic,meson-uart";
 151                                 reg = <0x0 0x84c0 0x0 0x14>;
 152                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 153                                 clocks = <&xtal>;
 154                                 status = "disabled";
 155                         };
 156
 157                         uart_B: serial@84dc {
 158                                 compatible = "amlogic,meson-uart";
 159                                 reg = <0x0 0x84dc 0x0 0x14>;
 160                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 161                                 clocks = <&xtal>;
 162                                 status = "disabled";
 163                         };
 164
 165                         uart_C: serial@8700 {
 166                                 compatible = "amlogic,meson-uart";
 167                                 reg = <0x0 0x8700 0x0 0x14>;
 168                                 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
 169                                 clocks = <&xtal>;
 170                                 status = "disabled";
 171                         };
 172
 173                         watchdog@98d0 {
 174                                 compatible = "amlogic,meson-gxbb-wdt";
 175                                 reg = <0x0 0x098d0 0x0 0x10>;
 176                                 clocks = <&xtal>;
 177                         };
 178                 };
 179
 180                 gic: interrupt-controller@c4301000 {
 181                         compatible = "arm,gic-400";
 182                         reg = <0x0 0xc4301000 0 0x1000>,
 183                               <0x0 0xc4302000 0 0x2000>,
 184                               <0x0 0xc4304000 0 0x2000>,
 185                               <0x0 0xc4306000 0 0x2000>;
 186                         interrupt-controller;
 187                         interrupts = <GIC_PPI 9
 188                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 189                         #interrupt-cells = <3>;
 190                         #address-cells = <0>;
 191                 };
 192
 193                 aobus: aobus@c8100000 {
 194                         compatible = "simple-bus";
 195                         reg = <0x0 0xc8100000 0x0 0x100000>;
 196                         #address-cells = <2>;
 197                         #size-cells = <2>;
 198                         ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
 199
 200                         pinctrl_aobus: pinctrl@14 {
 201                                 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
 202                                 #address-cells = <2>;
 203                                 #size-cells = <2>;
 204                                 ranges;
 205
 206                                 gpio_ao: bank@14 {
 207                                         reg = <0x0 0x00014 0x0 0x8>,
 208                                               <0x0 0x0002c 0x0 0x4>,
 209                                               <0x0 0x00024 0x0 0x8>;
 210                                         reg-names = "mux", "pull", "gpio";
 211                                         gpio-controller;
 212                                         #gpio-cells = <2>;
 213                                 };
 214
 215                                 uart_ao_a_pins: uart_ao_a {
 216                                         mux {
 217                                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 218                                                 function = "uart_ao";
 219                                         };
 220                                 };
 221
 222                                 remote_input_ao_pins: remote_input_ao {
 223                                         mux {
 224                                                 groups = "remote_input_ao";
 225                                                 function = "remote_input_ao";
 226                                         };
 227                                 };
 228
 229                                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 230                                         mux {
 231                                                 groups = "pwm_ao_a_3";
 232                                                 function = "pwm_ao_a_3";
 233                                         };
 234                                 };
 235
 236                                 pwm_ao_a_6_pins: pwm_ao_a_6 {
 237                                         mux {
 238                                                 groups = "pwm_ao_a_6";
 239                                                 function = "pwm_ao_a_6";
 240                                         };
 241                                 };
 242
 243                                 pwm_ao_a_12_pins: pwm_ao_a_12 {
 244                                         mux {
 245                                                 groups = "pwm_ao_a_12";
 246                                                 function = "pwm_ao_a_12";
 247                                         };
 248                                 };
 249
 250                                 pwm_ao_b_pins: pwm_ao_b {
 251                                         mux {
 252                                                 groups = "pwm_ao_b";
 253                                                 function = "pwm_ao_b";
 254                                         };
 255                                 };
 256                         };
 257
 258                         clkc_AO: clock-controller@040 {
 259                                 compatible = "amlogic,gxbb-aoclkc";
 260                                 reg = <0x0 0x00040 0x0 0x4>;
 261                                 #clock-cells = <1>;
 262                                 #reset-cells = <1>;
 263                         };
 264
 265                         uart_AO: serial@4c0 {
 266                                 compatible = "amlogic,meson-uart";
 267                                 reg = <0x0 0x004c0 0x0 0x14>;
 268                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
 269                                 clocks = <&xtal>;
 270                                 status = "disabled";
 271                         };
 272
 273                         ir: ir@580 {
 274                                 compatible = "amlogic,meson-gxbb-ir";
 275                                 reg = <0x0 0x00580 0x0 0x40>;
 276                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
 277                                 status = "disabled";
 278                         };
 279                 };
 280
 281                 periphs: periphs@c8834000 {
 282                         compatible = "simple-bus";
 283                         reg = <0x0 0xc8834000 0x0 0x2000>;
 284                         #address-cells = <2>;
 285                         #size-cells = <2>;
 286                         ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
 287
 288                         rng {
 289                                 compatible = "amlogic,meson-rng";
 290                                 reg = <0x0 0x0 0x0 0x4>;
 291                         };
 292
 293                         pinctrl_periphs: pinctrl@4b0 {
 294                                 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
 295                                 #address-cells = <2>;
 296                                 #size-cells = <2>;
 297                                 ranges;
 298
 299                                 gpio: bank@4b0 {
 300                                         reg = <0x0 0x004b0 0x0 0x28>,
 301                                               <0x0 0x004e8 0x0 0x14>,
 302                                               <0x0 0x00120 0x0 0x14>,
 303                                               <0x0 0x00430 0x0 0x40>;
 304                                         reg-names = "mux", "pull", "pull-enable", "gpio";
 305                                         gpio-controller;
 306                                         #gpio-cells = <2>;
 307                                 };
 308
 309                                 emmc_pins: emmc {
 310                                         mux {
 311                                                 groups = "emmc_nand_d07",
 312                                                        "emmc_cmd",
 313                                                        "emmc_clk";
 314                                                 function = "emmc";
 315                                         };
 316                                 };
 317
 318                                 sdcard_pins: sdcard {
 319                                         mux {
 320                                                 groups = "sdcard_d0",
 321                                                        "sdcard_d1",
 322                                                        "sdcard_d2",
 323                                                        "sdcard_d3",
 324                                                        "sdcard_cmd",
 325                                                        "sdcard_clk";
 326                                                 function = "sdcard";
 327                                         };
 328                                 };
 329
 330                                 uart_a_pins: uart_a {
 331                                         mux {
 332                                                 groups = "uart_tx_a",
 333                                                        "uart_rx_a";
 334                                                 function = "uart_a";
 335                                         };
 336                                 };
 337
 338                                 uart_b_pins: uart_b {
 339                                         mux {
 340                                                 groups = "uart_tx_b",
 341                                                        "uart_rx_b";
 342                                                 function = "uart_b";
 343                                         };
 344                                 };
 345
 346                                 uart_c_pins: uart_c {
 347                                         mux {
 348                                                 groups = "uart_tx_c",
 349                                                        "uart_rx_c";
 350                                                 function = "uart_c";
 351                                         };
 352                                 };
 353
 354                                 eth_pins: eth_c {
 355                                         mux {
 356                                                 groups = "eth_mdio",
 357                                                        "eth_mdc",
 358                                                        "eth_clk_rx_clk",
 359                                                        "eth_rx_dv",
 360                                                        "eth_rxd0",
 361                                                        "eth_rxd1",
 362                                                        "eth_rxd2",
 363                                                        "eth_rxd3",
 364                                                        "eth_rgmii_tx_clk",
 365                                                        "eth_tx_en",
 366                                                        "eth_txd0",
 367                                                        "eth_txd1",
 368                                                        "eth_txd2",
 369                                                        "eth_txd3";
 370                                                 function = "eth";
 371                                         };
 372                                 };
 373
 374                                 pwm_a_x_pins: pwm_a_x {
 375                                         mux {
 376                                                 groups = "pwm_a_x";
 377                                                 function = "pwm_a_x";
 378                                         };
 379                                 };
 380
 381                                 pwm_a_y_pins: pwm_a_y {
 382                                         mux {
 383                                                 groups = "pwm_a_y";
 384                                                 function = "pwm_a_y";
 385                                         };
 386                                 };
 387
 388                                 pwm_b_pins: pwm_b {
 389                                         mux {
 390                                                 groups = "pwm_b";
 391                                                 function = "pwm_b";
 392                                         };
 393                                 };
 394
 395                                 pwm_d_pins: pwm_d {
 396                                         mux {
 397                                                 groups = "pwm_d";
 398                                                 function = "pwm_d";
 399                                         };
 400                                 };
 401
 402                                 pwm_e_pins: pwm_e {
 403                                         mux {
 404                                                 groups = "pwm_e";
 405                                                 function = "pwm_e";
 406                                         };
 407                                 };
 408
 409                                 pwm_f_x_pins: pwm_f_x {
 410                                         mux {
 411                                                 groups = "pwm_f_x";
 412                                                 function = "pwm_f_x";
 413                                         };
 414                                 };
 415
 416                                 pwm_f_y_pins: pwm_f_y {
 417                                         mux {
 418                                                 groups = "pwm_f_y";
 419                                                 function = "pwm_f_y";
 420                                         };
 421                                 };
 422                         };
 423                 };
 424
 425                 hiubus: hiubus@c883c000 {
 426                         compatible = "simple-bus";
 427                         reg = <0x0 0xc883c000 0x0 0x2000>;
 428                         #address-cells = <2>;
 429                         #size-cells = <2>;
 430                         ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
 431
 432                         clkc: clock-controller@0 {
 433                                 compatible = "amlogic,gxbb-clkc";
 434                                 #clock-cells = <1>;
 435                                 reg = <0x0 0x0 0x0 0x3db>;
 436                         };
 437                 };
 438
 439                 apb: apb@d0000000 {
 440                         compatible = "simple-bus";
 441                         reg = <0x0 0xd0000000 0x0 0x200000>;
 442                         #address-cells = <2>;
 443                         #size-cells = <2>;
 444                         ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
 445                 };
 446
 447                 ethmac: ethernet@c9410000 {
 448                         compatible = "amlogic,meson6-dwmac", "snps,dwmac";
 449                         reg = <0x0 0xc9410000 0x0 0x10000
 450                                0x0 0xc8834540 0x0 0x4>;
 451                         interrupts = <0 8 1>;
 452                         interrupt-names = "macirq";
 453                         clocks = <&clkc CLKID_ETH>;
 454                         clock-names = "stmmaceth";
 455                         phy-mode = "rgmii";
 456                         status = "disabled";
 457                 };
 458         };
 459 };