2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,potenza", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,potenza", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,potenza", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,potenza", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,potenza", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,potenza", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,potenza", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
101 compatible = "simple-bus";
102 #address-cells = <2>;
105 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
108 #address-cells = <2>;
112 compatible = "fixed-clock";
114 clock-frequency = <100000000>;
115 clock-output-names = "refclk";
118 pcppll: pcppll@17000100 {
119 compatible = "apm,xgene-pcppll-clock";
121 clocks = <&refclk 0>;
122 clock-names = "pcppll";
123 reg = <0x0 0x17000100 0x0 0x1000>;
124 clock-output-names = "pcppll";
128 socpll: socpll@17000120 {
129 compatible = "apm,xgene-socpll-clock";
131 clocks = <&refclk 0>;
132 clock-names = "socpll";
133 reg = <0x0 0x17000120 0x0 0x1000>;
134 clock-output-names = "socpll";
138 socplldiv2: socplldiv2 {
139 compatible = "fixed-factor-clock";
141 clocks = <&socpll 0>;
142 clock-names = "socplldiv2";
145 clock-output-names = "socplldiv2";
149 compatible = "apm,xgene-device-clock";
151 clocks = <&socplldiv2 0>;
152 clock-names = "qmlclk";
153 reg = <0x0 0x1703C000 0x0 0x1000>;
154 reg-names = "csr-reg";
155 clock-output-names = "qmlclk";
159 compatible = "apm,xgene-device-clock";
161 clocks = <&socplldiv2 0>;
162 clock-names = "ethclk";
163 reg = <0x0 0x17000000 0x0 0x1000>;
164 reg-names = "div-reg";
165 divider-offset = <0x238>;
166 divider-width = <0x9>;
167 divider-shift = <0x0>;
168 clock-output-names = "ethclk";
172 compatible = "apm,xgene-device-clock";
174 clocks = <ðclk 0>;
175 reg = <0x0 0x1702C000 0x0 0x1000>;
176 reg-names = "csr-reg";
177 clock-output-names = "menetclk";
180 sge0clk: sge0clk@1f21c000 {
181 compatible = "apm,xgene-device-clock";
183 clocks = <&socplldiv2 0>;
184 reg = <0x0 0x1f21c000 0x0 0x1000>;
185 reg-names = "csr-reg";
187 clock-output-names = "sge0clk";
190 xge0clk: xge0clk@1f61c000 {
191 compatible = "apm,xgene-device-clock";
193 clocks = <&socplldiv2 0>;
194 reg = <0x0 0x1f61c000 0x0 0x1000>;
195 reg-names = "csr-reg";
197 clock-output-names = "xge0clk";
200 sataphy1clk: sataphy1clk@1f21c000 {
201 compatible = "apm,xgene-device-clock";
203 clocks = <&socplldiv2 0>;
204 reg = <0x0 0x1f21c000 0x0 0x1000>;
205 reg-names = "csr-reg";
206 clock-output-names = "sataphy1clk";
210 enable-offset = <0x0>;
211 enable-mask = <0x06>;
214 sataphy2clk: sataphy1clk@1f22c000 {
215 compatible = "apm,xgene-device-clock";
217 clocks = <&socplldiv2 0>;
218 reg = <0x0 0x1f22c000 0x0 0x1000>;
219 reg-names = "csr-reg";
220 clock-output-names = "sataphy2clk";
224 enable-offset = <0x0>;
225 enable-mask = <0x06>;
228 sataphy3clk: sataphy1clk@1f23c000 {
229 compatible = "apm,xgene-device-clock";
231 clocks = <&socplldiv2 0>;
232 reg = <0x0 0x1f23c000 0x0 0x1000>;
233 reg-names = "csr-reg";
234 clock-output-names = "sataphy3clk";
238 enable-offset = <0x0>;
239 enable-mask = <0x06>;
242 sata01clk: sata01clk@1f21c000 {
243 compatible = "apm,xgene-device-clock";
245 clocks = <&socplldiv2 0>;
246 reg = <0x0 0x1f21c000 0x0 0x1000>;
247 reg-names = "csr-reg";
248 clock-output-names = "sata01clk";
251 enable-offset = <0x0>;
252 enable-mask = <0x39>;
255 sata23clk: sata23clk@1f22c000 {
256 compatible = "apm,xgene-device-clock";
258 clocks = <&socplldiv2 0>;
259 reg = <0x0 0x1f22c000 0x0 0x1000>;
260 reg-names = "csr-reg";
261 clock-output-names = "sata23clk";
264 enable-offset = <0x0>;
265 enable-mask = <0x39>;
268 sata45clk: sata45clk@1f23c000 {
269 compatible = "apm,xgene-device-clock";
271 clocks = <&socplldiv2 0>;
272 reg = <0x0 0x1f23c000 0x0 0x1000>;
273 reg-names = "csr-reg";
274 clock-output-names = "sata45clk";
277 enable-offset = <0x0>;
278 enable-mask = <0x39>;
281 rtcclk: rtcclk@17000000 {
282 compatible = "apm,xgene-device-clock";
284 clocks = <&socplldiv2 0>;
285 reg = <0x0 0x17000000 0x0 0x2000>;
286 reg-names = "csr-reg";
289 enable-offset = <0x10>;
291 clock-output-names = "rtcclk";
294 rngpkaclk: rngpkaclk@17000000 {
295 compatible = "apm,xgene-device-clock";
297 clocks = <&socplldiv2 0>;
298 reg = <0x0 0x17000000 0x0 0x2000>;
299 reg-names = "csr-reg";
302 enable-offset = <0x10>;
303 enable-mask = <0x10>;
304 clock-output-names = "rngpkaclk";
307 pcie0clk: pcie0clk@1f2bc000 {
309 compatible = "apm,xgene-device-clock";
311 clocks = <&socplldiv2 0>;
312 reg = <0x0 0x1f2bc000 0x0 0x1000>;
313 reg-names = "csr-reg";
314 clock-output-names = "pcie0clk";
317 pcie1clk: pcie1clk@1f2cc000 {
319 compatible = "apm,xgene-device-clock";
321 clocks = <&socplldiv2 0>;
322 reg = <0x0 0x1f2cc000 0x0 0x1000>;
323 reg-names = "csr-reg";
324 clock-output-names = "pcie1clk";
327 pcie2clk: pcie2clk@1f2dc000 {
329 compatible = "apm,xgene-device-clock";
331 clocks = <&socplldiv2 0>;
332 reg = <0x0 0x1f2dc000 0x0 0x1000>;
333 reg-names = "csr-reg";
334 clock-output-names = "pcie2clk";
337 pcie3clk: pcie3clk@1f50c000 {
339 compatible = "apm,xgene-device-clock";
341 clocks = <&socplldiv2 0>;
342 reg = <0x0 0x1f50c000 0x0 0x1000>;
343 reg-names = "csr-reg";
344 clock-output-names = "pcie3clk";
347 pcie4clk: pcie4clk@1f51c000 {
349 compatible = "apm,xgene-device-clock";
351 clocks = <&socplldiv2 0>;
352 reg = <0x0 0x1f51c000 0x0 0x1000>;
353 reg-names = "csr-reg";
354 clock-output-names = "pcie4clk";
357 dmaclk: dmaclk@1f27c000 {
358 compatible = "apm,xgene-device-clock";
360 clocks = <&socplldiv2 0>;
361 reg = <0x0 0x1f27c000 0x0 0x1000>;
362 reg-names = "csr-reg";
363 clock-output-names = "dmaclk";
367 pcie0: pcie@1f2b0000 {
370 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
371 #interrupt-cells = <1>;
373 #address-cells = <3>;
374 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
375 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
376 reg-names = "csr", "cfg";
377 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
378 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
379 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
380 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
381 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
382 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
383 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
384 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
385 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
387 clocks = <&pcie0clk 0>;
390 pcie1: pcie@1f2c0000 {
393 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
394 #interrupt-cells = <1>;
396 #address-cells = <3>;
397 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
398 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
399 reg-names = "csr", "cfg";
400 ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
401 0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
402 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
403 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
404 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
405 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
406 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
407 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
408 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
410 clocks = <&pcie1clk 0>;
413 pcie2: pcie@1f2d0000 {
416 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
417 #interrupt-cells = <1>;
419 #address-cells = <3>;
420 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
421 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
422 reg-names = "csr", "cfg";
423 ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000 /* io */
424 0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
425 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
426 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
427 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
428 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
429 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
430 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
431 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
433 clocks = <&pcie2clk 0>;
436 pcie3: pcie@1f500000 {
439 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
440 #interrupt-cells = <1>;
442 #address-cells = <3>;
443 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
444 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
445 reg-names = "csr", "cfg";
446 ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000 /* io */
447 0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem */
448 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
449 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
450 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
451 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
452 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
453 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
454 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
456 clocks = <&pcie3clk 0>;
459 pcie4: pcie@1f510000 {
462 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
463 #interrupt-cells = <1>;
465 #address-cells = <3>;
466 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
467 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
468 reg-names = "csr", "cfg";
469 ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000 /* io */
470 0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */
471 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
472 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
473 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
474 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
475 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
476 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
477 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
479 clocks = <&pcie4clk 0>;
482 serial0: serial@1c020000 {
484 device_type = "serial";
485 compatible = "ns16550a";
486 reg = <0 0x1c020000 0x0 0x1000>;
488 clock-frequency = <10000000>; /* Updated by bootloader */
489 interrupt-parent = <&gic>;
490 interrupts = <0x0 0x4c 0x4>;
493 serial1: serial@1c021000 {
495 device_type = "serial";
496 compatible = "ns16550a";
497 reg = <0 0x1c021000 0x0 0x1000>;
499 clock-frequency = <10000000>; /* Updated by bootloader */
500 interrupt-parent = <&gic>;
501 interrupts = <0x0 0x4d 0x4>;
504 serial2: serial@1c022000 {
506 device_type = "serial";
507 compatible = "ns16550a";
508 reg = <0 0x1c022000 0x0 0x1000>;
510 clock-frequency = <10000000>; /* Updated by bootloader */
511 interrupt-parent = <&gic>;
512 interrupts = <0x0 0x4e 0x4>;
515 serial3: serial@1c023000 {
517 device_type = "serial";
518 compatible = "ns16550a";
519 reg = <0 0x1c023000 0x0 0x1000>;
521 clock-frequency = <10000000>; /* Updated by bootloader */
522 interrupt-parent = <&gic>;
523 interrupts = <0x0 0x4f 0x4>;
527 compatible = "apm,xgene-phy";
528 reg = <0x0 0x1f21a000 0x0 0x100>;
530 clocks = <&sataphy1clk 0>;
532 apm,tx-boost-gain = <30 30 30 30 30 30>;
533 apm,tx-eye-tuning = <2 10 10 2 10 10>;
537 compatible = "apm,xgene-phy";
538 reg = <0x0 0x1f22a000 0x0 0x100>;
540 clocks = <&sataphy2clk 0>;
542 apm,tx-boost-gain = <30 30 30 30 30 30>;
543 apm,tx-eye-tuning = <1 10 10 2 10 10>;
547 compatible = "apm,xgene-phy";
548 reg = <0x0 0x1f23a000 0x0 0x100>;
550 clocks = <&sataphy3clk 0>;
552 apm,tx-boost-gain = <31 31 31 31 31 31>;
553 apm,tx-eye-tuning = <2 10 10 2 10 10>;
556 sata1: sata@1a000000 {
557 compatible = "apm,xgene-ahci";
558 reg = <0x0 0x1a000000 0x0 0x1000>,
559 <0x0 0x1f210000 0x0 0x1000>,
560 <0x0 0x1f21d000 0x0 0x1000>,
561 <0x0 0x1f21e000 0x0 0x1000>,
562 <0x0 0x1f217000 0x0 0x1000>;
563 interrupts = <0x0 0x86 0x4>;
566 clocks = <&sata01clk 0>;
568 phy-names = "sata-phy";
571 sata2: sata@1a400000 {
572 compatible = "apm,xgene-ahci";
573 reg = <0x0 0x1a400000 0x0 0x1000>,
574 <0x0 0x1f220000 0x0 0x1000>,
575 <0x0 0x1f22d000 0x0 0x1000>,
576 <0x0 0x1f22e000 0x0 0x1000>,
577 <0x0 0x1f227000 0x0 0x1000>;
578 interrupts = <0x0 0x87 0x4>;
581 clocks = <&sata23clk 0>;
583 phy-names = "sata-phy";
586 sata3: sata@1a800000 {
587 compatible = "apm,xgene-ahci";
588 reg = <0x0 0x1a800000 0x0 0x1000>,
589 <0x0 0x1f230000 0x0 0x1000>,
590 <0x0 0x1f23d000 0x0 0x1000>,
591 <0x0 0x1f23e000 0x0 0x1000>;
592 interrupts = <0x0 0x88 0x4>;
595 clocks = <&sata45clk 0>;
597 phy-names = "sata-phy";
601 compatible = "apm,xgene-rtc";
602 reg = <0x0 0x10510000 0x0 0x400>;
603 interrupts = <0x0 0x46 0x4>;
605 clocks = <&rtcclk 0>;
608 menet: ethernet@17020000 {
609 compatible = "apm,xgene-enet";
611 reg = <0x0 0x17020000 0x0 0xd100>,
612 <0x0 0X17030000 0x0 0Xc300>,
613 <0x0 0X10000000 0x0 0X200>;
614 reg-names = "enet_csr", "ring_csr", "ring_cmd";
615 interrupts = <0x0 0x3c 0x4>;
617 clocks = <&menetclk 0>;
618 /* mac address will be overwritten by the bootloader */
619 local-mac-address = [00 00 00 00 00 00];
620 phy-connection-type = "rgmii";
621 phy-handle = <&menetphy>;
623 compatible = "apm,xgene-mdio";
624 #address-cells = <1>;
626 menetphy: menetphy@3 {
627 compatible = "ethernet-phy-id001c.c915";
634 sgenet0: ethernet@1f210000 {
635 compatible = "apm,xgene1-sgenet";
637 reg = <0x0 0x1f210000 0x0 0xd100>,
638 <0x0 0x1f200000 0x0 0Xc300>,
639 <0x0 0x1B000000 0x0 0X200>;
640 reg-names = "enet_csr", "ring_csr", "ring_cmd";
641 interrupts = <0x0 0xA0 0x4>;
643 clocks = <&sge0clk 0>;
644 local-mac-address = [00 00 00 00 00 00];
645 phy-connection-type = "sgmii";
648 xgenet: ethernet@1f610000 {
649 compatible = "apm,xgene1-xgenet";
651 reg = <0x0 0x1f610000 0x0 0xd100>,
652 <0x0 0x1f600000 0x0 0Xc300>,
653 <0x0 0x18000000 0x0 0X200>;
654 reg-names = "enet_csr", "ring_csr", "ring_cmd";
655 interrupts = <0x0 0x60 0x4>;
657 clocks = <&xge0clk 0>;
658 /* mac address will be overwritten by the bootloader */
659 local-mac-address = [00 00 00 00 00 00];
660 phy-connection-type = "xgmii";
664 compatible = "apm,xgene-rng";
665 reg = <0x0 0x10520000 0x0 0x100>;
666 interrupts = <0x0 0x41 0x4>;
667 clocks = <&rngpkaclk 0>;
671 compatible = "apm,xgene-storm-dma";
673 reg = <0x0 0x1f270000 0x0 0x10000>,
674 <0x0 0x1f200000 0x0 0x10000>,
675 <0x0 0x1b008000 0x0 0x2000>,
676 <0x0 0x1054a000 0x0 0x100>;
677 interrupts = <0x0 0x82 0x4>,
683 clocks = <&dmaclk 0>;