2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,potenza", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,potenza", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,potenza", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,potenza", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,potenza", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,potenza", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,potenza", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
101 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
102 interrupts = <1 12 0xff04>;
106 compatible = "simple-bus";
107 #address-cells = <2>;
110 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
113 #address-cells = <2>;
117 compatible = "fixed-clock";
119 clock-frequency = <100000000>;
120 clock-output-names = "refclk";
123 pcppll: pcppll@17000100 {
124 compatible = "apm,xgene-pcppll-clock";
126 clocks = <&refclk 0>;
127 clock-names = "pcppll";
128 reg = <0x0 0x17000100 0x0 0x1000>;
129 clock-output-names = "pcppll";
133 socpll: socpll@17000120 {
134 compatible = "apm,xgene-socpll-clock";
136 clocks = <&refclk 0>;
137 clock-names = "socpll";
138 reg = <0x0 0x17000120 0x0 0x1000>;
139 clock-output-names = "socpll";
143 socplldiv2: socplldiv2 {
144 compatible = "fixed-factor-clock";
146 clocks = <&socpll 0>;
147 clock-names = "socplldiv2";
150 clock-output-names = "socplldiv2";
154 compatible = "apm,xgene-device-clock";
156 clocks = <&socplldiv2 0>;
157 clock-names = "qmlclk";
158 reg = <0x0 0x1703C000 0x0 0x1000>;
159 reg-names = "csr-reg";
160 clock-output-names = "qmlclk";
164 compatible = "apm,xgene-device-clock";
166 clocks = <&socplldiv2 0>;
167 clock-names = "ethclk";
168 reg = <0x0 0x17000000 0x0 0x1000>;
169 reg-names = "div-reg";
170 divider-offset = <0x238>;
171 divider-width = <0x9>;
172 divider-shift = <0x0>;
173 clock-output-names = "ethclk";
177 compatible = "apm,xgene-device-clock";
179 clocks = <ðclk 0>;
180 reg = <0x0 0x1702C000 0x0 0x1000>;
181 reg-names = "csr-reg";
182 clock-output-names = "menetclk";
185 sge0clk: sge0clk@1f21c000 {
186 compatible = "apm,xgene-device-clock";
188 clocks = <&socplldiv2 0>;
189 reg = <0x0 0x1f21c000 0x0 0x1000>;
190 reg-names = "csr-reg";
192 clock-output-names = "sge0clk";
195 sge1clk: sge1clk@1f21c000 {
196 compatible = "apm,xgene-device-clock";
198 clocks = <&socplldiv2 0>;
199 reg = <0x0 0x1f21c000 0x0 0x1000>;
200 reg-names = "csr-reg";
202 clock-output-names = "sge1clk";
205 xge0clk: xge0clk@1f61c000 {
206 compatible = "apm,xgene-device-clock";
208 clocks = <&socplldiv2 0>;
209 reg = <0x0 0x1f61c000 0x0 0x1000>;
210 reg-names = "csr-reg";
212 clock-output-names = "xge0clk";
215 sataphy1clk: sataphy1clk@1f21c000 {
216 compatible = "apm,xgene-device-clock";
218 clocks = <&socplldiv2 0>;
219 reg = <0x0 0x1f21c000 0x0 0x1000>;
220 reg-names = "csr-reg";
221 clock-output-names = "sataphy1clk";
225 enable-offset = <0x0>;
226 enable-mask = <0x06>;
229 sataphy2clk: sataphy1clk@1f22c000 {
230 compatible = "apm,xgene-device-clock";
232 clocks = <&socplldiv2 0>;
233 reg = <0x0 0x1f22c000 0x0 0x1000>;
234 reg-names = "csr-reg";
235 clock-output-names = "sataphy2clk";
239 enable-offset = <0x0>;
240 enable-mask = <0x06>;
243 sataphy3clk: sataphy1clk@1f23c000 {
244 compatible = "apm,xgene-device-clock";
246 clocks = <&socplldiv2 0>;
247 reg = <0x0 0x1f23c000 0x0 0x1000>;
248 reg-names = "csr-reg";
249 clock-output-names = "sataphy3clk";
253 enable-offset = <0x0>;
254 enable-mask = <0x06>;
257 sata01clk: sata01clk@1f21c000 {
258 compatible = "apm,xgene-device-clock";
260 clocks = <&socplldiv2 0>;
261 reg = <0x0 0x1f21c000 0x0 0x1000>;
262 reg-names = "csr-reg";
263 clock-output-names = "sata01clk";
266 enable-offset = <0x0>;
267 enable-mask = <0x39>;
270 sata23clk: sata23clk@1f22c000 {
271 compatible = "apm,xgene-device-clock";
273 clocks = <&socplldiv2 0>;
274 reg = <0x0 0x1f22c000 0x0 0x1000>;
275 reg-names = "csr-reg";
276 clock-output-names = "sata23clk";
279 enable-offset = <0x0>;
280 enable-mask = <0x39>;
283 sata45clk: sata45clk@1f23c000 {
284 compatible = "apm,xgene-device-clock";
286 clocks = <&socplldiv2 0>;
287 reg = <0x0 0x1f23c000 0x0 0x1000>;
288 reg-names = "csr-reg";
289 clock-output-names = "sata45clk";
292 enable-offset = <0x0>;
293 enable-mask = <0x39>;
296 rtcclk: rtcclk@17000000 {
297 compatible = "apm,xgene-device-clock";
299 clocks = <&socplldiv2 0>;
300 reg = <0x0 0x17000000 0x0 0x2000>;
301 reg-names = "csr-reg";
304 enable-offset = <0x10>;
306 clock-output-names = "rtcclk";
309 rngpkaclk: rngpkaclk@17000000 {
310 compatible = "apm,xgene-device-clock";
312 clocks = <&socplldiv2 0>;
313 reg = <0x0 0x17000000 0x0 0x2000>;
314 reg-names = "csr-reg";
317 enable-offset = <0x10>;
318 enable-mask = <0x10>;
319 clock-output-names = "rngpkaclk";
322 pcie0clk: pcie0clk@1f2bc000 {
324 compatible = "apm,xgene-device-clock";
326 clocks = <&socplldiv2 0>;
327 reg = <0x0 0x1f2bc000 0x0 0x1000>;
328 reg-names = "csr-reg";
329 clock-output-names = "pcie0clk";
332 pcie1clk: pcie1clk@1f2cc000 {
334 compatible = "apm,xgene-device-clock";
336 clocks = <&socplldiv2 0>;
337 reg = <0x0 0x1f2cc000 0x0 0x1000>;
338 reg-names = "csr-reg";
339 clock-output-names = "pcie1clk";
342 pcie2clk: pcie2clk@1f2dc000 {
344 compatible = "apm,xgene-device-clock";
346 clocks = <&socplldiv2 0>;
347 reg = <0x0 0x1f2dc000 0x0 0x1000>;
348 reg-names = "csr-reg";
349 clock-output-names = "pcie2clk";
352 pcie3clk: pcie3clk@1f50c000 {
354 compatible = "apm,xgene-device-clock";
356 clocks = <&socplldiv2 0>;
357 reg = <0x0 0x1f50c000 0x0 0x1000>;
358 reg-names = "csr-reg";
359 clock-output-names = "pcie3clk";
362 pcie4clk: pcie4clk@1f51c000 {
364 compatible = "apm,xgene-device-clock";
366 clocks = <&socplldiv2 0>;
367 reg = <0x0 0x1f51c000 0x0 0x1000>;
368 reg-names = "csr-reg";
369 clock-output-names = "pcie4clk";
372 dmaclk: dmaclk@1f27c000 {
373 compatible = "apm,xgene-device-clock";
375 clocks = <&socplldiv2 0>;
376 reg = <0x0 0x1f27c000 0x0 0x1000>;
377 reg-names = "csr-reg";
378 clock-output-names = "dmaclk";
383 compatible = "apm,xgene1-msi";
385 reg = <0x00 0x79000000 0x0 0x900000>;
386 interrupts = < 0x0 0x10 0x4
404 scu: system-clk-controller@17000000 {
405 compatible = "apm,xgene-scu","syscon";
406 reg = <0x0 0x17000000 0x0 0x400>;
409 reboot: reboot@17000014 {
410 compatible = "syscon-reboot";
417 compatible = "apm,xgene-csw", "syscon";
418 reg = <0x0 0x7e200000 0x0 0x1000>;
421 mcba: mcba@7e700000 {
422 compatible = "apm,xgene-mcb", "syscon";
423 reg = <0x0 0x7e700000 0x0 0x1000>;
426 mcbb: mcbb@7e720000 {
427 compatible = "apm,xgene-mcb", "syscon";
428 reg = <0x0 0x7e720000 0x0 0x1000>;
431 efuse: efuse@1054a000 {
432 compatible = "apm,xgene-efuse", "syscon";
433 reg = <0x0 0x1054a000 0x0 0x20>;
437 compatible = "apm,xgene-edac";
438 #address-cells = <2>;
442 regmap-mcba = <&mcba>;
443 regmap-mcbb = <&mcbb>;
444 regmap-efuse = <&efuse>;
445 reg = <0x0 0x78800000 0x0 0x100>;
446 interrupts = <0x0 0x20 0x4>,
451 compatible = "apm,xgene-edac-mc";
452 reg = <0x0 0x7e800000 0x0 0x1000>;
453 memory-controller = <0>;
457 compatible = "apm,xgene-edac-mc";
458 reg = <0x0 0x7e840000 0x0 0x1000>;
459 memory-controller = <1>;
463 compatible = "apm,xgene-edac-mc";
464 reg = <0x0 0x7e880000 0x0 0x1000>;
465 memory-controller = <2>;
469 compatible = "apm,xgene-edac-mc";
470 reg = <0x0 0x7e8c0000 0x0 0x1000>;
471 memory-controller = <3>;
475 compatible = "apm,xgene-edac-pmd";
476 reg = <0x0 0x7c000000 0x0 0x200000>;
477 pmd-controller = <0>;
481 compatible = "apm,xgene-edac-pmd";
482 reg = <0x0 0x7c200000 0x0 0x200000>;
483 pmd-controller = <1>;
487 compatible = "apm,xgene-edac-pmd";
488 reg = <0x0 0x7c400000 0x0 0x200000>;
489 pmd-controller = <2>;
493 compatible = "apm,xgene-edac-pmd";
494 reg = <0x0 0x7c600000 0x0 0x200000>;
495 pmd-controller = <3>;
499 pcie0: pcie@1f2b0000 {
502 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
503 #interrupt-cells = <1>;
505 #address-cells = <3>;
506 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
507 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
508 reg-names = "csr", "cfg";
509 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
510 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
511 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
512 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
513 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
514 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
515 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
516 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
517 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
518 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
520 clocks = <&pcie0clk 0>;
524 pcie1: pcie@1f2c0000 {
527 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
528 #interrupt-cells = <1>;
530 #address-cells = <3>;
531 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
532 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
533 reg-names = "csr", "cfg";
534 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
535 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
536 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
537 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
538 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
539 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
540 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
541 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
542 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
543 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
545 clocks = <&pcie1clk 0>;
549 pcie2: pcie@1f2d0000 {
552 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
553 #interrupt-cells = <1>;
555 #address-cells = <3>;
556 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
557 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
558 reg-names = "csr", "cfg";
559 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
560 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
561 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
562 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
563 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
564 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
565 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
566 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
567 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
568 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
570 clocks = <&pcie2clk 0>;
574 pcie3: pcie@1f500000 {
577 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
578 #interrupt-cells = <1>;
580 #address-cells = <3>;
581 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
582 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
583 reg-names = "csr", "cfg";
584 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
585 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
586 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
587 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
588 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
589 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
590 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
591 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
592 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
593 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
595 clocks = <&pcie3clk 0>;
599 pcie4: pcie@1f510000 {
602 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
603 #interrupt-cells = <1>;
605 #address-cells = <3>;
606 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
607 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
608 reg-names = "csr", "cfg";
609 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
610 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
611 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
612 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
613 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
614 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
615 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
616 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
617 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
618 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
620 clocks = <&pcie4clk 0>;
624 serial0: serial@1c020000 {
626 device_type = "serial";
627 compatible = "ns16550a";
628 reg = <0 0x1c020000 0x0 0x1000>;
630 clock-frequency = <10000000>; /* Updated by bootloader */
631 interrupt-parent = <&gic>;
632 interrupts = <0x0 0x4c 0x4>;
635 serial1: serial@1c021000 {
637 device_type = "serial";
638 compatible = "ns16550a";
639 reg = <0 0x1c021000 0x0 0x1000>;
641 clock-frequency = <10000000>; /* Updated by bootloader */
642 interrupt-parent = <&gic>;
643 interrupts = <0x0 0x4d 0x4>;
646 serial2: serial@1c022000 {
648 device_type = "serial";
649 compatible = "ns16550a";
650 reg = <0 0x1c022000 0x0 0x1000>;
652 clock-frequency = <10000000>; /* Updated by bootloader */
653 interrupt-parent = <&gic>;
654 interrupts = <0x0 0x4e 0x4>;
657 serial3: serial@1c023000 {
659 device_type = "serial";
660 compatible = "ns16550a";
661 reg = <0 0x1c023000 0x0 0x1000>;
663 clock-frequency = <10000000>; /* Updated by bootloader */
664 interrupt-parent = <&gic>;
665 interrupts = <0x0 0x4f 0x4>;
669 compatible = "apm,xgene-phy";
670 reg = <0x0 0x1f21a000 0x0 0x100>;
672 clocks = <&sataphy1clk 0>;
674 apm,tx-boost-gain = <30 30 30 30 30 30>;
675 apm,tx-eye-tuning = <2 10 10 2 10 10>;
679 compatible = "apm,xgene-phy";
680 reg = <0x0 0x1f22a000 0x0 0x100>;
682 clocks = <&sataphy2clk 0>;
684 apm,tx-boost-gain = <30 30 30 30 30 30>;
685 apm,tx-eye-tuning = <1 10 10 2 10 10>;
689 compatible = "apm,xgene-phy";
690 reg = <0x0 0x1f23a000 0x0 0x100>;
692 clocks = <&sataphy3clk 0>;
694 apm,tx-boost-gain = <31 31 31 31 31 31>;
695 apm,tx-eye-tuning = <2 10 10 2 10 10>;
698 sata1: sata@1a000000 {
699 compatible = "apm,xgene-ahci";
700 reg = <0x0 0x1a000000 0x0 0x1000>,
701 <0x0 0x1f210000 0x0 0x1000>,
702 <0x0 0x1f21d000 0x0 0x1000>,
703 <0x0 0x1f21e000 0x0 0x1000>,
704 <0x0 0x1f217000 0x0 0x1000>;
705 interrupts = <0x0 0x86 0x4>;
708 clocks = <&sata01clk 0>;
710 phy-names = "sata-phy";
713 sata2: sata@1a400000 {
714 compatible = "apm,xgene-ahci";
715 reg = <0x0 0x1a400000 0x0 0x1000>,
716 <0x0 0x1f220000 0x0 0x1000>,
717 <0x0 0x1f22d000 0x0 0x1000>,
718 <0x0 0x1f22e000 0x0 0x1000>,
719 <0x0 0x1f227000 0x0 0x1000>;
720 interrupts = <0x0 0x87 0x4>;
723 clocks = <&sata23clk 0>;
725 phy-names = "sata-phy";
728 sata3: sata@1a800000 {
729 compatible = "apm,xgene-ahci";
730 reg = <0x0 0x1a800000 0x0 0x1000>,
731 <0x0 0x1f230000 0x0 0x1000>,
732 <0x0 0x1f23d000 0x0 0x1000>,
733 <0x0 0x1f23e000 0x0 0x1000>;
734 interrupts = <0x0 0x88 0x4>;
737 clocks = <&sata45clk 0>;
739 phy-names = "sata-phy";
742 sbgpio: sbgpio@17001000{
743 compatible = "apm,xgene-gpio-sb";
744 reg = <0x0 0x17001000 0x0 0x400>;
747 interrupts = <0x0 0x28 0x1>,
756 compatible = "apm,xgene-rtc";
757 reg = <0x0 0x10510000 0x0 0x400>;
758 interrupts = <0x0 0x46 0x4>;
760 clocks = <&rtcclk 0>;
763 menet: ethernet@17020000 {
764 compatible = "apm,xgene-enet";
766 reg = <0x0 0x17020000 0x0 0xd100>,
767 <0x0 0X17030000 0x0 0Xc300>,
768 <0x0 0X10000000 0x0 0X200>;
769 reg-names = "enet_csr", "ring_csr", "ring_cmd";
770 interrupts = <0x0 0x3c 0x4>;
772 clocks = <&menetclk 0>;
773 /* mac address will be overwritten by the bootloader */
774 local-mac-address = [00 00 00 00 00 00];
775 phy-connection-type = "rgmii";
776 phy-handle = <&menetphy>;
778 compatible = "apm,xgene-mdio";
779 #address-cells = <1>;
781 menetphy: menetphy@3 {
782 compatible = "ethernet-phy-id001c.c915";
789 sgenet0: ethernet@1f210000 {
790 compatible = "apm,xgene1-sgenet";
792 reg = <0x0 0x1f210000 0x0 0xd100>,
793 <0x0 0x1f200000 0x0 0Xc300>,
794 <0x0 0x1B000000 0x0 0X200>;
795 reg-names = "enet_csr", "ring_csr", "ring_cmd";
796 interrupts = <0x0 0xA0 0x4>,
799 clocks = <&sge0clk 0>;
800 local-mac-address = [00 00 00 00 00 00];
801 phy-connection-type = "sgmii";
804 sgenet1: ethernet@1f210030 {
805 compatible = "apm,xgene1-sgenet";
807 reg = <0x0 0x1f210030 0x0 0xd100>,
808 <0x0 0x1f200000 0x0 0Xc300>,
809 <0x0 0x1B000000 0x0 0X8000>;
810 reg-names = "enet_csr", "ring_csr", "ring_cmd";
811 interrupts = <0x0 0xAC 0x4>,
815 clocks = <&sge1clk 0>;
816 local-mac-address = [00 00 00 00 00 00];
817 phy-connection-type = "sgmii";
820 xgenet: ethernet@1f610000 {
821 compatible = "apm,xgene1-xgenet";
823 reg = <0x0 0x1f610000 0x0 0xd100>,
824 <0x0 0x1f600000 0x0 0Xc300>,
825 <0x0 0x18000000 0x0 0X200>;
826 reg-names = "enet_csr", "ring_csr", "ring_cmd";
827 interrupts = <0x0 0x60 0x4>,
830 clocks = <&xge0clk 0>;
831 /* mac address will be overwritten by the bootloader */
832 local-mac-address = [00 00 00 00 00 00];
833 phy-connection-type = "xgmii";
837 compatible = "apm,xgene-rng";
838 reg = <0x0 0x10520000 0x0 0x100>;
839 interrupts = <0x0 0x41 0x4>;
840 clocks = <&rngpkaclk 0>;
844 compatible = "apm,xgene-storm-dma";
846 reg = <0x0 0x1f270000 0x0 0x10000>,
847 <0x0 0x1f200000 0x0 0x10000>,
848 <0x0 0x1b000000 0x0 0x400000>,
849 <0x0 0x1054a000 0x0 0x100>;
850 interrupts = <0x0 0x82 0x4>,
856 clocks = <&dmaclk 0>;