2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,potenza", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,potenza", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,potenza", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,potenza", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,potenza", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,potenza", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,potenza", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
101 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
102 interrupts = <1 12 0xff04>;
106 compatible = "simple-bus";
107 #address-cells = <2>;
110 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
113 #address-cells = <2>;
117 compatible = "fixed-clock";
119 clock-frequency = <100000000>;
120 clock-output-names = "refclk";
123 pcppll: pcppll@17000100 {
124 compatible = "apm,xgene-pcppll-clock";
126 clocks = <&refclk 0>;
127 clock-names = "pcppll";
128 reg = <0x0 0x17000100 0x0 0x1000>;
129 clock-output-names = "pcppll";
133 socpll: socpll@17000120 {
134 compatible = "apm,xgene-socpll-clock";
136 clocks = <&refclk 0>;
137 clock-names = "socpll";
138 reg = <0x0 0x17000120 0x0 0x1000>;
139 clock-output-names = "socpll";
143 socplldiv2: socplldiv2 {
144 compatible = "fixed-factor-clock";
146 clocks = <&socpll 0>;
147 clock-names = "socplldiv2";
150 clock-output-names = "socplldiv2";
154 compatible = "apm,xgene-device-clock";
156 clocks = <&socplldiv2 0>;
157 clock-names = "qmlclk";
158 reg = <0x0 0x1703C000 0x0 0x1000>;
159 reg-names = "csr-reg";
160 clock-output-names = "qmlclk";
164 compatible = "apm,xgene-device-clock";
166 clocks = <&socplldiv2 0>;
167 clock-names = "ethclk";
168 reg = <0x0 0x17000000 0x0 0x1000>;
169 reg-names = "div-reg";
170 divider-offset = <0x238>;
171 divider-width = <0x9>;
172 divider-shift = <0x0>;
173 clock-output-names = "ethclk";
177 compatible = "apm,xgene-device-clock";
179 clocks = <ðclk 0>;
180 reg = <0x0 0x1702C000 0x0 0x1000>;
181 reg-names = "csr-reg";
182 clock-output-names = "menetclk";
185 sge0clk: sge0clk@1f21c000 {
186 compatible = "apm,xgene-device-clock";
188 clocks = <&socplldiv2 0>;
189 reg = <0x0 0x1f21c000 0x0 0x1000>;
190 reg-names = "csr-reg";
192 clock-output-names = "sge0clk";
195 sge1clk: sge1clk@1f21c000 {
196 compatible = "apm,xgene-device-clock";
198 clocks = <&socplldiv2 0>;
199 reg = <0x0 0x1f21c000 0x0 0x1000>;
200 reg-names = "csr-reg";
202 clock-output-names = "sge1clk";
205 xge0clk: xge0clk@1f61c000 {
206 compatible = "apm,xgene-device-clock";
208 clocks = <&socplldiv2 0>;
209 reg = <0x0 0x1f61c000 0x0 0x1000>;
210 reg-names = "csr-reg";
212 clock-output-names = "xge0clk";
215 xge1clk: xge1clk@1f62c000 {
216 compatible = "apm,xgene-device-clock";
219 clocks = <&socplldiv2 0>;
220 reg = <0x0 0x1f62c000 0x0 0x1000>;
221 reg-names = "csr-reg";
223 clock-output-names = "xge1clk";
226 sataphy1clk: sataphy1clk@1f21c000 {
227 compatible = "apm,xgene-device-clock";
229 clocks = <&socplldiv2 0>;
230 reg = <0x0 0x1f21c000 0x0 0x1000>;
231 reg-names = "csr-reg";
232 clock-output-names = "sataphy1clk";
236 enable-offset = <0x0>;
237 enable-mask = <0x06>;
240 sataphy2clk: sataphy1clk@1f22c000 {
241 compatible = "apm,xgene-device-clock";
243 clocks = <&socplldiv2 0>;
244 reg = <0x0 0x1f22c000 0x0 0x1000>;
245 reg-names = "csr-reg";
246 clock-output-names = "sataphy2clk";
250 enable-offset = <0x0>;
251 enable-mask = <0x06>;
254 sataphy3clk: sataphy1clk@1f23c000 {
255 compatible = "apm,xgene-device-clock";
257 clocks = <&socplldiv2 0>;
258 reg = <0x0 0x1f23c000 0x0 0x1000>;
259 reg-names = "csr-reg";
260 clock-output-names = "sataphy3clk";
264 enable-offset = <0x0>;
265 enable-mask = <0x06>;
268 sata01clk: sata01clk@1f21c000 {
269 compatible = "apm,xgene-device-clock";
271 clocks = <&socplldiv2 0>;
272 reg = <0x0 0x1f21c000 0x0 0x1000>;
273 reg-names = "csr-reg";
274 clock-output-names = "sata01clk";
277 enable-offset = <0x0>;
278 enable-mask = <0x39>;
281 sata23clk: sata23clk@1f22c000 {
282 compatible = "apm,xgene-device-clock";
284 clocks = <&socplldiv2 0>;
285 reg = <0x0 0x1f22c000 0x0 0x1000>;
286 reg-names = "csr-reg";
287 clock-output-names = "sata23clk";
290 enable-offset = <0x0>;
291 enable-mask = <0x39>;
294 sata45clk: sata45clk@1f23c000 {
295 compatible = "apm,xgene-device-clock";
297 clocks = <&socplldiv2 0>;
298 reg = <0x0 0x1f23c000 0x0 0x1000>;
299 reg-names = "csr-reg";
300 clock-output-names = "sata45clk";
303 enable-offset = <0x0>;
304 enable-mask = <0x39>;
307 rtcclk: rtcclk@17000000 {
308 compatible = "apm,xgene-device-clock";
310 clocks = <&socplldiv2 0>;
311 reg = <0x0 0x17000000 0x0 0x2000>;
312 reg-names = "csr-reg";
315 enable-offset = <0x10>;
317 clock-output-names = "rtcclk";
320 rngpkaclk: rngpkaclk@17000000 {
321 compatible = "apm,xgene-device-clock";
323 clocks = <&socplldiv2 0>;
324 reg = <0x0 0x17000000 0x0 0x2000>;
325 reg-names = "csr-reg";
328 enable-offset = <0x10>;
329 enable-mask = <0x10>;
330 clock-output-names = "rngpkaclk";
333 pcie0clk: pcie0clk@1f2bc000 {
335 compatible = "apm,xgene-device-clock";
337 clocks = <&socplldiv2 0>;
338 reg = <0x0 0x1f2bc000 0x0 0x1000>;
339 reg-names = "csr-reg";
340 clock-output-names = "pcie0clk";
343 pcie1clk: pcie1clk@1f2cc000 {
345 compatible = "apm,xgene-device-clock";
347 clocks = <&socplldiv2 0>;
348 reg = <0x0 0x1f2cc000 0x0 0x1000>;
349 reg-names = "csr-reg";
350 clock-output-names = "pcie1clk";
353 pcie2clk: pcie2clk@1f2dc000 {
355 compatible = "apm,xgene-device-clock";
357 clocks = <&socplldiv2 0>;
358 reg = <0x0 0x1f2dc000 0x0 0x1000>;
359 reg-names = "csr-reg";
360 clock-output-names = "pcie2clk";
363 pcie3clk: pcie3clk@1f50c000 {
365 compatible = "apm,xgene-device-clock";
367 clocks = <&socplldiv2 0>;
368 reg = <0x0 0x1f50c000 0x0 0x1000>;
369 reg-names = "csr-reg";
370 clock-output-names = "pcie3clk";
373 pcie4clk: pcie4clk@1f51c000 {
375 compatible = "apm,xgene-device-clock";
377 clocks = <&socplldiv2 0>;
378 reg = <0x0 0x1f51c000 0x0 0x1000>;
379 reg-names = "csr-reg";
380 clock-output-names = "pcie4clk";
383 dmaclk: dmaclk@1f27c000 {
384 compatible = "apm,xgene-device-clock";
386 clocks = <&socplldiv2 0>;
387 reg = <0x0 0x1f27c000 0x0 0x1000>;
388 reg-names = "csr-reg";
389 clock-output-names = "dmaclk";
394 compatible = "apm,xgene1-msi";
396 reg = <0x00 0x79000000 0x0 0x900000>;
397 interrupts = < 0x0 0x10 0x4
415 scu: system-clk-controller@17000000 {
416 compatible = "apm,xgene-scu","syscon";
417 reg = <0x0 0x17000000 0x0 0x400>;
420 reboot: reboot@17000014 {
421 compatible = "syscon-reboot";
428 compatible = "apm,xgene-csw", "syscon";
429 reg = <0x0 0x7e200000 0x0 0x1000>;
432 mcba: mcba@7e700000 {
433 compatible = "apm,xgene-mcb", "syscon";
434 reg = <0x0 0x7e700000 0x0 0x1000>;
437 mcbb: mcbb@7e720000 {
438 compatible = "apm,xgene-mcb", "syscon";
439 reg = <0x0 0x7e720000 0x0 0x1000>;
442 efuse: efuse@1054a000 {
443 compatible = "apm,xgene-efuse", "syscon";
444 reg = <0x0 0x1054a000 0x0 0x20>;
448 compatible = "apm,xgene-edac";
449 #address-cells = <2>;
453 regmap-mcba = <&mcba>;
454 regmap-mcbb = <&mcbb>;
455 regmap-efuse = <&efuse>;
456 reg = <0x0 0x78800000 0x0 0x100>;
457 interrupts = <0x0 0x20 0x4>,
462 compatible = "apm,xgene-edac-mc";
463 reg = <0x0 0x7e800000 0x0 0x1000>;
464 memory-controller = <0>;
468 compatible = "apm,xgene-edac-mc";
469 reg = <0x0 0x7e840000 0x0 0x1000>;
470 memory-controller = <1>;
474 compatible = "apm,xgene-edac-mc";
475 reg = <0x0 0x7e880000 0x0 0x1000>;
476 memory-controller = <2>;
480 compatible = "apm,xgene-edac-mc";
481 reg = <0x0 0x7e8c0000 0x0 0x1000>;
482 memory-controller = <3>;
486 compatible = "apm,xgene-edac-pmd";
487 reg = <0x0 0x7c000000 0x0 0x200000>;
488 pmd-controller = <0>;
492 compatible = "apm,xgene-edac-pmd";
493 reg = <0x0 0x7c200000 0x0 0x200000>;
494 pmd-controller = <1>;
498 compatible = "apm,xgene-edac-pmd";
499 reg = <0x0 0x7c400000 0x0 0x200000>;
500 pmd-controller = <2>;
504 compatible = "apm,xgene-edac-pmd";
505 reg = <0x0 0x7c600000 0x0 0x200000>;
506 pmd-controller = <3>;
510 pcie0: pcie@1f2b0000 {
513 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
514 #interrupt-cells = <1>;
516 #address-cells = <3>;
517 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
518 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
519 reg-names = "csr", "cfg";
520 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
521 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
522 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
523 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
524 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
525 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
526 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
527 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
528 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
529 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
531 clocks = <&pcie0clk 0>;
535 pcie1: pcie@1f2c0000 {
538 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
539 #interrupt-cells = <1>;
541 #address-cells = <3>;
542 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
543 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
544 reg-names = "csr", "cfg";
545 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
546 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
547 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
548 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
549 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
550 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
551 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
552 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
553 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
554 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
556 clocks = <&pcie1clk 0>;
560 pcie2: pcie@1f2d0000 {
563 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
564 #interrupt-cells = <1>;
566 #address-cells = <3>;
567 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
568 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
569 reg-names = "csr", "cfg";
570 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
571 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
572 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
573 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
574 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
575 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
576 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
577 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
578 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
579 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
581 clocks = <&pcie2clk 0>;
585 pcie3: pcie@1f500000 {
588 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
589 #interrupt-cells = <1>;
591 #address-cells = <3>;
592 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
593 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
594 reg-names = "csr", "cfg";
595 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
596 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
597 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
598 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
599 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
600 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
601 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
602 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
603 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
604 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
606 clocks = <&pcie3clk 0>;
610 pcie4: pcie@1f510000 {
613 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
614 #interrupt-cells = <1>;
616 #address-cells = <3>;
617 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
618 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
619 reg-names = "csr", "cfg";
620 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
621 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
622 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
624 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
625 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
626 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
627 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
628 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
629 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
631 clocks = <&pcie4clk 0>;
635 serial0: serial@1c020000 {
637 device_type = "serial";
638 compatible = "ns16550a";
639 reg = <0 0x1c020000 0x0 0x1000>;
641 clock-frequency = <10000000>; /* Updated by bootloader */
642 interrupt-parent = <&gic>;
643 interrupts = <0x0 0x4c 0x4>;
646 serial1: serial@1c021000 {
648 device_type = "serial";
649 compatible = "ns16550a";
650 reg = <0 0x1c021000 0x0 0x1000>;
652 clock-frequency = <10000000>; /* Updated by bootloader */
653 interrupt-parent = <&gic>;
654 interrupts = <0x0 0x4d 0x4>;
657 serial2: serial@1c022000 {
659 device_type = "serial";
660 compatible = "ns16550a";
661 reg = <0 0x1c022000 0x0 0x1000>;
663 clock-frequency = <10000000>; /* Updated by bootloader */
664 interrupt-parent = <&gic>;
665 interrupts = <0x0 0x4e 0x4>;
668 serial3: serial@1c023000 {
670 device_type = "serial";
671 compatible = "ns16550a";
672 reg = <0 0x1c023000 0x0 0x1000>;
674 clock-frequency = <10000000>; /* Updated by bootloader */
675 interrupt-parent = <&gic>;
676 interrupts = <0x0 0x4f 0x4>;
680 compatible = "apm,xgene-phy";
681 reg = <0x0 0x1f21a000 0x0 0x100>;
683 clocks = <&sataphy1clk 0>;
685 apm,tx-boost-gain = <30 30 30 30 30 30>;
686 apm,tx-eye-tuning = <2 10 10 2 10 10>;
690 compatible = "apm,xgene-phy";
691 reg = <0x0 0x1f22a000 0x0 0x100>;
693 clocks = <&sataphy2clk 0>;
695 apm,tx-boost-gain = <30 30 30 30 30 30>;
696 apm,tx-eye-tuning = <1 10 10 2 10 10>;
700 compatible = "apm,xgene-phy";
701 reg = <0x0 0x1f23a000 0x0 0x100>;
703 clocks = <&sataphy3clk 0>;
705 apm,tx-boost-gain = <31 31 31 31 31 31>;
706 apm,tx-eye-tuning = <2 10 10 2 10 10>;
709 sata1: sata@1a000000 {
710 compatible = "apm,xgene-ahci";
711 reg = <0x0 0x1a000000 0x0 0x1000>,
712 <0x0 0x1f210000 0x0 0x1000>,
713 <0x0 0x1f21d000 0x0 0x1000>,
714 <0x0 0x1f21e000 0x0 0x1000>,
715 <0x0 0x1f217000 0x0 0x1000>;
716 interrupts = <0x0 0x86 0x4>;
719 clocks = <&sata01clk 0>;
721 phy-names = "sata-phy";
724 sata2: sata@1a400000 {
725 compatible = "apm,xgene-ahci";
726 reg = <0x0 0x1a400000 0x0 0x1000>,
727 <0x0 0x1f220000 0x0 0x1000>,
728 <0x0 0x1f22d000 0x0 0x1000>,
729 <0x0 0x1f22e000 0x0 0x1000>,
730 <0x0 0x1f227000 0x0 0x1000>;
731 interrupts = <0x0 0x87 0x4>;
734 clocks = <&sata23clk 0>;
736 phy-names = "sata-phy";
739 sata3: sata@1a800000 {
740 compatible = "apm,xgene-ahci";
741 reg = <0x0 0x1a800000 0x0 0x1000>,
742 <0x0 0x1f230000 0x0 0x1000>,
743 <0x0 0x1f23d000 0x0 0x1000>,
744 <0x0 0x1f23e000 0x0 0x1000>;
745 interrupts = <0x0 0x88 0x4>;
748 clocks = <&sata45clk 0>;
750 phy-names = "sata-phy";
753 sbgpio: sbgpio@17001000{
754 compatible = "apm,xgene-gpio-sb";
755 reg = <0x0 0x17001000 0x0 0x400>;
758 interrupts = <0x0 0x28 0x1>,
767 compatible = "apm,xgene-rtc";
768 reg = <0x0 0x10510000 0x0 0x400>;
769 interrupts = <0x0 0x46 0x4>;
771 clocks = <&rtcclk 0>;
774 menet: ethernet@17020000 {
775 compatible = "apm,xgene-enet";
777 reg = <0x0 0x17020000 0x0 0xd100>,
778 <0x0 0X17030000 0x0 0Xc300>,
779 <0x0 0X10000000 0x0 0X200>;
780 reg-names = "enet_csr", "ring_csr", "ring_cmd";
781 interrupts = <0x0 0x3c 0x4>;
783 clocks = <&menetclk 0>;
784 /* mac address will be overwritten by the bootloader */
785 local-mac-address = [00 00 00 00 00 00];
786 phy-connection-type = "rgmii";
787 phy-handle = <&menetphy>;
789 compatible = "apm,xgene-mdio";
790 #address-cells = <1>;
792 menetphy: menetphy@3 {
793 compatible = "ethernet-phy-id001c.c915";
800 sgenet0: ethernet@1f210000 {
801 compatible = "apm,xgene1-sgenet";
803 reg = <0x0 0x1f210000 0x0 0xd100>,
804 <0x0 0x1f200000 0x0 0Xc300>,
805 <0x0 0x1B000000 0x0 0X200>;
806 reg-names = "enet_csr", "ring_csr", "ring_cmd";
807 interrupts = <0x0 0xA0 0x4>,
810 clocks = <&sge0clk 0>;
811 local-mac-address = [00 00 00 00 00 00];
812 phy-connection-type = "sgmii";
815 sgenet1: ethernet@1f210030 {
816 compatible = "apm,xgene1-sgenet";
818 reg = <0x0 0x1f210030 0x0 0xd100>,
819 <0x0 0x1f200000 0x0 0Xc300>,
820 <0x0 0x1B000000 0x0 0X8000>;
821 reg-names = "enet_csr", "ring_csr", "ring_cmd";
822 interrupts = <0x0 0xAC 0x4>,
826 clocks = <&sge1clk 0>;
827 local-mac-address = [00 00 00 00 00 00];
828 phy-connection-type = "sgmii";
831 xgenet: ethernet@1f610000 {
832 compatible = "apm,xgene1-xgenet";
834 reg = <0x0 0x1f610000 0x0 0xd100>,
835 <0x0 0x1f600000 0x0 0Xc300>,
836 <0x0 0x18000000 0x0 0X200>;
837 reg-names = "enet_csr", "ring_csr", "ring_cmd";
838 interrupts = <0x0 0x60 0x4>,
841 clocks = <&xge0clk 0>;
842 /* mac address will be overwritten by the bootloader */
843 local-mac-address = [00 00 00 00 00 00];
844 phy-connection-type = "xgmii";
847 xgenet1: ethernet@1f620000 {
848 compatible = "apm,xgene1-xgenet";
850 reg = <0x0 0x1f620000 0x0 0xd100>,
851 <0x0 0x1f600000 0x0 0Xc300>,
852 <0x0 0x18000000 0x0 0X8000>;
853 reg-names = "enet_csr", "ring_csr", "ring_cmd";
854 interrupts = <0x0 0x6C 0x4>,
858 clocks = <&xge1clk 0>;
859 /* mac address will be overwritten by the bootloader */
860 local-mac-address = [00 00 00 00 00 00];
861 phy-connection-type = "xgmii";
865 compatible = "apm,xgene-rng";
866 reg = <0x0 0x10520000 0x0 0x100>;
867 interrupts = <0x0 0x41 0x4>;
868 clocks = <&rngpkaclk 0>;
872 compatible = "apm,xgene-storm-dma";
874 reg = <0x0 0x1f270000 0x0 0x10000>,
875 <0x0 0x1f200000 0x0 0x10000>,
876 <0x0 0x1b000000 0x0 0x400000>,
877 <0x0 0x1054a000 0x0 0x100>;
878 interrupts = <0x0 0x82 0x4>,
884 clocks = <&dmaclk 0>;