arch/arm64/boot/dts/arm/juno-base.dtsi

   1         /*
   2          *  Devices shared by all Juno boards
   3          */
   4
   5         memtimer: timer@2a810000 {
   6                 compatible = "arm,armv7-timer-mem";
   7                 reg = <0x0 0x2a810000 0x0 0x10000>;
   8                 clock-frequency = <50000000>;
   9                 #address-cells = <2>;
  10                 #size-cells = <2>;
  11                 ranges;
  12                 status = "disabled";
  13                 frame@2a830000 {
  14                         frame-number = <1>;
  15                         interrupts = <0 60 4>;
  16                         reg = <0x0 0x2a830000 0x0 0x10000>;
  17                 };
  18         };
  19
  20         mailbox: mhu@2b1f0000 {
  21                 compatible = "arm,mhu", "arm,primecell";
  22                 reg = <0x0 0x2b1f0000 0x0 0x1000>;
  23                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
  24                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  25                 interrupt-names = "mhu_lpri_rx",
  26                                   "mhu_hpri_rx";
  27                 #mbox-cells = <1>;
  28                 clocks = <&soc_refclk100mhz>;
  29                 clock-names = "apb_pclk";
  30         };
  31
  32         smmu_pcie: iommu@2b500000 {
  33                 compatible = "arm,mmu-401", "arm,smmu-v1";
  34                 reg = <0x0 0x2b500000 0x0 0x10000>;
  35                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  36                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  37                 #iommu-cells = <1>;
  38                 #global-interrupts = <1>;
  39                 dma-coherent;
  40                 status = "disabled";
  41         };
  42
  43         smmu_etr: iommu@2b600000 {
  44                 compatible = "arm,mmu-401", "arm,smmu-v1";
  45                 reg = <0x0 0x2b600000 0x0 0x10000>;
  46                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  48                 #iommu-cells = <1>;
  49                 #global-interrupts = <1>;
  50                 dma-coherent;
  51                 status = "disabled";
  52         };
  53
  54         gic: interrupt-controller@2c010000 {
  55                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  56                 reg = <0x0 0x2c010000 0 0x1000>,
  57                       <0x0 0x2c02f000 0 0x2000>,
  58                       <0x0 0x2c04f000 0 0x2000>,
  59                       <0x0 0x2c06f000 0 0x2000>;
  60                 #address-cells = <2>;
  61                 #interrupt-cells = <3>;
  62                 #size-cells = <2>;
  63                 interrupt-controller;
  64                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
  65                 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
  66                 v2m_0: v2m@0 {
  67                         compatible = "arm,gic-v2m-frame";
  68                         msi-controller;
  69                         reg = <0 0 0 0x1000>;
  70                 };
  71         };
  72
  73         timer {
  74                 compatible = "arm,armv8-timer";
  75                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  78                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
  79         };
  80
  81         /*
  82          * Juno TRMs specify the size for these coresight components as 64K.
  83          * The actual size is just 4K though 64K is reserved. Access to the
  84          * unmapped reserved region results in a DECERR response.
  85          */
  86         etf@20010000 {
  87                 compatible = "arm,coresight-tmc", "arm,primecell";
  88                 reg = <0 0x20010000 0 0x1000>;
  89
  90                 clocks = <&soc_smc50mhz>;
  91                 clock-names = "apb_pclk";
  92                 power-domains = <&scpi_devpd 0>;
  93                 ports {
  94                         #address-cells = <1>;
  95                         #size-cells = <0>;
  96
  97                         /* input port */
  98                         port@0 {
  99                                 reg = <0>;
 100                                 etf_in_port: endpoint {
 101                                         slave-mode;
 102                                         remote-endpoint = <&main_funnel_out_port>;
 103                                 };
 104                         };
 105
 106                         /* output port */
 107                         port@1 {
 108                                 reg = <0>;
 109                                 etf_out_port: endpoint {
 110                                         remote-endpoint = <&replicator_in_port0>;
 111                                 };
 112                         };
 113                 };
 114         };
 115
 116         tpiu@20030000 {
 117                 compatible = "arm,coresight-tpiu", "arm,primecell";
 118                 reg = <0 0x20030000 0 0x1000>;
 119
 120                 clocks = <&soc_smc50mhz>;
 121                 clock-names = "apb_pclk";
 122                 power-domains = <&scpi_devpd 0>;
 123                 port {
 124                         tpiu_in_port: endpoint {
 125                                 slave-mode;
 126                                 remote-endpoint = <&replicator_out_port0>;
 127                         };
 128                 };
 129         };
 130
 131         main-funnel@20040000 {
 132                 compatible = "arm,coresight-funnel", "arm,primecell";
 133                 reg = <0 0x20040000 0 0x1000>;
 134
 135                 clocks = <&soc_smc50mhz>;
 136                 clock-names = "apb_pclk";
 137                 power-domains = <&scpi_devpd 0>;
 138                 ports {
 139                         #address-cells = <1>;
 140                         #size-cells = <0>;
 141
 142                         port@0 {
 143                                 reg = <0>;
 144                                 main_funnel_out_port: endpoint {
 145                                         remote-endpoint = <&etf_in_port>;
 146                                 };
 147                         };
 148
 149                         port@1 {
 150                                 reg = <0>;
 151                                 main_funnel_in_port0: endpoint {
 152                                         slave-mode;
 153                                         remote-endpoint = <&cluster0_funnel_out_port>;
 154                                 };
 155                         };
 156
 157                         port@2 {
 158                                 reg = <1>;
 159                                 main_funnel_in_port1: endpoint {
 160                                         slave-mode;
 161                                         remote-endpoint = <&cluster1_funnel_out_port>;
 162                                 };
 163                         };
 164
 165                 };
 166         };
 167
 168         etr@20070000 {
 169                 compatible = "arm,coresight-tmc", "arm,primecell";
 170                 reg = <0 0x20070000 0 0x1000>;
 171                 iommus = <&smmu_etr 0>;
 172
 173                 clocks = <&soc_smc50mhz>;
 174                 clock-names = "apb_pclk";
 175                 power-domains = <&scpi_devpd 0>;
 176                 port {
 177                         etr_in_port: endpoint {
 178                                 slave-mode;
 179                                 remote-endpoint = <&replicator_out_port1>;
 180                         };
 181                 };
 182         };
 183
 184         etm0: etm@22040000 {
 185                 compatible = "arm,coresight-etm4x", "arm,primecell";
 186                 reg = <0 0x22040000 0 0x1000>;
 187
 188                 clocks = <&soc_smc50mhz>;
 189                 clock-names = "apb_pclk";
 190                 power-domains = <&scpi_devpd 0>;
 191                 port {
 192                         cluster0_etm0_out_port: endpoint {
 193                                 remote-endpoint = <&cluster0_funnel_in_port0>;
 194                         };
 195                 };
 196         };
 197
 198         cluster0-funnel@220c0000 {
 199                 compatible = "arm,coresight-funnel", "arm,primecell";
 200                 reg = <0 0x220c0000 0 0x1000>;
 201
 202                 clocks = <&soc_smc50mhz>;
 203                 clock-names = "apb_pclk";
 204                 power-domains = <&scpi_devpd 0>;
 205                 ports {
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208
 209                         port@0 {
 210                                 reg = <0>;
 211                                 cluster0_funnel_out_port: endpoint {
 212                                         remote-endpoint = <&main_funnel_in_port0>;
 213                                 };
 214                         };
 215
 216                         port@1 {
 217                                 reg = <0>;
 218                                 cluster0_funnel_in_port0: endpoint {
 219                                         slave-mode;
 220                                         remote-endpoint = <&cluster0_etm0_out_port>;
 221                                 };
 222                         };
 223
 224                         port@2 {
 225                                 reg = <1>;
 226                                 cluster0_funnel_in_port1: endpoint {
 227                                         slave-mode;
 228                                         remote-endpoint = <&cluster0_etm1_out_port>;
 229                                 };
 230                         };
 231                 };
 232         };
 233
 234         etm1: etm@22140000 {
 235                 compatible = "arm,coresight-etm4x", "arm,primecell";
 236                 reg = <0 0x22140000 0 0x1000>;
 237
 238                 clocks = <&soc_smc50mhz>;
 239                 clock-names = "apb_pclk";
 240                 power-domains = <&scpi_devpd 0>;
 241                 port {
 242                         cluster0_etm1_out_port: endpoint {
 243                                 remote-endpoint = <&cluster0_funnel_in_port1>;
 244                         };
 245                 };
 246         };
 247
 248         etm2: etm@23040000 {
 249                 compatible = "arm,coresight-etm4x", "arm,primecell";
 250                 reg = <0 0x23040000 0 0x1000>;
 251
 252                 clocks = <&soc_smc50mhz>;
 253                 clock-names = "apb_pclk";
 254                 power-domains = <&scpi_devpd 0>;
 255                 port {
 256                         cluster1_etm0_out_port: endpoint {
 257                                 remote-endpoint = <&cluster1_funnel_in_port0>;
 258                         };
 259                 };
 260         };
 261
 262         cluster1-funnel@230c0000 {
 263                 compatible = "arm,coresight-funnel", "arm,primecell";
 264                 reg = <0 0x230c0000 0 0x1000>;
 265
 266                 clocks = <&soc_smc50mhz>;
 267                 clock-names = "apb_pclk";
 268                 power-domains = <&scpi_devpd 0>;
 269                 ports {
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272
 273                         port@0 {
 274                                 reg = <0>;
 275                                 cluster1_funnel_out_port: endpoint {
 276                                         remote-endpoint = <&main_funnel_in_port1>;
 277                                 };
 278                         };
 279
 280                         port@1 {
 281                                 reg = <0>;
 282                                 cluster1_funnel_in_port0: endpoint {
 283                                         slave-mode;
 284                                         remote-endpoint = <&cluster1_etm0_out_port>;
 285                                 };
 286                         };
 287
 288                         port@2 {
 289                                 reg = <1>;
 290                                 cluster1_funnel_in_port1: endpoint {
 291                                         slave-mode;
 292                                         remote-endpoint = <&cluster1_etm1_out_port>;
 293                                 };
 294                         };
 295                         port@3 {
 296                                 reg = <2>;
 297                                 cluster1_funnel_in_port2: endpoint {
 298                                         slave-mode;
 299                                         remote-endpoint = <&cluster1_etm2_out_port>;
 300                                 };
 301                         };
 302                         port@4 {
 303                                 reg = <3>;
 304                                 cluster1_funnel_in_port3: endpoint {
 305                                         slave-mode;
 306                                         remote-endpoint = <&cluster1_etm3_out_port>;
 307                                 };
 308                         };
 309                 };
 310         };
 311
 312         etm3: etm@23140000 {
 313                 compatible = "arm,coresight-etm4x", "arm,primecell";
 314                 reg = <0 0x23140000 0 0x1000>;
 315
 316                 clocks = <&soc_smc50mhz>;
 317                 clock-names = "apb_pclk";
 318                 power-domains = <&scpi_devpd 0>;
 319                 port {
 320                         cluster1_etm1_out_port: endpoint {
 321                                 remote-endpoint = <&cluster1_funnel_in_port1>;
 322                         };
 323                 };
 324         };
 325
 326         etm4: etm@23240000 {
 327                 compatible = "arm,coresight-etm4x", "arm,primecell";
 328                 reg = <0 0x23240000 0 0x1000>;
 329
 330                 clocks = <&soc_smc50mhz>;
 331                 clock-names = "apb_pclk";
 332                 power-domains = <&scpi_devpd 0>;
 333                 port {
 334                         cluster1_etm2_out_port: endpoint {
 335                                 remote-endpoint = <&cluster1_funnel_in_port2>;
 336                         };
 337                 };
 338         };
 339
 340         etm5: etm@23340000 {
 341                 compatible = "arm,coresight-etm4x", "arm,primecell";
 342                 reg = <0 0x23340000 0 0x1000>;
 343
 344                 clocks = <&soc_smc50mhz>;
 345                 clock-names = "apb_pclk";
 346                 power-domains = <&scpi_devpd 0>;
 347                 port {
 348                         cluster1_etm3_out_port: endpoint {
 349                                 remote-endpoint = <&cluster1_funnel_in_port3>;
 350                         };
 351                 };
 352         };
 353
 354         coresight-replicator {
 355                 /*
 356                  * Non-configurable replicators don't show up on the
 357                  * AMBA bus.  As such no need to add "arm,primecell".
 358                  */
 359                 compatible = "arm,coresight-replicator";
 360
 361                 ports {
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364
 365                         /* replicator output ports */
 366                         port@0 {
 367                                 reg = <0>;
 368                                 replicator_out_port0: endpoint {
 369                                         remote-endpoint = <&tpiu_in_port>;
 370                                 };
 371                         };
 372
 373                         port@1 {
 374                                 reg = <1>;
 375                                 replicator_out_port1: endpoint {
 376                                         remote-endpoint = <&etr_in_port>;
 377                                 };
 378                         };
 379
 380                         /* replicator input port */
 381                         port@2 {
 382                                 reg = <0>;
 383                                 replicator_in_port0: endpoint {
 384                                         slave-mode;
 385                                         remote-endpoint = <&etf_out_port>;
 386                                 };
 387                         };
 388                 };
 389         };
 390
 391         sram: sram@2e000000 {
 392                 compatible = "arm,juno-sram-ns", "mmio-sram";
 393                 reg = <0x0 0x2e000000 0x0 0x8000>;
 394
 395                 #address-cells = <1>;
 396                 #size-cells = <1>;
 397                 ranges = <0 0x0 0x2e000000 0x8000>;
 398
 399                 cpu_scp_lpri: scp-shmem@0 {
 400                         compatible = "arm,juno-scp-shmem";
 401                         reg = <0x0 0x200>;
 402                 };
 403
 404                 cpu_scp_hpri: scp-shmem@200 {
 405                         compatible = "arm,juno-scp-shmem";
 406                         reg = <0x200 0x200>;
 407                 };
 408         };
 409
 410         pcie_ctlr: pcie-controller@40000000 {
 411                 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
 412                 device_type = "pci";
 413                 reg = <0 0x40000000 0 0x10000000>;      /* ECAM config space */
 414                 bus-range = <0 255>;
 415                 linux,pci-domain = <0>;
 416                 #address-cells = <3>;
 417                 #size-cells = <2>;
 418                 dma-coherent;
 419                 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
 420                          <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
 421                          <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
 422                 #interrupt-cells = <1>;
 423                 interrupt-map-mask = <0 0 0 7>;
 424                 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
 425                                 <0 0 0 2 &gic 0 0 0 137 4>,
 426                                 <0 0 0 3 &gic 0 0 0 138 4>,
 427                                 <0 0 0 4 &gic 0 0 0 139 4>;
 428                 msi-parent = <&v2m_0>;
 429                 status = "disabled";
 430                 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
 431                 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
 432         };
 433
 434         scpi {
 435                 compatible = "arm,scpi";
 436                 mboxes = <&mailbox 1>;
 437                 shmem = <&cpu_scp_hpri>;
 438
 439                 clocks {
 440                         compatible = "arm,scpi-clocks";
 441
 442                         scpi_dvfs: scpi-dvfs {
 443                                 compatible = "arm,scpi-dvfs-clocks";
 444                                 #clock-cells = <1>;
 445                                 clock-indices = <0>, <1>, <2>;
 446                                 clock-output-names = "atlclk", "aplclk","gpuclk";
 447                         };
 448                         scpi_clk: scpi-clk {
 449                                 compatible = "arm,scpi-variable-clocks";
 450                                 #clock-cells = <1>;
 451                                 clock-indices = <3>;
 452                                 clock-output-names = "pxlclk";
 453                         };
 454                 };
 455
 456                 scpi_devpd: scpi-power-domains {
 457                         compatible = "arm,scpi-power-domains";
 458                         num-domains = <2>;
 459                         #power-domain-cells = <1>;
 460                 };
 461
 462                 scpi_sensors0: sensors {
 463                         compatible = "arm,scpi-sensors";
 464                         #thermal-sensor-cells = <1>;
 465                 };
 466         };
 467
 468         thermal-zones {
 469                 pmic {
 470                         polling-delay = <1000>;
 471                         polling-delay-passive = <100>;
 472                         thermal-sensors = <&scpi_sensors0 0>;
 473                 };
 474
 475                 soc {
 476                         polling-delay = <1000>;
 477                         polling-delay-passive = <100>;
 478                         thermal-sensors = <&scpi_sensors0 3>;
 479                 };
 480
 481                 big_cluster_thermal_zone: big_cluster {
 482                         polling-delay = <1000>;
 483                         polling-delay-passive = <100>;
 484                         thermal-sensors = <&scpi_sensors0 21>;
 485                         status = "disabled";
 486                 };
 487
 488                 little_cluster_thermal_zone: little_cluster {
 489                         polling-delay = <1000>;
 490                         polling-delay-passive = <100>;
 491                         thermal-sensors = <&scpi_sensors0 22>;
 492                         status = "disabled";
 493                 };
 494
 495                 gpu0_thermal_zone: gpu0 {
 496                         polling-delay = <1000>;
 497                         polling-delay-passive = <100>;
 498                         thermal-sensors = <&scpi_sensors0 23>;
 499                         status = "disabled";
 500                 };
 501
 502                 gpu1_thermal_zone: gpu1 {
 503                         polling-delay = <1000>;
 504                         polling-delay-passive = <100>;
 505                         thermal-sensors = <&scpi_sensors0 24>;
 506                         status = "disabled";
 507                 };
 508         };
 509
 510         /include/ "juno-clocks.dtsi"
 511
 512         smmu_dma: iommu@7fb00000 {
 513                 compatible = "arm,mmu-401", "arm,smmu-v1";
 514                 reg = <0x0 0x7fb00000 0x0 0x10000>;
 515                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 516                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 517                 #iommu-cells = <1>;
 518                 #global-interrupts = <1>;
 519                 dma-coherent;
 520                 status = "disabled";
 521         };
 522
 523         smmu_hdlcd1: iommu@7fb10000 {
 524                 compatible = "arm,mmu-401", "arm,smmu-v1";
 525                 reg = <0x0 0x7fb10000 0x0 0x10000>;
 526                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 527                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 528                 #iommu-cells = <1>;
 529                 #global-interrupts = <1>;
 530                 status = "disabled";
 531         };
 532
 533         smmu_hdlcd0: iommu@7fb20000 {
 534                 compatible = "arm,mmu-401", "arm,smmu-v1";
 535                 reg = <0x0 0x7fb20000 0x0 0x10000>;
 536                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 537                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 538                 #iommu-cells = <1>;
 539                 #global-interrupts = <1>;
 540                 status = "disabled";
 541         };
 542
 543         smmu_usb: iommu@7fb30000 {
 544                 compatible = "arm,mmu-401", "arm,smmu-v1";
 545                 reg = <0x0 0x7fb30000 0x0 0x10000>;
 546                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 547                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 548                 #iommu-cells = <1>;
 549                 #global-interrupts = <1>;
 550                 dma-coherent;
 551                 status = "disabled";
 552         };
 553
 554         dma@7ff00000 {
 555                 compatible = "arm,pl330", "arm,primecell";
 556                 reg = <0x0 0x7ff00000 0 0x1000>;
 557                 #dma-cells = <1>;
 558                 #dma-channels = <8>;
 559                 #dma-requests = <32>;
 560                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 561                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 562                              <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 563                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 564                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 565                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 566                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 567                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 568                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 569                 iommus = <&smmu_dma 0>,
 570                          <&smmu_dma 1>,
 571                          <&smmu_dma 2>,
 572                          <&smmu_dma 3>,
 573                          <&smmu_dma 4>,
 574                          <&smmu_dma 5>,
 575                          <&smmu_dma 6>,
 576                          <&smmu_dma 7>,
 577                          <&smmu_dma 8>;
 578                 clocks = <&soc_faxiclk>;
 579                 clock-names = "apb_pclk";
 580         };
 581
 582         hdlcd@7ff50000 {
 583                 compatible = "arm,hdlcd";
 584                 reg = <0 0x7ff50000 0 0x1000>;
 585                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 586                 iommus = <&smmu_hdlcd1 0>;
 587                 clocks = <&scpi_clk 3>;
 588                 clock-names = "pxlclk";
 589
 590                 port {
 591                         hdlcd1_output: hdlcd1-endpoint {
 592                                 remote-endpoint = <&tda998x_1_input>;
 593                         };
 594                 };
 595         };
 596
 597         hdlcd@7ff60000 {
 598                 compatible = "arm,hdlcd";
 599                 reg = <0 0x7ff60000 0 0x1000>;
 600                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 601                 iommus = <&smmu_hdlcd0 0>;
 602                 clocks = <&scpi_clk 3>;
 603                 clock-names = "pxlclk";
 604
 605                 port {
 606                         hdlcd0_output: hdlcd0-endpoint {
 607                                 remote-endpoint = <&tda998x_0_input>;
 608                         };
 609                 };
 610         };
 611
 612         soc_uart0: uart@7ff80000 {
 613                 compatible = "arm,pl011", "arm,primecell";
 614                 reg = <0x0 0x7ff80000 0x0 0x1000>;
 615                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 616                 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
 617                 clock-names = "uartclk", "apb_pclk";
 618         };
 619
 620         i2c@7ffa0000 {
 621                 compatible = "snps,designware-i2c";
 622                 reg = <0x0 0x7ffa0000 0x0 0x1000>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 626                 clock-frequency = <400000>;
 627                 i2c-sda-hold-time-ns = <500>;
 628                 clocks = <&soc_smc50mhz>;
 629
 630                 hdmi-transmitter@70 {
 631                         compatible = "nxp,tda998x";
 632                         reg = <0x70>;
 633                         port {
 634                                 tda998x_0_input: tda998x-0-endpoint {
 635                                         remote-endpoint = <&hdlcd0_output>;
 636                                 };
 637                         };
 638                 };
 639
 640                 hdmi-transmitter@71 {
 641                         compatible = "nxp,tda998x";
 642                         reg = <0x71>;
 643                         port {
 644                                 tda998x_1_input: tda998x-1-endpoint {
 645                                         remote-endpoint = <&hdlcd1_output>;
 646                                 };
 647                         };
 648                 };
 649         };
 650
 651         ohci@7ffb0000 {
 652                 compatible = "generic-ohci";
 653                 reg = <0x0 0x7ffb0000 0x0 0x10000>;
 654                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 655                 iommus = <&smmu_usb 0>;
 656                 clocks = <&soc_usb48mhz>;
 657         };
 658
 659         ehci@7ffc0000 {
 660                 compatible = "generic-ehci";
 661                 reg = <0x0 0x7ffc0000 0x0 0x10000>;
 662                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 663                 iommus = <&smmu_usb 0>;
 664                 clocks = <&soc_usb48mhz>;
 665         };
 666
 667         memory-controller@7ffd0000 {
 668                 compatible = "arm,pl354", "arm,primecell";
 669                 reg = <0 0x7ffd0000 0 0x1000>;
 670                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 671                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 672                 clocks = <&soc_smc50mhz>;
 673                 clock-names = "apb_pclk";
 674         };
 675
 676         memory@80000000 {
 677                 device_type = "memory";
 678                 /* last 16MB of the first memory area is reserved for secure world use by firmware */
 679                 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
 680                       <0x00000008 0x80000000 0x1 0x80000000>;
 681         };
 682
 683         smb@08000000 {
 684                 compatible = "simple-bus";
 685                 #address-cells = <2>;
 686                 #size-cells = <1>;
 687                 ranges = <0 0 0 0x08000000 0x04000000>,
 688                          <1 0 0 0x14000000 0x04000000>,
 689                          <2 0 0 0x18000000 0x04000000>,
 690                          <3 0 0 0x1c000000 0x04000000>,
 691                          <4 0 0 0x0c000000 0x04000000>,
 692                          <5 0 0 0x10000000 0x04000000>;
 693
 694                 #interrupt-cells = <1>;
 695                 interrupt-map-mask = <0 0 15>;
 696                 interrupt-map = <0 0  0 &gic 0 0 0  68 IRQ_TYPE_LEVEL_HIGH>,
 697                                 <0 0  1 &gic 0 0 0  69 IRQ_TYPE_LEVEL_HIGH>,
 698                                 <0 0  2 &gic 0 0 0  70 IRQ_TYPE_LEVEL_HIGH>,
 699                                 <0 0  3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
 700                                 <0 0  4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
 701                                 <0 0  5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
 702                                 <0 0  6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
 703                                 <0 0  7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
 704                                 <0 0  8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
 705                                 <0 0  9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
 706                                 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
 707                                 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
 708                                 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
 709
 710                 /include/ "juno-motherboard.dtsi"
 711         };
 712
 713         site2: tlx@60000000 {
 714                 compatible = "simple-bus";
 715                 #address-cells = <1>;
 716                 #size-cells = <1>;
 717                 ranges = <0 0 0x60000000 0x10000000>;
 718                 #interrupt-cells = <1>;
 719                 interrupt-map-mask = <0 0>;
 720                 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
 721         };