1 #include "juno-clocks.dtsi"
5 * Devices shared by all Juno boards
7 dma-ranges = <0 0 0 0 0x100 0>;
9 memtimer: timer@2a810000 {
10 compatible = "arm,armv7-timer-mem";
11 reg = <0x0 0x2a810000 0x0 0x10000>;
12 clock-frequency = <50000000>;
19 interrupts = <0 60 4>;
20 reg = <0x0 0x2a830000 0x0 0x10000>;
24 mailbox: mhu@2b1f0000 {
25 compatible = "arm,mhu", "arm,primecell";
26 reg = <0x0 0x2b1f0000 0x0 0x1000>;
27 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
28 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-names = "mhu_lpri_rx",
32 clocks = <&soc_refclk100mhz>;
33 clock-names = "apb_pclk";
36 smmu_pcie: iommu@2b500000 {
37 compatible = "arm,mmu-401", "arm,smmu-v1";
38 reg = <0x0 0x2b500000 0x0 0x10000>;
39 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
42 #global-interrupts = <1>;
47 smmu_etr: iommu@2b600000 {
48 compatible = "arm,mmu-401", "arm,smmu-v1";
49 reg = <0x0 0x2b600000 0x0 0x10000>;
50 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
53 #global-interrupts = <1>;
55 power-domains = <&scpi_devpd 0>;
59 gic: interrupt-controller@2c010000 {
60 compatible = "arm,gic-400", "arm,cortex-a15-gic";
61 reg = <0x0 0x2c010000 0 0x1000>,
62 <0x0 0x2c02f000 0 0x2000>,
63 <0x0 0x2c04f000 0 0x2000>,
64 <0x0 0x2c06f000 0 0x2000>;
66 #interrupt-cells = <3>;
69 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
70 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
72 compatible = "arm,gic-v2m-frame";
79 compatible = "arm,armv8-timer";
80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
87 * Juno TRMs specify the size for these coresight components as 64K.
88 * The actual size is just 4K though 64K is reserved. Access to the
89 * unmapped reserved region results in a DECERR response.
91 etf@20010000 { /* etf0 */
92 compatible = "arm,coresight-tmc", "arm,primecell";
93 reg = <0 0x20010000 0 0x1000>;
95 clocks = <&soc_smc50mhz>;
96 clock-names = "apb_pclk";
97 power-domains = <&scpi_devpd 0>;
105 etf0_in_port: endpoint {
107 remote-endpoint = <&main_funnel_out_port>;
114 etf0_out_port: endpoint {
121 compatible = "arm,coresight-tpiu", "arm,primecell";
122 reg = <0 0x20030000 0 0x1000>;
124 clocks = <&soc_smc50mhz>;
125 clock-names = "apb_pclk";
126 power-domains = <&scpi_devpd 0>;
128 tpiu_in_port: endpoint {
130 remote-endpoint = <&replicator_out_port0>;
135 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
136 main_funnel: funnel@20040000 {
137 compatible = "arm,coresight-funnel", "arm,primecell";
138 reg = <0 0x20040000 0 0x1000>;
140 clocks = <&soc_smc50mhz>;
141 clock-names = "apb_pclk";
142 power-domains = <&scpi_devpd 0>;
144 #address-cells = <1>;
150 main_funnel_out_port: endpoint {
151 remote-endpoint = <&etf0_in_port>;
158 main_funnel_in_port0: endpoint {
160 remote-endpoint = <&cluster0_funnel_out_port>;
166 main_funnel_in_port1: endpoint {
168 remote-endpoint = <&cluster1_funnel_out_port>;
175 compatible = "arm,coresight-tmc", "arm,primecell";
176 reg = <0 0x20070000 0 0x1000>;
177 iommus = <&smmu_etr 0>;
179 clocks = <&soc_smc50mhz>;
180 clock-names = "apb_pclk";
181 power-domains = <&scpi_devpd 0>;
183 etr_in_port: endpoint {
185 remote-endpoint = <&replicator_out_port1>;
191 compatible = "arm,coresight-stm", "arm,primecell";
192 reg = <0 0x20100000 0 0x1000>,
193 <0 0x28000000 0 0x1000000>;
194 reg-names = "stm-base", "stm-stimulus-base";
196 clocks = <&soc_smc50mhz>;
197 clock-names = "apb_pclk";
198 power-domains = <&scpi_devpd 0>;
200 stm_out_port: endpoint {
206 compatible = "arm,coresight-etm4x", "arm,primecell";
207 reg = <0 0x22040000 0 0x1000>;
209 clocks = <&soc_smc50mhz>;
210 clock-names = "apb_pclk";
211 power-domains = <&scpi_devpd 0>;
213 cluster0_etm0_out_port: endpoint {
214 remote-endpoint = <&cluster0_funnel_in_port0>;
219 funnel@220c0000 { /* cluster0 funnel */
220 compatible = "arm,coresight-funnel", "arm,primecell";
221 reg = <0 0x220c0000 0 0x1000>;
223 clocks = <&soc_smc50mhz>;
224 clock-names = "apb_pclk";
225 power-domains = <&scpi_devpd 0>;
227 #address-cells = <1>;
232 cluster0_funnel_out_port: endpoint {
233 remote-endpoint = <&main_funnel_in_port0>;
239 cluster0_funnel_in_port0: endpoint {
241 remote-endpoint = <&cluster0_etm0_out_port>;
247 cluster0_funnel_in_port1: endpoint {
249 remote-endpoint = <&cluster0_etm1_out_port>;
256 compatible = "arm,coresight-etm4x", "arm,primecell";
257 reg = <0 0x22140000 0 0x1000>;
259 clocks = <&soc_smc50mhz>;
260 clock-names = "apb_pclk";
261 power-domains = <&scpi_devpd 0>;
263 cluster0_etm1_out_port: endpoint {
264 remote-endpoint = <&cluster0_funnel_in_port1>;
270 compatible = "arm,coresight-etm4x", "arm,primecell";
271 reg = <0 0x23040000 0 0x1000>;
273 clocks = <&soc_smc50mhz>;
274 clock-names = "apb_pclk";
275 power-domains = <&scpi_devpd 0>;
277 cluster1_etm0_out_port: endpoint {
278 remote-endpoint = <&cluster1_funnel_in_port0>;
283 funnel@230c0000 { /* cluster1 funnel */
284 compatible = "arm,coresight-funnel", "arm,primecell";
285 reg = <0 0x230c0000 0 0x1000>;
287 clocks = <&soc_smc50mhz>;
288 clock-names = "apb_pclk";
289 power-domains = <&scpi_devpd 0>;
291 #address-cells = <1>;
296 cluster1_funnel_out_port: endpoint {
297 remote-endpoint = <&main_funnel_in_port1>;
303 cluster1_funnel_in_port0: endpoint {
305 remote-endpoint = <&cluster1_etm0_out_port>;
311 cluster1_funnel_in_port1: endpoint {
313 remote-endpoint = <&cluster1_etm1_out_port>;
318 cluster1_funnel_in_port2: endpoint {
320 remote-endpoint = <&cluster1_etm2_out_port>;
325 cluster1_funnel_in_port3: endpoint {
327 remote-endpoint = <&cluster1_etm3_out_port>;
334 compatible = "arm,coresight-etm4x", "arm,primecell";
335 reg = <0 0x23140000 0 0x1000>;
337 clocks = <&soc_smc50mhz>;
338 clock-names = "apb_pclk";
339 power-domains = <&scpi_devpd 0>;
341 cluster1_etm1_out_port: endpoint {
342 remote-endpoint = <&cluster1_funnel_in_port1>;
348 compatible = "arm,coresight-etm4x", "arm,primecell";
349 reg = <0 0x23240000 0 0x1000>;
351 clocks = <&soc_smc50mhz>;
352 clock-names = "apb_pclk";
353 power-domains = <&scpi_devpd 0>;
355 cluster1_etm2_out_port: endpoint {
356 remote-endpoint = <&cluster1_funnel_in_port2>;
362 compatible = "arm,coresight-etm4x", "arm,primecell";
363 reg = <0 0x23340000 0 0x1000>;
365 clocks = <&soc_smc50mhz>;
366 clock-names = "apb_pclk";
367 power-domains = <&scpi_devpd 0>;
369 cluster1_etm3_out_port: endpoint {
370 remote-endpoint = <&cluster1_funnel_in_port3>;
375 coresight-replicator {
377 * Non-configurable replicators don't show up on the
378 * AMBA bus. As such no need to add "arm,primecell".
380 compatible = "arm,coresight-replicator";
383 #address-cells = <1>;
386 /* replicator output ports */
389 replicator_out_port0: endpoint {
390 remote-endpoint = <&tpiu_in_port>;
396 replicator_out_port1: endpoint {
397 remote-endpoint = <&etr_in_port>;
401 /* replicator input port */
404 replicator_in_port0: endpoint {
411 sram: sram@2e000000 {
412 compatible = "arm,juno-sram-ns", "mmio-sram";
413 reg = <0x0 0x2e000000 0x0 0x8000>;
415 #address-cells = <1>;
417 ranges = <0 0x0 0x2e000000 0x8000>;
419 cpu_scp_lpri: scp-shmem@0 {
420 compatible = "arm,juno-scp-shmem";
424 cpu_scp_hpri: scp-shmem@200 {
425 compatible = "arm,juno-scp-shmem";
430 pcie_ctlr: pcie-controller@40000000 {
431 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
433 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
435 linux,pci-domain = <0>;
436 #address-cells = <3>;
439 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
440 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
441 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
442 #interrupt-cells = <1>;
443 interrupt-map-mask = <0 0 0 7>;
444 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
445 <0 0 0 2 &gic 0 0 0 137 4>,
446 <0 0 0 3 &gic 0 0 0 138 4>,
447 <0 0 0 4 &gic 0 0 0 139 4>;
448 msi-parent = <&v2m_0>;
450 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
451 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
455 compatible = "arm,scpi";
456 mboxes = <&mailbox 1>;
457 shmem = <&cpu_scp_hpri>;
460 compatible = "arm,scpi-clocks";
462 scpi_dvfs: scpi-dvfs {
463 compatible = "arm,scpi-dvfs-clocks";
465 clock-indices = <0>, <1>, <2>;
466 clock-output-names = "atlclk", "aplclk","gpuclk";
469 compatible = "arm,scpi-variable-clocks";
472 clock-output-names = "pxlclk";
476 scpi_devpd: scpi-power-domains {
477 compatible = "arm,scpi-power-domains";
479 #power-domain-cells = <1>;
482 scpi_sensors0: sensors {
483 compatible = "arm,scpi-sensors";
484 #thermal-sensor-cells = <1>;
490 polling-delay = <1000>;
491 polling-delay-passive = <100>;
492 thermal-sensors = <&scpi_sensors0 0>;
496 polling-delay = <1000>;
497 polling-delay-passive = <100>;
498 thermal-sensors = <&scpi_sensors0 3>;
501 big_cluster_thermal_zone: big_cluster {
502 polling-delay = <1000>;
503 polling-delay-passive = <100>;
504 thermal-sensors = <&scpi_sensors0 21>;
508 little_cluster_thermal_zone: little_cluster {
509 polling-delay = <1000>;
510 polling-delay-passive = <100>;
511 thermal-sensors = <&scpi_sensors0 22>;
515 gpu0_thermal_zone: gpu0 {
516 polling-delay = <1000>;
517 polling-delay-passive = <100>;
518 thermal-sensors = <&scpi_sensors0 23>;
522 gpu1_thermal_zone: gpu1 {
523 polling-delay = <1000>;
524 polling-delay-passive = <100>;
525 thermal-sensors = <&scpi_sensors0 24>;
530 smmu_dma: iommu@7fb00000 {
531 compatible = "arm,mmu-401", "arm,smmu-v1";
532 reg = <0x0 0x7fb00000 0x0 0x10000>;
533 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
536 #global-interrupts = <1>;
541 smmu_hdlcd1: iommu@7fb10000 {
542 compatible = "arm,mmu-401", "arm,smmu-v1";
543 reg = <0x0 0x7fb10000 0x0 0x10000>;
544 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
547 #global-interrupts = <1>;
551 smmu_hdlcd0: iommu@7fb20000 {
552 compatible = "arm,mmu-401", "arm,smmu-v1";
553 reg = <0x0 0x7fb20000 0x0 0x10000>;
554 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
557 #global-interrupts = <1>;
561 smmu_usb: iommu@7fb30000 {
562 compatible = "arm,mmu-401", "arm,smmu-v1";
563 reg = <0x0 0x7fb30000 0x0 0x10000>;
564 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
567 #global-interrupts = <1>;
573 compatible = "arm,pl330", "arm,primecell";
574 reg = <0x0 0x7ff00000 0 0x1000>;
577 #dma-requests = <32>;
578 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
587 iommus = <&smmu_dma 0>,
596 clocks = <&soc_faxiclk>;
597 clock-names = "apb_pclk";
601 compatible = "arm,hdlcd";
602 reg = <0 0x7ff50000 0 0x1000>;
603 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
604 iommus = <&smmu_hdlcd1 0>;
605 clocks = <&scpi_clk 3>;
606 clock-names = "pxlclk";
609 hdlcd1_output: hdlcd1-endpoint {
610 remote-endpoint = <&tda998x_1_input>;
616 compatible = "arm,hdlcd";
617 reg = <0 0x7ff60000 0 0x1000>;
618 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
619 iommus = <&smmu_hdlcd0 0>;
620 clocks = <&scpi_clk 3>;
621 clock-names = "pxlclk";
624 hdlcd0_output: hdlcd0-endpoint {
625 remote-endpoint = <&tda998x_0_input>;
630 soc_uart0: uart@7ff80000 {
631 compatible = "arm,pl011", "arm,primecell";
632 reg = <0x0 0x7ff80000 0x0 0x1000>;
633 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
635 clock-names = "uartclk", "apb_pclk";
639 compatible = "snps,designware-i2c";
640 reg = <0x0 0x7ffa0000 0x0 0x1000>;
641 #address-cells = <1>;
643 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
644 clock-frequency = <400000>;
645 i2c-sda-hold-time-ns = <500>;
646 clocks = <&soc_smc50mhz>;
648 hdmi-transmitter@70 {
649 compatible = "nxp,tda998x";
652 tda998x_0_input: tda998x-0-endpoint {
653 remote-endpoint = <&hdlcd0_output>;
658 hdmi-transmitter@71 {
659 compatible = "nxp,tda998x";
662 tda998x_1_input: tda998x-1-endpoint {
663 remote-endpoint = <&hdlcd1_output>;
670 compatible = "generic-ohci";
671 reg = <0x0 0x7ffb0000 0x0 0x10000>;
672 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
673 iommus = <&smmu_usb 0>;
674 clocks = <&soc_usb48mhz>;
678 compatible = "generic-ehci";
679 reg = <0x0 0x7ffc0000 0x0 0x10000>;
680 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
681 iommus = <&smmu_usb 0>;
682 clocks = <&soc_usb48mhz>;
685 memory-controller@7ffd0000 {
686 compatible = "arm,pl354", "arm,primecell";
687 reg = <0 0x7ffd0000 0 0x1000>;
688 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&soc_smc50mhz>;
691 clock-names = "apb_pclk";
695 device_type = "memory";
696 /* last 16MB of the first memory area is reserved for secure world use by firmware */
697 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
698 <0x00000008 0x80000000 0x1 0x80000000>;
702 compatible = "simple-bus";
703 #address-cells = <2>;
705 ranges = <0 0 0 0x08000000 0x04000000>,
706 <1 0 0 0x14000000 0x04000000>,
707 <2 0 0 0x18000000 0x04000000>,
708 <3 0 0 0x1c000000 0x04000000>,
709 <4 0 0 0x0c000000 0x04000000>,
710 <5 0 0 0x10000000 0x04000000>;
712 #interrupt-cells = <1>;
713 interrupt-map-mask = <0 0 15>;
714 interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
715 <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
716 <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
717 <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
718 <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
719 <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
720 <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
721 <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
722 <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
723 <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
724 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
725 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
726 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
728 /include/ "juno-motherboard.dtsi"
731 site2: tlx@60000000 {
732 compatible = "simple-bus";
733 #address-cells = <1>;
735 ranges = <0 0 0x60000000 0x10000000>;
736 #interrupt-cells = <1>;
737 interrupt-map-mask = <0 0>;
738 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;