2 * Devices shared by all Juno boards
5 memtimer: timer@2a810000 {
6 compatible = "arm,armv7-timer-mem";
7 reg = <0x0 0x2a810000 0x0 0x10000>;
8 clock-frequency = <50000000>;
15 interrupts = <0 60 4>;
16 reg = <0x0 0x2a830000 0x0 0x10000>;
20 mailbox: mhu@2b1f0000 {
21 compatible = "arm,mhu", "arm,primecell";
22 reg = <0x0 0x2b1f0000 0x0 0x1000>;
23 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
24 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
25 interrupt-names = "mhu_lpri_rx",
28 clocks = <&soc_refclk100mhz>;
29 clock-names = "apb_pclk";
32 smmu_pcie: iommu@2b500000 {
33 compatible = "arm,mmu-401", "arm,smmu-v1";
34 reg = <0x0 0x2b500000 0x0 0x10000>;
35 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
38 #global-interrupts = <1>;
43 smmu_etr: iommu@2b600000 {
44 compatible = "arm,mmu-401", "arm,smmu-v1";
45 reg = <0x0 0x2b600000 0x0 0x10000>;
46 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
49 #global-interrupts = <1>;
54 gic: interrupt-controller@2c010000 {
55 compatible = "arm,gic-400", "arm,cortex-a15-gic";
56 reg = <0x0 0x2c010000 0 0x1000>,
57 <0x0 0x2c02f000 0 0x2000>,
58 <0x0 0x2c04f000 0 0x2000>,
59 <0x0 0x2c06f000 0 0x2000>;
61 #interrupt-cells = <3>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
65 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
67 compatible = "arm,gic-v2m-frame";
74 compatible = "arm,armv8-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
78 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
82 * Juno TRMs specify the size for these coresight components as 64K.
83 * The actual size is just 4K though 64K is reserved. Access to the
84 * unmapped reserved region results in a DECERR response.
87 compatible = "arm,coresight-tmc", "arm,primecell";
88 reg = <0 0x20010000 0 0x1000>;
90 clocks = <&soc_smc50mhz>;
91 clock-names = "apb_pclk";
92 power-domains = <&scpi_devpd 0>;
100 etf_in_port: endpoint {
102 remote-endpoint = <&main_funnel_out_port>;
109 etf_out_port: endpoint {
110 remote-endpoint = <&replicator_in_port0>;
117 compatible = "arm,coresight-tpiu", "arm,primecell";
118 reg = <0 0x20030000 0 0x1000>;
120 clocks = <&soc_smc50mhz>;
121 clock-names = "apb_pclk";
122 power-domains = <&scpi_devpd 0>;
124 tpiu_in_port: endpoint {
126 remote-endpoint = <&replicator_out_port0>;
131 main-funnel@20040000 {
132 compatible = "arm,coresight-funnel", "arm,primecell";
133 reg = <0 0x20040000 0 0x1000>;
135 clocks = <&soc_smc50mhz>;
136 clock-names = "apb_pclk";
137 power-domains = <&scpi_devpd 0>;
139 #address-cells = <1>;
144 main_funnel_out_port: endpoint {
145 remote-endpoint = <&etf_in_port>;
151 main_funnel_in_port0: endpoint {
153 remote-endpoint = <&cluster0_funnel_out_port>;
159 main_funnel_in_port1: endpoint {
161 remote-endpoint = <&cluster1_funnel_out_port>;
169 compatible = "arm,coresight-tmc", "arm,primecell";
170 reg = <0 0x20070000 0 0x1000>;
171 iommus = <&smmu_etr 0>;
173 clocks = <&soc_smc50mhz>;
174 clock-names = "apb_pclk";
175 power-domains = <&scpi_devpd 0>;
177 etr_in_port: endpoint {
179 remote-endpoint = <&replicator_out_port1>;
185 compatible = "arm,coresight-etm4x", "arm,primecell";
186 reg = <0 0x22040000 0 0x1000>;
188 clocks = <&soc_smc50mhz>;
189 clock-names = "apb_pclk";
190 power-domains = <&scpi_devpd 0>;
192 cluster0_etm0_out_port: endpoint {
193 remote-endpoint = <&cluster0_funnel_in_port0>;
198 cluster0-funnel@220c0000 {
199 compatible = "arm,coresight-funnel", "arm,primecell";
200 reg = <0 0x220c0000 0 0x1000>;
202 clocks = <&soc_smc50mhz>;
203 clock-names = "apb_pclk";
204 power-domains = <&scpi_devpd 0>;
206 #address-cells = <1>;
211 cluster0_funnel_out_port: endpoint {
212 remote-endpoint = <&main_funnel_in_port0>;
218 cluster0_funnel_in_port0: endpoint {
220 remote-endpoint = <&cluster0_etm0_out_port>;
226 cluster0_funnel_in_port1: endpoint {
228 remote-endpoint = <&cluster0_etm1_out_port>;
235 compatible = "arm,coresight-etm4x", "arm,primecell";
236 reg = <0 0x22140000 0 0x1000>;
238 clocks = <&soc_smc50mhz>;
239 clock-names = "apb_pclk";
240 power-domains = <&scpi_devpd 0>;
242 cluster0_etm1_out_port: endpoint {
243 remote-endpoint = <&cluster0_funnel_in_port1>;
249 compatible = "arm,coresight-etm4x", "arm,primecell";
250 reg = <0 0x23040000 0 0x1000>;
252 clocks = <&soc_smc50mhz>;
253 clock-names = "apb_pclk";
254 power-domains = <&scpi_devpd 0>;
256 cluster1_etm0_out_port: endpoint {
257 remote-endpoint = <&cluster1_funnel_in_port0>;
262 cluster1-funnel@230c0000 {
263 compatible = "arm,coresight-funnel", "arm,primecell";
264 reg = <0 0x230c0000 0 0x1000>;
266 clocks = <&soc_smc50mhz>;
267 clock-names = "apb_pclk";
268 power-domains = <&scpi_devpd 0>;
270 #address-cells = <1>;
275 cluster1_funnel_out_port: endpoint {
276 remote-endpoint = <&main_funnel_in_port1>;
282 cluster1_funnel_in_port0: endpoint {
284 remote-endpoint = <&cluster1_etm0_out_port>;
290 cluster1_funnel_in_port1: endpoint {
292 remote-endpoint = <&cluster1_etm1_out_port>;
297 cluster1_funnel_in_port2: endpoint {
299 remote-endpoint = <&cluster1_etm2_out_port>;
304 cluster1_funnel_in_port3: endpoint {
306 remote-endpoint = <&cluster1_etm3_out_port>;
313 compatible = "arm,coresight-etm4x", "arm,primecell";
314 reg = <0 0x23140000 0 0x1000>;
316 clocks = <&soc_smc50mhz>;
317 clock-names = "apb_pclk";
318 power-domains = <&scpi_devpd 0>;
320 cluster1_etm1_out_port: endpoint {
321 remote-endpoint = <&cluster1_funnel_in_port1>;
327 compatible = "arm,coresight-etm4x", "arm,primecell";
328 reg = <0 0x23240000 0 0x1000>;
330 clocks = <&soc_smc50mhz>;
331 clock-names = "apb_pclk";
332 power-domains = <&scpi_devpd 0>;
334 cluster1_etm2_out_port: endpoint {
335 remote-endpoint = <&cluster1_funnel_in_port2>;
341 compatible = "arm,coresight-etm4x", "arm,primecell";
342 reg = <0 0x23340000 0 0x1000>;
344 clocks = <&soc_smc50mhz>;
345 clock-names = "apb_pclk";
346 power-domains = <&scpi_devpd 0>;
348 cluster1_etm3_out_port: endpoint {
349 remote-endpoint = <&cluster1_funnel_in_port3>;
354 coresight-replicator {
356 * Non-configurable replicators don't show up on the
357 * AMBA bus. As such no need to add "arm,primecell".
359 compatible = "arm,coresight-replicator";
362 #address-cells = <1>;
365 /* replicator output ports */
368 replicator_out_port0: endpoint {
369 remote-endpoint = <&tpiu_in_port>;
375 replicator_out_port1: endpoint {
376 remote-endpoint = <&etr_in_port>;
380 /* replicator input port */
383 replicator_in_port0: endpoint {
385 remote-endpoint = <&etf_out_port>;
391 sram: sram@2e000000 {
392 compatible = "arm,juno-sram-ns", "mmio-sram";
393 reg = <0x0 0x2e000000 0x0 0x8000>;
395 #address-cells = <1>;
397 ranges = <0 0x0 0x2e000000 0x8000>;
399 cpu_scp_lpri: scp-shmem@0 {
400 compatible = "arm,juno-scp-shmem";
404 cpu_scp_hpri: scp-shmem@200 {
405 compatible = "arm,juno-scp-shmem";
410 pcie_ctlr: pcie-controller@40000000 {
411 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
413 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
415 linux,pci-domain = <0>;
416 #address-cells = <3>;
419 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
420 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
421 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
422 #interrupt-cells = <1>;
423 interrupt-map-mask = <0 0 0 7>;
424 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
425 <0 0 0 2 &gic 0 0 0 137 4>,
426 <0 0 0 3 &gic 0 0 0 138 4>,
427 <0 0 0 4 &gic 0 0 0 139 4>;
428 msi-parent = <&v2m_0>;
430 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
431 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
435 compatible = "arm,scpi";
436 mboxes = <&mailbox 1>;
437 shmem = <&cpu_scp_hpri>;
440 compatible = "arm,scpi-clocks";
442 scpi_dvfs: scpi-dvfs {
443 compatible = "arm,scpi-dvfs-clocks";
445 clock-indices = <0>, <1>, <2>;
446 clock-output-names = "atlclk", "aplclk","gpuclk";
449 compatible = "arm,scpi-variable-clocks";
452 clock-output-names = "pxlclk";
456 scpi_devpd: scpi-power-domains {
457 compatible = "arm,scpi-power-domains";
459 #power-domain-cells = <1>;
462 scpi_sensors0: sensors {
463 compatible = "arm,scpi-sensors";
464 #thermal-sensor-cells = <1>;
470 polling-delay = <1000>;
471 polling-delay-passive = <100>;
472 thermal-sensors = <&scpi_sensors0 0>;
476 polling-delay = <1000>;
477 polling-delay-passive = <100>;
478 thermal-sensors = <&scpi_sensors0 3>;
481 big_cluster_thermal_zone: big_cluster {
482 polling-delay = <1000>;
483 polling-delay-passive = <100>;
484 thermal-sensors = <&scpi_sensors0 21>;
488 little_cluster_thermal_zone: little_cluster {
489 polling-delay = <1000>;
490 polling-delay-passive = <100>;
491 thermal-sensors = <&scpi_sensors0 22>;
495 gpu0_thermal_zone: gpu0 {
496 polling-delay = <1000>;
497 polling-delay-passive = <100>;
498 thermal-sensors = <&scpi_sensors0 23>;
502 gpu1_thermal_zone: gpu1 {
503 polling-delay = <1000>;
504 polling-delay-passive = <100>;
505 thermal-sensors = <&scpi_sensors0 24>;
510 /include/ "juno-clocks.dtsi"
512 smmu_dma: iommu@7fb00000 {
513 compatible = "arm,mmu-401", "arm,smmu-v1";
514 reg = <0x0 0x7fb00000 0x0 0x10000>;
515 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
518 #global-interrupts = <1>;
523 smmu_hdlcd1: iommu@7fb10000 {
524 compatible = "arm,mmu-401", "arm,smmu-v1";
525 reg = <0x0 0x7fb10000 0x0 0x10000>;
526 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
529 #global-interrupts = <1>;
533 smmu_hdlcd0: iommu@7fb20000 {
534 compatible = "arm,mmu-401", "arm,smmu-v1";
535 reg = <0x0 0x7fb20000 0x0 0x10000>;
536 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
539 #global-interrupts = <1>;
543 smmu_usb: iommu@7fb30000 {
544 compatible = "arm,mmu-401", "arm,smmu-v1";
545 reg = <0x0 0x7fb30000 0x0 0x10000>;
546 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
549 #global-interrupts = <1>;
555 compatible = "arm,pl330", "arm,primecell";
556 reg = <0x0 0x7ff00000 0 0x1000>;
559 #dma-requests = <32>;
560 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
569 iommus = <&smmu_dma 0>,
578 clocks = <&soc_faxiclk>;
579 clock-names = "apb_pclk";
583 compatible = "arm,hdlcd";
584 reg = <0 0x7ff50000 0 0x1000>;
585 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
586 iommus = <&smmu_hdlcd1 0>;
587 clocks = <&scpi_clk 3>;
588 clock-names = "pxlclk";
591 hdlcd1_output: hdlcd1-endpoint {
592 remote-endpoint = <&tda998x_1_input>;
598 compatible = "arm,hdlcd";
599 reg = <0 0x7ff60000 0 0x1000>;
600 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
601 iommus = <&smmu_hdlcd0 0>;
602 clocks = <&scpi_clk 3>;
603 clock-names = "pxlclk";
606 hdlcd0_output: hdlcd0-endpoint {
607 remote-endpoint = <&tda998x_0_input>;
612 soc_uart0: uart@7ff80000 {
613 compatible = "arm,pl011", "arm,primecell";
614 reg = <0x0 0x7ff80000 0x0 0x1000>;
615 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
617 clock-names = "uartclk", "apb_pclk";
621 compatible = "snps,designware-i2c";
622 reg = <0x0 0x7ffa0000 0x0 0x1000>;
623 #address-cells = <1>;
625 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
626 clock-frequency = <400000>;
627 i2c-sda-hold-time-ns = <500>;
628 clocks = <&soc_smc50mhz>;
630 hdmi-transmitter@70 {
631 compatible = "nxp,tda998x";
634 tda998x_0_input: tda998x-0-endpoint {
635 remote-endpoint = <&hdlcd0_output>;
640 hdmi-transmitter@71 {
641 compatible = "nxp,tda998x";
644 tda998x_1_input: tda998x-1-endpoint {
645 remote-endpoint = <&hdlcd1_output>;
652 compatible = "generic-ohci";
653 reg = <0x0 0x7ffb0000 0x0 0x10000>;
654 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
655 iommus = <&smmu_usb 0>;
656 clocks = <&soc_usb48mhz>;
660 compatible = "generic-ehci";
661 reg = <0x0 0x7ffc0000 0x0 0x10000>;
662 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
663 iommus = <&smmu_usb 0>;
664 clocks = <&soc_usb48mhz>;
667 memory-controller@7ffd0000 {
668 compatible = "arm,pl354", "arm,primecell";
669 reg = <0 0x7ffd0000 0 0x1000>;
670 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&soc_smc50mhz>;
673 clock-names = "apb_pclk";
677 device_type = "memory";
678 /* last 16MB of the first memory area is reserved for secure world use by firmware */
679 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
680 <0x00000008 0x80000000 0x1 0x80000000>;
684 compatible = "simple-bus";
685 #address-cells = <2>;
687 ranges = <0 0 0 0x08000000 0x04000000>,
688 <1 0 0 0x14000000 0x04000000>,
689 <2 0 0 0x18000000 0x04000000>,
690 <3 0 0 0x1c000000 0x04000000>,
691 <4 0 0 0x0c000000 0x04000000>,
692 <5 0 0 0x10000000 0x04000000>;
694 #interrupt-cells = <1>;
695 interrupt-map-mask = <0 0 15>;
696 interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
697 <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
698 <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
699 <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
700 <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
701 <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
702 <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
703 <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
704 <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
705 <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
706 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
707 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
708 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
710 /include/ "juno-motherboard.dtsi"
713 site2: tlx@60000000 {
714 compatible = "simple-bus";
715 #address-cells = <1>;
717 ranges = <0 0 0x60000000 0x10000000>;
718 #interrupt-cells = <1>;
719 interrupt-map-mask = <0 0>;
720 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;