2 * ARM Ltd. Juno Platform
4 * Copyright (c) 2015 ARM Ltd.
6 * This file is licensed under a dual GPLv2 or BSD license.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
16 model = "ARM Juno development board (r1)";
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
66 entry-method = "arm,psci";
68 CPU_SLEEP_0: cpu-sleep-0 {
69 compatible = "arm,idle-state";
70 arm,psci-suspend-param = <0x0010000>;
72 entry-latency-us = <300>;
73 exit-latency-us = <1200>;
74 min-residency-us = <2000>;
77 CLUSTER_SLEEP_0: cluster-sleep-0 {
78 compatible = "arm,idle-state";
79 arm,psci-suspend-param = <0x1010000>;
81 entry-latency-us = <400>;
82 exit-latency-us = <1200>;
83 min-residency-us = <2500>;
88 compatible = "arm,cortex-a57","arm,armv8";
91 enable-method = "psci";
92 next-level-cache = <&A57_L2>;
93 clocks = <&scpi_dvfs 0>;
94 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
95 capacity-dmips-mhz = <1024>;
99 compatible = "arm,cortex-a57","arm,armv8";
102 enable-method = "psci";
103 next-level-cache = <&A57_L2>;
104 clocks = <&scpi_dvfs 0>;
105 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
106 capacity-dmips-mhz = <1024>;
110 compatible = "arm,cortex-a53","arm,armv8";
113 enable-method = "psci";
114 next-level-cache = <&A53_L2>;
115 clocks = <&scpi_dvfs 1>;
116 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
117 capacity-dmips-mhz = <578>;
121 compatible = "arm,cortex-a53","arm,armv8";
124 enable-method = "psci";
125 next-level-cache = <&A53_L2>;
126 clocks = <&scpi_dvfs 1>;
127 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
128 capacity-dmips-mhz = <578>;
132 compatible = "arm,cortex-a53","arm,armv8";
135 enable-method = "psci";
136 next-level-cache = <&A53_L2>;
137 clocks = <&scpi_dvfs 1>;
138 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
139 capacity-dmips-mhz = <578>;
143 compatible = "arm,cortex-a53","arm,armv8";
146 enable-method = "psci";
147 next-level-cache = <&A53_L2>;
148 clocks = <&scpi_dvfs 1>;
149 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
150 capacity-dmips-mhz = <578>;
154 compatible = "cache";
158 compatible = "cache";
163 compatible = "arm,cortex-a57-pmu";
164 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-affinity = <&A57_0>,
171 compatible = "arm,cortex-a53-pmu";
172 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-affinity = <&A53_0>,
215 &big_cluster_thermal_zone {
219 &little_cluster_thermal_zone {
232 remote-endpoint = <&csys2_funnel_in_port0>;
235 &replicator_in_port0 {
236 remote-endpoint = <&csys2_funnel_out_port>;
240 remote-endpoint = <&csys1_funnel_in_port0>;