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33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/clock/bcm-ns2.h>
37 compatible = "brcm,ns2";
38 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a57", "arm,armv8";
50 enable-method = "psci";
51 next-level-cache = <&CLUSTER0_L2>;
56 compatible = "arm,cortex-a57", "arm,armv8";
58 enable-method = "psci";
59 next-level-cache = <&CLUSTER0_L2>;
64 compatible = "arm,cortex-a57", "arm,armv8";
66 enable-method = "psci";
67 next-level-cache = <&CLUSTER0_L2>;
72 compatible = "arm,cortex-a57", "arm,armv8";
74 enable-method = "psci";
75 next-level-cache = <&CLUSTER0_L2>;
78 CLUSTER0_L2: l2-cache@000 {
84 compatible = "arm,psci-1.0";
89 compatible = "arm,armv8-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
91 IRQ_TYPE_EDGE_RISING)>,
92 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
93 IRQ_TYPE_EDGE_RISING)>,
94 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
95 IRQ_TYPE_EDGE_RISING)>,
96 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
97 IRQ_TYPE_EDGE_RISING)>;
101 compatible = "arm,armv8-pmuv3";
102 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
106 interrupt-affinity = <&A57_0>,
112 pcie0: pcie@20020000 {
113 compatible = "brcm,iproc-pcie";
114 reg = <0 0x20020000 0 0x1000>;
116 #interrupt-cells = <1>;
117 interrupt-map-mask = <0 0 0 0>;
118 interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
120 linux,pci-domain = <0>;
122 bus-range = <0x00 0xff>;
124 #address-cells = <3>;
127 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
130 brcm,pcie-ob-oarr-size;
131 brcm,pcie-ob-axi-offset = <0x00000000>;
132 brcm,pcie-ob-window-size = <256>;
136 msi-parent = <&msi0>;
138 compatible = "brcm,iproc-msi";
140 interrupt-parent = <&gic>;
141 interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
142 <GIC_SPI 278 IRQ_TYPE_NONE>,
143 <GIC_SPI 279 IRQ_TYPE_NONE>,
144 <GIC_SPI 280 IRQ_TYPE_NONE>;
145 brcm,num-eq-region = <1>;
146 brcm,num-msi-msg-region = <1>;
150 pcie4: pcie@50020000 {
151 compatible = "brcm,iproc-pcie";
152 reg = <0 0x50020000 0 0x1000>;
154 #interrupt-cells = <1>;
155 interrupt-map-mask = <0 0 0 0>;
156 interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
158 linux,pci-domain = <4>;
160 bus-range = <0x00 0xff>;
162 #address-cells = <3>;
165 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
168 brcm,pcie-ob-oarr-size;
169 brcm,pcie-ob-axi-offset = <0x30000000>;
170 brcm,pcie-ob-window-size = <256>;
174 msi-parent = <&msi4>;
176 compatible = "brcm,iproc-msi";
178 interrupt-parent = <&gic>;
179 interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
180 <GIC_SPI 302 IRQ_TYPE_NONE>,
181 <GIC_SPI 303 IRQ_TYPE_NONE>,
182 <GIC_SPI 304 IRQ_TYPE_NONE>;
187 compatible = "simple-bus";
188 #address-cells = <1>;
190 ranges = <0 0 0 0xffffffff>;
192 #include "ns2-clock.dtsi"
195 compatible = "arm,pl330", "arm,primecell";
196 reg = <0x61360000 0x1000>;
197 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
208 #dma-requests = <32>;
209 clocks = <&iprocslow>;
210 clock-names = "apb_pclk";
214 compatible = "arm,mmu-500";
215 reg = <0x64000000 0x40000>;
216 #global-interrupts = <2>;
217 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
254 pinctrl: pinctrl@6501d130 {
255 compatible = "brcm,ns2-pinmux";
256 reg = <0x6501d130 0x08>,
261 gpio_aon: gpio@65024800 {
262 compatible = "brcm,iproc-gpio";
263 reg = <0x65024800 0x50>,
270 gic: interrupt-controller@65210000 {
271 compatible = "arm,gic-400";
272 #interrupt-cells = <3>;
273 interrupt-controller;
274 reg = <0x65210000 0x1000>,
278 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
279 IRQ_TYPE_LEVEL_HIGH)>;
283 compatible = "arm,cci-400";
284 #address-cells = <1>;
286 reg = <0x65590000 0x1000>;
287 ranges = <0 0x65590000 0x10000>;
290 compatible = "arm,cci-400-pmu,r1",
292 reg = <0x9000 0x4000>;
293 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
303 compatible = "brcm,iproc-pwm";
304 reg = <0x66010000 0x28>;
310 mdio_mux_iproc: mdio-mux@6602023c {
311 compatible = "brcm,mdio-mux-iproc";
312 reg = <0x6602023c 0x14>;
313 #address-cells = <1>;
318 #address-cells = <1>;
321 pci_phy0: pci-phy@0 {
322 compatible = "brcm,ns2-pcie-phy";
331 #address-cells = <1>;
334 pci_phy1: pci-phy@0 {
335 compatible = "brcm,ns2-pcie-phy";
344 #address-cells = <1>;
349 timer0: timer@66030000 {
350 compatible = "arm,sp804", "arm,primecell";
351 reg = <0x66030000 0x1000>;
352 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&iprocslow>,
356 clock-names = "timer1", "timer2", "apb_pclk";
359 timer1: timer@66040000 {
360 compatible = "arm,sp804", "arm,primecell";
361 reg = <0x66040000 0x1000>;
362 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&iprocslow>,
366 clock-names = "timer1", "timer2", "apb_pclk";
369 timer2: timer@66050000 {
370 compatible = "arm,sp804", "arm,primecell";
371 reg = <0x66050000 0x1000>;
372 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&iprocslow>,
376 clock-names = "timer1", "timer2", "apb_pclk";
379 timer3: timer@66060000 {
380 compatible = "arm,sp804", "arm,primecell";
381 reg = <0x66060000 0x1000>;
382 interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&iprocslow>,
386 clock-names = "timer1", "timer2", "apb_pclk";
390 compatible = "brcm,iproc-i2c";
391 reg = <0x66080000 0x100>;
392 #address-cells = <1>;
394 interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
395 clock-frequency = <100000>;
399 wdt0: watchdog@66090000 {
400 compatible = "arm,sp805", "arm,primecell";
401 reg = <0x66090000 0x1000>;
402 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&iprocslow>, <&iprocslow>;
404 clock-names = "wdogclk", "apb_pclk";
407 gpio_g: gpio@660a0000 {
408 compatible = "brcm,iproc-gpio";
409 reg = <0x660a0000 0x50>;
413 interrupt-controller;
414 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
418 compatible = "brcm,iproc-i2c";
419 reg = <0x660b0000 0x100>;
420 #address-cells = <1>;
422 interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
423 clock-frequency = <100000>;
427 uart0: serial@66100000 {
428 compatible = "snps,dw-apb-uart";
429 reg = <0x66100000 0x100>;
430 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&iprocslow>;
437 uart1: serial@66110000 {
438 compatible = "snps,dw-apb-uart";
439 reg = <0x66110000 0x100>;
440 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&iprocslow>;
447 uart2: serial@66120000 {
448 compatible = "snps,dw-apb-uart";
449 reg = <0x66120000 0x100>;
450 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&iprocslow>;
457 uart3: serial@66130000 {
458 compatible = "snps,dw-apb-uart";
459 reg = <0x66130000 0x100>;
460 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
468 compatible = "arm,pl022", "arm,primecell";
469 reg = <0x66180000 0x1000>;
470 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&iprocslow>, <&iprocslow>;
472 clock-names = "spiclk", "apb_pclk";
473 #address-cells = <1>;
479 compatible = "arm,pl022", "arm,primecell";
480 reg = <0x66190000 0x1000>;
481 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&iprocslow>, <&iprocslow>;
483 clock-names = "spiclk", "apb_pclk";
484 #address-cells = <1>;
489 hwrng: hwrng@66220000 {
490 compatible = "brcm,iproc-rng200";
491 reg = <0x66220000 0x28>;
494 sata_phy: sata_phy@663f0100 {
495 compatible = "brcm,iproc-ns2-sata-phy";
496 reg = <0x663f0100 0x1f00>,
498 reg-names = "phy", "phy-ctrl";
499 #address-cells = <1>;
502 sata_phy0: sata-phy@0 {
508 sata_phy1: sata-phy@1 {
515 sata: ahci@663f2000 {
516 compatible = "brcm,iproc-ahci", "generic-ahci";
517 reg = <0x663f2000 0x1000>;
519 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
520 #address-cells = <1>;
527 phy-names = "sata-phy";
533 phy-names = "sata-phy";
537 sdio0: sdhci@66420000 {
538 compatible = "brcm,sdhci-iproc-cygnus";
539 reg = <0x66420000 0x100>;
540 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
546 sdio1: sdhci@66430000 {
547 compatible = "brcm,sdhci-iproc-cygnus";
548 reg = <0x66430000 0x100>;
549 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
555 nand: nand@66460000 {
556 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
557 reg = <0x66460000 0x600>,
560 reg-names = "nand", "iproc-idm", "iproc-ext";
561 interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;