arch/arm64/boot/dts/broadcom/ns2.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright (c) 2015 Broadcom.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /memreserve/ 0x81000000 0x00200000;
  34
  35 #include <dt-bindings/interrupt-controller/arm-gic.h>
  36 #include <dt-bindings/clock/bcm-ns2.h>
  37
  38 / {
  39         compatible = "brcm,ns2";
  40         interrupt-parent = <&gic>;
  41         #address-cells = <2>;
  42         #size-cells = <2>;
  43
  44         cpus {
  45                 #address-cells = <2>;
  46                 #size-cells = <0>;
  47
  48                 A57_0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a57", "arm,armv8";
  51                         reg = <0 0>;
  52                         enable-method = "psci";
  53                         next-level-cache = <&CLUSTER0_L2>;
  54                 };
  55
  56                 A57_1: cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a57", "arm,armv8";
  59                         reg = <0 1>;
  60                         enable-method = "psci";
  61                         next-level-cache = <&CLUSTER0_L2>;
  62                 };
  63
  64                 A57_2: cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a57", "arm,armv8";
  67                         reg = <0 2>;
  68                         enable-method = "psci";
  69                         next-level-cache = <&CLUSTER0_L2>;
  70                 };
  71
  72                 A57_3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a57", "arm,armv8";
  75                         reg = <0 3>;
  76                         enable-method = "psci";
  77                         next-level-cache = <&CLUSTER0_L2>;
  78                 };
  79
  80                 CLUSTER0_L2: l2-cache@000 {
  81                         compatible = "cache";
  82                 };
  83         };
  84
  85         psci {
  86                 compatible = "arm,psci-1.0";
  87                 method = "smc";
  88         };
  89
  90         timer {
  91                 compatible = "arm,armv8-timer";
  92                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
  93                               IRQ_TYPE_LEVEL_LOW)>,
  94                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
  95                               IRQ_TYPE_LEVEL_LOW)>,
  96                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
  97                               IRQ_TYPE_LEVEL_LOW)>,
  98                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
  99                               IRQ_TYPE_LEVEL_LOW)>;
 100         };
 101
 102         pmu {
 103                 compatible = "arm,armv8-pmuv3";
 104                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 107                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 108                 interrupt-affinity = <&A57_0>,
 109                                      <&A57_1>,
 110                                      <&A57_2>,
 111                                      <&A57_3>;
 112         };
 113
 114         pcie0: pcie@20020000 {
 115                 compatible = "brcm,iproc-pcie";
 116                 reg = <0 0x20020000 0 0x1000>;
 117                 dma-coherent;
 118
 119                 #interrupt-cells = <1>;
 120                 interrupt-map-mask = <0 0 0 0>;
 121                 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_NONE>;
 122
 123                 linux,pci-domain = <0>;
 124
 125                 bus-range = <0x00 0xff>;
 126
 127                 #address-cells = <3>;
 128                 #size-cells = <2>;
 129                 device_type = "pci";
 130                 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
 131
 132                 brcm,pcie-ob;
 133                 brcm,pcie-ob-oarr-size;
 134                 brcm,pcie-ob-axi-offset = <0x00000000>;
 135                 brcm,pcie-ob-window-size = <256>;
 136
 137                 status = "disabled";
 138
 139                 phys = <&pci_phy0>;
 140                 phy-names = "pcie-phy";
 141
 142                 msi-parent = <&v2m0>;
 143         };
 144
 145         pcie4: pcie@50020000 {
 146                 compatible = "brcm,iproc-pcie";
 147                 reg = <0 0x50020000 0 0x1000>;
 148                 dma-coherent;
 149
 150                 #interrupt-cells = <1>;
 151                 interrupt-map-mask = <0 0 0 0>;
 152                 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_NONE>;
 153
 154                 linux,pci-domain = <4>;
 155
 156                 bus-range = <0x00 0xff>;
 157
 158                 #address-cells = <3>;
 159                 #size-cells = <2>;
 160                 device_type = "pci";
 161                 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
 162
 163                 brcm,pcie-ob;
 164                 brcm,pcie-ob-oarr-size;
 165                 brcm,pcie-ob-axi-offset = <0x30000000>;
 166                 brcm,pcie-ob-window-size = <256>;
 167
 168                 status = "disabled";
 169
 170                 phys = <&pci_phy1>;
 171                 phy-names = "pcie-phy";
 172
 173                 msi-parent = <&v2m0>;
 174         };
 175
 176         pcie8: pcie@60c00000 {
 177                 compatible = "brcm,iproc-pcie-paxc";
 178                 reg = <0 0x60c00000 0 0x1000>;
 179                 dma-coherent;
 180                 linux,pci-domain = <8>;
 181
 182                 bus-range = <0x0 0x1>;
 183
 184                 #address-cells = <3>;
 185                 #size-cells = <2>;
 186                 device_type = "pci";
 187                 ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
 188
 189                 status = "disabled";
 190
 191                 msi-parent = <&v2m0>;
 192         };
 193
 194         soc: soc {
 195                 compatible = "simple-bus";
 196                 #address-cells = <1>;
 197                 #size-cells = <1>;
 198                 ranges = <0 0 0 0xffffffff>;
 199
 200                 #include "ns2-clock.dtsi"
 201
 202                 enet: ethernet@61000000 {
 203                         compatible = "brcm,ns2-amac";
 204                         reg = <0x61000000 0x1000>,
 205                               <0x61090000 0x1000>,
 206                               <0x61030000 0x100>;
 207                         reg-names = "amac_base", "idm_base", "nicpm_base";
 208                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 209                         dma-coherent;
 210                         phy-handle = <&gphy0>;
 211                         phy-mode = "rgmii";
 212                         status = "disabled";
 213                 };
 214
 215                 pdc0: iproc-pdc0@612c0000 {
 216                         compatible = "brcm,iproc-pdc-mbox";
 217                         reg = <0x612c0000 0x445>;  /* PDC FS0 regs */
 218                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 219                         #mbox-cells = <1>;
 220                         dma-coherent;
 221                         brcm,rx-status-len = <32>;
 222                         brcm,use-bcm-hdr;
 223                 };
 224
 225                 pdc1: iproc-pdc1@612e0000 {
 226                         compatible = "brcm,iproc-pdc-mbox";
 227                         reg = <0x612e0000 0x445>;  /* PDC FS1 regs */
 228                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 229                         #mbox-cells = <1>;
 230                         dma-coherent;
 231                         brcm,rx-status-len = <32>;
 232                         brcm,use-bcm-hdr;
 233                 };
 234
 235                 pdc2: iproc-pdc2@61300000 {
 236                         compatible = "brcm,iproc-pdc-mbox";
 237                         reg = <0x61300000 0x445>;  /* PDC FS2 regs */
 238                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 239                         #mbox-cells = <1>;
 240                         dma-coherent;
 241                         brcm,rx-status-len = <32>;
 242                         brcm,use-bcm-hdr;
 243                 };
 244
 245                 pdc3: iproc-pdc3@61320000 {
 246                         compatible = "brcm,iproc-pdc-mbox";
 247                         reg = <0x61320000 0x445>;  /* PDC FS3 regs */
 248                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 249                         #mbox-cells = <1>;
 250                         dma-coherent;
 251                         brcm,rx-status-len = <32>;
 252                         brcm,use-bcm-hdr;
 253                 };
 254
 255                 dma0: dma@61360000 {
 256                         compatible = "arm,pl330", "arm,primecell";
 257                         reg = <0x61360000 0x1000>;
 258                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 259                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
 260                                      <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 261                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 262                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 263                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 264                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 265                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 266                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 267                         #dma-cells = <1>;
 268                         #dma-channels = <8>;
 269                         #dma-requests = <32>;
 270                         clocks = <&iprocslow>;
 271                         clock-names = "apb_pclk";
 272                 };
 273
 274                 smmu: mmu@64000000 {
 275                         compatible = "arm,mmu-500";
 276                         reg = <0x64000000 0x40000>;
 277                         #global-interrupts = <2>;
 278                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 280                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
 284                                      <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 287                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 288                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 292                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 293                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 294                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 295                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 297                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 298                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 299                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 300                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 301                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 302                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 306                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 307                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 309                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
 312                         #iommu-cells = <1>;
 313                 };
 314
 315                 pinctrl: pinctrl@6501d130 {
 316                         compatible = "brcm,ns2-pinmux";
 317                         reg = <0x6501d130 0x08>,
 318                               <0x660a0028 0x04>,
 319                               <0x660009b0 0x40>;
 320                 };
 321
 322                 gpio_aon: gpio@65024800 {
 323                         compatible = "brcm,iproc-gpio";
 324                         reg = <0x65024800 0x50>,
 325                               <0x65024008 0x18>;
 326                         ngpios = <6>;
 327                         #gpio-cells = <2>;
 328                         gpio-controller;
 329                 };
 330
 331                 gic: interrupt-controller@65210000 {
 332                         compatible = "arm,gic-400";
 333                         #interrupt-cells = <3>;
 334                         interrupt-controller;
 335                         reg = <0x65210000 0x1000>,
 336                               <0x65220000 0x1000>,
 337                               <0x65240000 0x2000>,
 338                               <0x65260000 0x1000>;
 339                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 340                                       IRQ_TYPE_LEVEL_HIGH)>;
 341
 342                         #address-cells = <1>;
 343                         #size-cells = <1>;
 344                         ranges = <0 0x652e0000 0x80000>;
 345
 346                         v2m0: v2m@00000 {
 347                                 compatible = "arm,gic-v2m-frame";
 348                                 interrupt-parent = <&gic>;
 349                                 msi-controller;
 350                                 reg = <0x00000 0x1000>;
 351                                 arm,msi-base-spi = <72>;
 352                                 arm,msi-num-spis = <16>;
 353                         };
 354
 355                         v2m1: v2m@10000 {
 356                                 compatible = "arm,gic-v2m-frame";
 357                                 interrupt-parent = <&gic>;
 358                                 msi-controller;
 359                                 reg = <0x10000 0x1000>;
 360                                 arm,msi-base-spi = <88>;
 361                                 arm,msi-num-spis = <16>;
 362                         };
 363
 364                         v2m2: v2m@20000 {
 365                                 compatible = "arm,gic-v2m-frame";
 366                                 interrupt-parent = <&gic>;
 367                                 msi-controller;
 368                                 reg = <0x20000 0x1000>;
 369                                 arm,msi-base-spi = <104>;
 370                                 arm,msi-num-spis = <16>;
 371                         };
 372
 373                         v2m3: v2m@30000 {
 374                                 compatible = "arm,gic-v2m-frame";
 375                                 interrupt-parent = <&gic>;
 376                                 msi-controller;
 377                                 reg = <0x30000 0x1000>;
 378                                 arm,msi-base-spi = <120>;
 379                                 arm,msi-num-spis = <16>;
 380                         };
 381
 382                         v2m4: v2m@40000 {
 383                                 compatible = "arm,gic-v2m-frame";
 384                                 interrupt-parent = <&gic>;
 385                                 msi-controller;
 386                                 reg = <0x40000 0x1000>;
 387                                 arm,msi-base-spi = <136>;
 388                                 arm,msi-num-spis = <16>;
 389                         };
 390
 391                         v2m5: v2m@50000 {
 392                                 compatible = "arm,gic-v2m-frame";
 393                                 interrupt-parent = <&gic>;
 394                                 msi-controller;
 395                                 reg = <0x50000 0x1000>;
 396                                 arm,msi-base-spi = <152>;
 397                                 arm,msi-num-spis = <16>;
 398                         };
 399
 400                         v2m6: v2m@60000 {
 401                                 compatible = "arm,gic-v2m-frame";
 402                                 interrupt-parent = <&gic>;
 403                                 msi-controller;
 404                                 reg = <0x60000 0x1000>;
 405                                 arm,msi-base-spi = <168>;
 406                                 arm,msi-num-spis = <16>;
 407                         };
 408
 409                         v2m7: v2m@70000 {
 410                                 compatible = "arm,gic-v2m-frame";
 411                                 interrupt-parent = <&gic>;
 412                                 msi-controller;
 413                                 reg = <0x70000 0x1000>;
 414                                 arm,msi-base-spi = <184>;
 415                                 arm,msi-num-spis = <16>;
 416                         };
 417                 };
 418
 419                 cci@65590000 {
 420                         compatible = "arm,cci-400";
 421                         #address-cells = <1>;
 422                         #size-cells = <1>;
 423                         reg = <0x65590000 0x1000>;
 424                         ranges = <0 0x65590000 0x10000>;
 425
 426                         pmu@9000 {
 427                                 compatible = "arm,cci-400-pmu,r1",
 428                                              "arm,cci-400-pmu";
 429                                 reg = <0x9000 0x4000>;
 430                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 431                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 432                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
 433                                              <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 434                                              <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 435                                              <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
 436                         };
 437                 };
 438
 439                 pwm: pwm@66010000 {
 440                         compatible = "brcm,iproc-pwm";
 441                         reg = <0x66010000 0x28>;
 442                         clocks = <&osc>;
 443                         #pwm-cells = <3>;
 444                         status = "disabled";
 445                 };
 446
 447                 mdio_mux_iproc: mdio-mux@6602023c {
 448                         compatible = "brcm,mdio-mux-iproc";
 449                         reg = <0x6602023c 0x14>;
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452
 453                         mdio@0 {
 454                                 reg = <0x0>;
 455                                 #address-cells = <1>;
 456                                 #size-cells = <0>;
 457
 458                                 pci_phy0: pci-phy@0 {
 459                                         compatible = "brcm,ns2-pcie-phy";
 460                                         reg = <0x0>;
 461                                         #phy-cells = <0>;
 462                                         status = "disabled";
 463                                 };
 464                         };
 465
 466                         mdio@7 {
 467                                 reg = <0x7>;
 468                                 #address-cells = <1>;
 469                                 #size-cells = <0>;
 470
 471                                 pci_phy1: pci-phy@0 {
 472                                         compatible = "brcm,ns2-pcie-phy";
 473                                         reg = <0x0>;
 474                                         #phy-cells = <0>;
 475                                         status = "disabled";
 476                                 };
 477                         };
 478
 479                         mdio@10 {
 480                                 reg = <0x10>;
 481                                 #address-cells = <1>;
 482                                 #size-cells = <0>;
 483                         };
 484                 };
 485
 486                 timer0: timer@66030000 {
 487                         compatible = "arm,sp804", "arm,primecell";
 488                         reg = <0x66030000 0x1000>;
 489                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&iprocslow>,
 491                                  <&iprocslow>,
 492                                  <&iprocslow>;
 493                         clock-names = "timer1", "timer2", "apb_pclk";
 494                 };
 495
 496                 timer1: timer@66040000 {
 497                         compatible = "arm,sp804", "arm,primecell";
 498                         reg = <0x66040000 0x1000>;
 499                         interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 500                         clocks = <&iprocslow>,
 501                                  <&iprocslow>,
 502                                  <&iprocslow>;
 503                         clock-names = "timer1", "timer2", "apb_pclk";
 504                 };
 505
 506                 timer2: timer@66050000 {
 507                         compatible = "arm,sp804", "arm,primecell";
 508                         reg = <0x66050000 0x1000>;
 509                         interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&iprocslow>,
 511                                  <&iprocslow>,
 512                                  <&iprocslow>;
 513                         clock-names = "timer1", "timer2", "apb_pclk";
 514                 };
 515
 516                 timer3: timer@66060000 {
 517                         compatible = "arm,sp804", "arm,primecell";
 518                         reg = <0x66060000 0x1000>;
 519                         interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&iprocslow>,
 521                                  <&iprocslow>,
 522                                  <&iprocslow>;
 523                         clock-names = "timer1", "timer2", "apb_pclk";
 524                 };
 525
 526                 i2c0: i2c@66080000 {
 527                         compatible = "brcm,iproc-i2c";
 528                         reg = <0x66080000 0x100>;
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
 532                         clock-frequency = <100000>;
 533                         status = "disabled";
 534                 };
 535
 536                 wdt0: watchdog@66090000 {
 537                         compatible = "arm,sp805", "arm,primecell";
 538                         reg = <0x66090000 0x1000>;
 539                         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
 540                         clocks = <&iprocslow>, <&iprocslow>;
 541                         clock-names = "wdogclk", "apb_pclk";
 542                 };
 543
 544                 gpio_g: gpio@660a0000 {
 545                         compatible = "brcm,iproc-gpio";
 546                         reg = <0x660a0000 0x50>;
 547                         ngpios = <32>;
 548                         #gpio-cells = <2>;
 549                         gpio-controller;
 550                         interrupt-controller;
 551                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
 552                 };
 553
 554                 i2c1: i2c@660b0000 {
 555                         compatible = "brcm,iproc-i2c";
 556                         reg = <0x660b0000 0x100>;
 557                         #address-cells = <1>;
 558                         #size-cells = <0>;
 559                         interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
 560                         clock-frequency = <100000>;
 561                         status = "disabled";
 562                 };
 563
 564                 uart0: serial@66100000 {
 565                         compatible = "snps,dw-apb-uart";
 566                         reg = <0x66100000 0x100>;
 567                         interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
 568                         clocks = <&iprocslow>;
 569                         reg-shift = <2>;
 570                         reg-io-width = <4>;
 571                         status = "disabled";
 572                 };
 573
 574                 uart1: serial@66110000 {
 575                         compatible = "snps,dw-apb-uart";
 576                         reg = <0x66110000 0x100>;
 577                         interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
 578                         clocks = <&iprocslow>;
 579                         reg-shift = <2>;
 580                         reg-io-width = <4>;
 581                         status = "disabled";
 582                 };
 583
 584                 uart2: serial@66120000 {
 585                         compatible = "snps,dw-apb-uart";
 586                         reg = <0x66120000 0x100>;
 587                         interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
 588                         clocks = <&iprocslow>;
 589                         reg-shift = <2>;
 590                         reg-io-width = <4>;
 591                         status = "disabled";
 592                 };
 593
 594                 uart3: serial@66130000 {
 595                         compatible = "snps,dw-apb-uart";
 596                         reg = <0x66130000 0x100>;
 597                         interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
 598                         reg-shift = <2>;
 599                         reg-io-width = <4>;
 600                         clocks = <&osc>;
 601                         status = "disabled";
 602                 };
 603
 604                 ssp0: ssp@66180000 {
 605                         compatible = "arm,pl022", "arm,primecell";
 606                         reg = <0x66180000 0x1000>;
 607                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 608                         clocks = <&iprocslow>, <&iprocslow>;
 609                         clock-names = "spiclk", "apb_pclk";
 610                         #address-cells = <1>;
 611                         #size-cells = <0>;
 612                         status = "disabled";
 613                 };
 614
 615                 ssp1: ssp@66190000 {
 616                         compatible = "arm,pl022", "arm,primecell";
 617                         reg = <0x66190000 0x1000>;
 618                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 619                         clocks = <&iprocslow>, <&iprocslow>;
 620                         clock-names = "spiclk", "apb_pclk";
 621                         #address-cells = <1>;
 622                         #size-cells = <0>;
 623                         status = "disabled";
 624                 };
 625
 626                 hwrng: hwrng@66220000 {
 627                         compatible = "brcm,iproc-rng200";
 628                         reg = <0x66220000 0x28>;
 629                 };
 630
 631                 sata_phy: sata_phy@663f0100 {
 632                         compatible = "brcm,iproc-ns2-sata-phy";
 633                         reg = <0x663f0100 0x1f00>,
 634                               <0x663f004c 0x10>;
 635                         reg-names = "phy", "phy-ctrl";
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638
 639                         sata_phy0: sata-phy@0 {
 640                                 reg = <0>;
 641                                 #phy-cells = <0>;
 642                                 status = "disabled";
 643                         };
 644
 645                         sata_phy1: sata-phy@1 {
 646                                 reg = <1>;
 647                                 #phy-cells = <0>;
 648                                 status = "disabled";
 649                         };
 650                 };
 651
 652                 sata: ahci@663f2000 {
 653                         compatible = "brcm,iproc-ahci", "generic-ahci";
 654                         reg = <0x663f2000 0x1000>;
 655                         dma-coherent;
 656                         reg-names = "ahci";
 657                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                         status = "disabled";
 661
 662                         sata0: sata-port@0 {
 663                                 reg = <0>;
 664                                 phys = <&sata_phy0>;
 665                                 phy-names = "sata-phy";
 666                         };
 667
 668                         sata1: sata-port@1 {
 669                                 reg = <1>;
 670                                 phys = <&sata_phy1>;
 671                                 phy-names = "sata-phy";
 672                         };
 673                 };
 674
 675                 sdio0: sdhci@66420000 {
 676                         compatible = "brcm,sdhci-iproc-cygnus";
 677                         reg = <0x66420000 0x100>;
 678                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 679                         dma-coherent;
 680                         bus-width = <8>;
 681                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 682                         status = "disabled";
 683                 };
 684
 685                 sdio1: sdhci@66430000 {
 686                         compatible = "brcm,sdhci-iproc-cygnus";
 687                         reg = <0x66430000 0x100>;
 688                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 689                         dma-coherent;
 690                         bus-width = <8>;
 691                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 692                         status = "disabled";
 693                 };
 694
 695                 nand: nand@66460000 {
 696                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 697                         reg = <0x66460000 0x600>,
 698                               <0x67015408 0x600>,
 699                               <0x66460f00 0x20>;
 700                         reg-names = "nand", "iproc-idm", "iproc-ext";
 701                         interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 702
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705
 706                         brcm,nand-has-wp;
 707                 };
 708
 709                 qspi: spi@66470200 {
 710                         compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
 711                         reg = <0x66470200 0x184>,
 712                                 <0x66470000 0x124>,
 713                                 <0x67017408 0x004>,
 714                                 <0x664703a0 0x01c>;
 715                         reg-names = "mspi", "bspi", "intr_regs",
 716                                 "intr_status_reg";
 717                         interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
 718                         interrupt-names = "spi_l1_intr";
 719                         clocks = <&iprocmed>;
 720                         clock-names = "iprocmed";
 721                         num-cs = <2>;
 722                         #address-cells = <1>;
 723                         #size-cells = <0>;
 724                 };
 725
 726         };
 727 };