arch/arm64/boot/dts/exynos/exynos5433.dtsi

   1 /*
   2  * Samsung's Exynos5433 SoC device tree source
   3  *
   4  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
   5  *
   6  * Samsung's Exynos5433 SoC device nodes are listed in this file.
   7  * Exynos5433 based board files can include this file and provide
   8  * values for board specific bindings.
   9  *
  10  * Note: This file does not include device nodes for all the controllers in
  11  * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
  12  * additional nodes can be added to this file.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include <dt-bindings/clock/exynos5433.h>
  20 #include <dt-bindings/interrupt-controller/arm-gic.h>
  21
  22 / {
  23         compatible = "samsung,exynos5433";
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         interrupt-parent = <&gic>;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@100 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53", "arm,armv8";
  36                         enable-method = "psci";
  37                         reg = <0x100>;
  38                         clock-frequency = <1300000000>;
  39                         clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
  40                         clock-names = "apolloclk";
  41                         operating-points-v2 = <&cluster_a53_opp_table>;
  42                         #cooling-cells = <2>;
  43                 };
  44
  45                 cpu1: cpu@101 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a53", "arm,armv8";
  48                         enable-method = "psci";
  49                         reg = <0x101>;
  50                         clock-frequency = <1300000000>;
  51                         operating-points-v2 = <&cluster_a53_opp_table>;
  52                         #cooling-cells = <2>;
  53                 };
  54
  55                 cpu2: cpu@102 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53", "arm,armv8";
  58                         enable-method = "psci";
  59                         reg = <0x102>;
  60                         clock-frequency = <1300000000>;
  61                         operating-points-v2 = <&cluster_a53_opp_table>;
  62                         #cooling-cells = <2>;
  63                 };
  64
  65                 cpu3: cpu@103 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         enable-method = "psci";
  69                         reg = <0x103>;
  70                         clock-frequency = <1300000000>;
  71                         operating-points-v2 = <&cluster_a53_opp_table>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu4: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a57", "arm,armv8";
  78                         enable-method = "psci";
  79                         reg = <0x0>;
  80                         clock-frequency = <1900000000>;
  81                         clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
  82                         clock-names = "atlasclk";
  83                         operating-points-v2 = <&cluster_a57_opp_table>;
  84                         #cooling-cells = <2>;
  85                 };
  86
  87                 cpu5: cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a57", "arm,armv8";
  90                         enable-method = "psci";
  91                         reg = <0x1>;
  92                         clock-frequency = <1900000000>;
  93                         operating-points-v2 = <&cluster_a57_opp_table>;
  94                         #cooling-cells = <2>;
  95                 };
  96
  97                 cpu6: cpu@2 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a57", "arm,armv8";
 100                         enable-method = "psci";
 101                         reg = <0x2>;
 102                         clock-frequency = <1900000000>;
 103                         operating-points-v2 = <&cluster_a57_opp_table>;
 104                         #cooling-cells = <2>;
 105                 };
 106
 107                 cpu7: cpu@3 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a57", "arm,armv8";
 110                         enable-method = "psci";
 111                         reg = <0x3>;
 112                         clock-frequency = <1900000000>;
 113                         operating-points-v2 = <&cluster_a57_opp_table>;
 114                         #cooling-cells = <2>;
 115                 };
 116         };
 117
 118         cluster_a53_opp_table: opp_table0 {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121
 122                 opp@400000000 {
 123                         opp-hz = /bits/ 64 <400000000>;
 124                         opp-microvolt = <900000>;
 125                 };
 126                 opp@500000000 {
 127                         opp-hz = /bits/ 64 <500000000>;
 128                         opp-microvolt = <925000>;
 129                 };
 130                 opp@600000000 {
 131                         opp-hz = /bits/ 64 <600000000>;
 132                         opp-microvolt = <950000>;
 133                 };
 134                 opp@700000000 {
 135                         opp-hz = /bits/ 64 <700000000>;
 136                         opp-microvolt = <975000>;
 137                 };
 138                 opp@800000000 {
 139                         opp-hz = /bits/ 64 <800000000>;
 140                         opp-microvolt = <1000000>;
 141                 };
 142                 opp@900000000 {
 143                         opp-hz = /bits/ 64 <900000000>;
 144                         opp-microvolt = <1050000>;
 145                 };
 146                 opp@1000000000 {
 147                         opp-hz = /bits/ 64 <1000000000>;
 148                         opp-microvolt = <1075000>;
 149                 };
 150                 opp@1100000000 {
 151                         opp-hz = /bits/ 64 <1100000000>;
 152                         opp-microvolt = <1112500>;
 153                 };
 154                 opp@1200000000 {
 155                         opp-hz = /bits/ 64 <1200000000>;
 156                         opp-microvolt = <1112500>;
 157                 };
 158                 opp@1300000000 {
 159                         opp-hz = /bits/ 64 <1300000000>;
 160                         opp-microvolt = <1150000>;
 161                 };
 162         };
 163
 164         cluster_a57_opp_table: opp_table1 {
 165                 compatible = "operating-points-v2";
 166                 opp-shared;
 167
 168                 opp@500000000 {
 169                         opp-hz = /bits/ 64 <500000000>;
 170                         opp-microvolt = <900000>;
 171                 };
 172                 opp@600000000 {
 173                         opp-hz = /bits/ 64 <600000000>;
 174                         opp-microvolt = <900000>;
 175                 };
 176                 opp@700000000 {
 177                         opp-hz = /bits/ 64 <700000000>;
 178                         opp-microvolt = <912500>;
 179                 };
 180                 opp@800000000 {
 181                         opp-hz = /bits/ 64 <800000000>;
 182                         opp-microvolt = <912500>;
 183                 };
 184                 opp@900000000 {
 185                         opp-hz = /bits/ 64 <900000000>;
 186                         opp-microvolt = <937500>;
 187                 };
 188                 opp@1000000000 {
 189                         opp-hz = /bits/ 64 <1000000000>;
 190                         opp-microvolt = <975000>;
 191                 };
 192                 opp@1100000000 {
 193                         opp-hz = /bits/ 64 <1100000000>;
 194                         opp-microvolt = <1012500>;
 195                 };
 196                 opp@1200000000 {
 197                         opp-hz = /bits/ 64 <1200000000>;
 198                         opp-microvolt = <1037500>;
 199                 };
 200                 opp@1300000000 {
 201                         opp-hz = /bits/ 64 <1300000000>;
 202                         opp-microvolt = <1062500>;
 203                 };
 204                 opp@1400000000 {
 205                         opp-hz = /bits/ 64 <1400000000>;
 206                         opp-microvolt = <1087500>;
 207                 };
 208                 opp@1500000000 {
 209                         opp-hz = /bits/ 64 <1500000000>;
 210                         opp-microvolt = <1125000>;
 211                 };
 212                 opp@1600000000 {
 213                         opp-hz = /bits/ 64 <1600000000>;
 214                         opp-microvolt = <1137500>;
 215                 };
 216                 opp@1700000000 {
 217                         opp-hz = /bits/ 64 <1700000000>;
 218                         opp-microvolt = <1175000>;
 219                 };
 220                 opp@1800000000 {
 221                         opp-hz = /bits/ 64 <1800000000>;
 222                         opp-microvolt = <1212500>;
 223                 };
 224                 opp@1900000000 {
 225                         opp-hz = /bits/ 64 <1900000000>;
 226                         opp-microvolt = <1262500>;
 227                 };
 228         };
 229
 230         psci {
 231                 compatible = "arm,psci";
 232                 method = "smc";
 233                 cpu_off = <0x84000002>;
 234                 cpu_on = <0xC4000003>;
 235         };
 236
 237         reboot: syscon-reboot {
 238                 compatible = "syscon-reboot";
 239                 regmap = <&pmu_system_controller>;
 240                 offset = <0x400>; /* SWRESET */
 241                 mask = <0x1>;
 242         };
 243
 244         soc: soc {
 245                 compatible = "simple-bus";
 246                 #address-cells = <1>;
 247                 #size-cells = <1>;
 248                 ranges = <0x0 0x0 0x0 0x18000000>;
 249
 250                 chipid@10000000 {
 251                         compatible = "samsung,exynos4210-chipid";
 252                         reg = <0x10000000 0x100>;
 253                 };
 254
 255                 xxti: xxti {
 256                         compatible = "fixed-clock";
 257                         clock-output-names = "oscclk";
 258                         #clock-cells = <0>;
 259                 };
 260
 261                 cmu_top: clock-controller@10030000 {
 262                         compatible = "samsung,exynos5433-cmu-top";
 263                         reg = <0x10030000 0x1000>;
 264                         #clock-cells = <1>;
 265
 266                         clock-names = "oscclk",
 267                                 "sclk_mphy_pll",
 268                                 "sclk_mfc_pll",
 269                                 "sclk_bus_pll";
 270                         clocks = <&xxti>,
 271                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
 272                                 <&cmu_mif CLK_SCLK_MFC_PLL>,
 273                                 <&cmu_mif CLK_SCLK_BUS_PLL>;
 274                 };
 275
 276                 cmu_cpif: clock-controller@10fc0000 {
 277                         compatible = "samsung,exynos5433-cmu-cpif";
 278                         reg = <0x10fc0000 0x1000>;
 279                         #clock-cells = <1>;
 280
 281                         clock-names = "oscclk";
 282                         clocks = <&xxti>;
 283                 };
 284
 285                 cmu_mif: clock-controller@105b0000 {
 286                         compatible = "samsung,exynos5433-cmu-mif";
 287                         reg = <0x105b0000 0x2000>;
 288                         #clock-cells = <1>;
 289
 290                         clock-names = "oscclk",
 291                                 "sclk_mphy_pll";
 292                         clocks = <&xxti>,
 293                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
 294                 };
 295
 296                 cmu_peric: clock-controller@14c80000 {
 297                         compatible = "samsung,exynos5433-cmu-peric";
 298                         reg = <0x14c80000 0x1000>;
 299                         #clock-cells = <1>;
 300                 };
 301
 302                 cmu_peris: clock-controller@10040000 {
 303                         compatible = "samsung,exynos5433-cmu-peris";
 304                         reg = <0x10040000 0x1000>;
 305                         #clock-cells = <1>;
 306                 };
 307
 308                 cmu_fsys: clock-controller@156e0000 {
 309                         compatible = "samsung,exynos5433-cmu-fsys";
 310                         reg = <0x156e0000 0x1000>;
 311                         #clock-cells = <1>;
 312
 313                         clock-names = "oscclk",
 314                                 "sclk_ufs_mphy",
 315                                 "aclk_fsys_200",
 316                                 "sclk_pcie_100_fsys",
 317                                 "sclk_ufsunipro_fsys",
 318                                 "sclk_mmc2_fsys",
 319                                 "sclk_mmc1_fsys",
 320                                 "sclk_mmc0_fsys",
 321                                 "sclk_usbhost30_fsys",
 322                                 "sclk_usbdrd30_fsys";
 323                         clocks = <&xxti>,
 324                                 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
 325                                 <&cmu_top CLK_ACLK_FSYS_200>,
 326                                 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
 327                                 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
 328                                 <&cmu_top CLK_SCLK_MMC2_FSYS>,
 329                                 <&cmu_top CLK_SCLK_MMC1_FSYS>,
 330                                 <&cmu_top CLK_SCLK_MMC0_FSYS>,
 331                                 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
 332                                 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
 333                 };
 334
 335                 cmu_g2d: clock-controller@12460000 {
 336                         compatible = "samsung,exynos5433-cmu-g2d";
 337                         reg = <0x12460000 0x1000>;
 338                         #clock-cells = <1>;
 339
 340                         clock-names = "oscclk",
 341                                 "aclk_g2d_266",
 342                                 "aclk_g2d_400";
 343                         clocks = <&xxti>,
 344                                 <&cmu_top CLK_ACLK_G2D_266>,
 345                                 <&cmu_top CLK_ACLK_G2D_400>;
 346                 };
 347
 348                 cmu_disp: clock-controller@13b90000 {
 349                         compatible = "samsung,exynos5433-cmu-disp";
 350                         reg = <0x13b90000 0x1000>;
 351                         #clock-cells = <1>;
 352
 353                         clock-names = "oscclk",
 354                                 "sclk_dsim1_disp",
 355                                 "sclk_dsim0_disp",
 356                                 "sclk_dsd_disp",
 357                                 "sclk_decon_tv_eclk_disp",
 358                                 "sclk_decon_vclk_disp",
 359                                 "sclk_decon_eclk_disp",
 360                                 "sclk_decon_tv_vclk_disp",
 361                                 "aclk_disp_333";
 362                         clocks = <&xxti>,
 363                                 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
 364                                 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
 365                                 <&cmu_mif CLK_SCLK_DSD_DISP>,
 366                                 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
 367                                 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
 368                                 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 369                                 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 370                                 <&cmu_mif CLK_ACLK_DISP_333>;
 371                 };
 372
 373                 cmu_aud: clock-controller@114c0000 {
 374                         compatible = "samsung,exynos5433-cmu-aud";
 375                         reg = <0x114c0000 0x1000>;
 376                         #clock-cells = <1>;
 377                         clock-names = "oscclk", "fout_aud_pll";
 378                         clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
 379                 };
 380
 381                 cmu_bus0: clock-controller@13600000 {
 382                         compatible = "samsung,exynos5433-cmu-bus0";
 383                         reg = <0x13600000 0x1000>;
 384                         #clock-cells = <1>;
 385
 386                         clock-names = "aclk_bus0_400";
 387                         clocks = <&cmu_top CLK_ACLK_BUS0_400>;
 388                 };
 389
 390                 cmu_bus1: clock-controller@14800000 {
 391                         compatible = "samsung,exynos5433-cmu-bus1";
 392                         reg = <0x14800000 0x1000>;
 393                         #clock-cells = <1>;
 394
 395                         clock-names = "aclk_bus1_400";
 396                         clocks = <&cmu_top CLK_ACLK_BUS1_400>;
 397                 };
 398
 399                 cmu_bus2: clock-controller@13400000 {
 400                         compatible = "samsung,exynos5433-cmu-bus2";
 401                         reg = <0x13400000 0x1000>;
 402                         #clock-cells = <1>;
 403
 404                         clock-names = "oscclk", "aclk_bus2_400";
 405                         clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
 406                 };
 407
 408                 cmu_g3d: clock-controller@14aa0000 {
 409                         compatible = "samsung,exynos5433-cmu-g3d";
 410                         reg = <0x14aa0000 0x2000>;
 411                         #clock-cells = <1>;
 412
 413                         clock-names = "oscclk", "aclk_g3d_400";
 414                         clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
 415                 };
 416
 417                 cmu_gscl: clock-controller@13cf0000 {
 418                         compatible = "samsung,exynos5433-cmu-gscl";
 419                         reg = <0x13cf0000 0x1000>;
 420                         #clock-cells = <1>;
 421
 422                         clock-names = "oscclk",
 423                                 "aclk_gscl_111",
 424                                 "aclk_gscl_333";
 425                         clocks = <&xxti>,
 426                                 <&cmu_top CLK_ACLK_GSCL_111>,
 427                                 <&cmu_top CLK_ACLK_GSCL_333>;
 428                 };
 429
 430                 cmu_apollo: clock-controller@11900000 {
 431                         compatible = "samsung,exynos5433-cmu-apollo";
 432                         reg = <0x11900000 0x2000>;
 433                         #clock-cells = <1>;
 434
 435                         clock-names = "oscclk", "sclk_bus_pll_apollo";
 436                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
 437                 };
 438
 439                 cmu_atlas: clock-controller@11800000 {
 440                         compatible = "samsung,exynos5433-cmu-atlas";
 441                         reg = <0x11800000 0x2000>;
 442                         #clock-cells = <1>;
 443
 444                         clock-names = "oscclk", "sclk_bus_pll_atlas";
 445                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
 446                 };
 447
 448                 cmu_mscl: clock-controller@105d0000 {
 449                         compatible = "samsung,exynos5433-cmu-mscl";
 450                         reg = <0x150d0000 0x1000>;
 451                         #clock-cells = <1>;
 452
 453                         clock-names = "oscclk",
 454                                 "sclk_jpeg_mscl",
 455                                 "aclk_mscl_400";
 456                         clocks = <&xxti>,
 457                                 <&cmu_top CLK_SCLK_JPEG_MSCL>,
 458                                 <&cmu_top CLK_ACLK_MSCL_400>;
 459                 };
 460
 461                 cmu_mfc: clock-controller@15280000 {
 462                         compatible = "samsung,exynos5433-cmu-mfc";
 463                         reg = <0x15280000 0x1000>;
 464                         #clock-cells = <1>;
 465
 466                         clock-names = "oscclk", "aclk_mfc_400";
 467                         clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
 468                 };
 469
 470                 cmu_hevc: clock-controller@14f80000 {
 471                         compatible = "samsung,exynos5433-cmu-hevc";
 472                         reg = <0x14f80000 0x1000>;
 473                         #clock-cells = <1>;
 474
 475                         clock-names = "oscclk", "aclk_hevc_400";
 476                         clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
 477                 };
 478
 479                 cmu_isp: clock-controller@146d0000 {
 480                         compatible = "samsung,exynos5433-cmu-isp";
 481                         reg = <0x146d0000 0x1000>;
 482                         #clock-cells = <1>;
 483
 484                         clock-names = "oscclk",
 485                                 "aclk_isp_dis_400",
 486                                 "aclk_isp_400";
 487                         clocks = <&xxti>,
 488                                 <&cmu_top CLK_ACLK_ISP_DIS_400>,
 489                                 <&cmu_top CLK_ACLK_ISP_400>;
 490                 };
 491
 492                 cmu_cam0: clock-controller@120d0000 {
 493                         compatible = "samsung,exynos5433-cmu-cam0";
 494                         reg = <0x120d0000 0x1000>;
 495                         #clock-cells = <1>;
 496
 497                         clock-names = "oscclk",
 498                                 "aclk_cam0_333",
 499                                 "aclk_cam0_400",
 500                                 "aclk_cam0_552";
 501                         clocks = <&xxti>,
 502                                 <&cmu_top CLK_ACLK_CAM0_333>,
 503                                 <&cmu_top CLK_ACLK_CAM0_400>,
 504                                 <&cmu_top CLK_ACLK_CAM0_552>;
 505                 };
 506
 507                 cmu_cam1: clock-controller@145d0000 {
 508                         compatible = "samsung,exynos5433-cmu-cam1";
 509                         reg = <0x145d0000 0x1000>;
 510                         #clock-cells = <1>;
 511
 512                         clock-names = "oscclk",
 513                                 "sclk_isp_uart_cam1",
 514                                 "sclk_isp_spi1_cam1",
 515                                 "sclk_isp_spi0_cam1",
 516                                 "aclk_cam1_333",
 517                                 "aclk_cam1_400",
 518                                 "aclk_cam1_552";
 519                         clocks = <&xxti>,
 520                                 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
 521                                 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
 522                                 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
 523                                 <&cmu_top CLK_ACLK_CAM1_333>,
 524                                 <&cmu_top CLK_ACLK_CAM1_400>,
 525                                 <&cmu_top CLK_ACLK_CAM1_552>;
 526                 };
 527
 528                 tmu_atlas0: tmu@10060000 {
 529                         compatible = "samsung,exynos5433-tmu";
 530                         reg = <0x10060000 0x200>;
 531                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 533                                 <&cmu_peris CLK_SCLK_TMU0>;
 534                         clock-names = "tmu_apbif", "tmu_sclk";
 535                         #include "exynos5433-tmu-sensor-conf.dtsi"
 536                         status = "disabled";
 537                 };
 538
 539                 tmu_atlas1: tmu@10068000 {
 540                         compatible = "samsung,exynos5433-tmu";
 541                         reg = <0x10068000 0x200>;
 542                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 543                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 544                                 <&cmu_peris CLK_SCLK_TMU0>;
 545                         clock-names = "tmu_apbif", "tmu_sclk";
 546                         #include "exynos5433-tmu-sensor-conf.dtsi"
 547                         status = "disabled";
 548                 };
 549
 550                 tmu_g3d: tmu@10070000 {
 551                         compatible = "samsung,exynos5433-tmu";
 552                         reg = <0x10070000 0x200>;
 553                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 554                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 555                                 <&cmu_peris CLK_SCLK_TMU1>;
 556                         clock-names = "tmu_apbif", "tmu_sclk";
 557                         #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
 558                         status = "disabled";
 559                 };
 560
 561                 tmu_apollo: tmu@10078000 {
 562                         compatible = "samsung,exynos5433-tmu";
 563                         reg = <0x10078000 0x200>;
 564                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 565                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 566                                 <&cmu_peris CLK_SCLK_TMU1>;
 567                         clock-names = "tmu_apbif", "tmu_sclk";
 568                         #include "exynos5433-tmu-sensor-conf.dtsi"
 569                         status = "disabled";
 570                 };
 571
 572                 tmu_isp: tmu@1007c000 {
 573                         compatible = "samsung,exynos5433-tmu";
 574                         reg = <0x1007c000 0x200>;
 575                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 577                                 <&cmu_peris CLK_SCLK_TMU1>;
 578                         clock-names = "tmu_apbif", "tmu_sclk";
 579                         #include "exynos5433-tmu-sensor-conf.dtsi"
 580                         status = "disabled";
 581                 };
 582
 583                 mct@101c0000 {
 584                         compatible = "samsung,exynos4210-mct";
 585                         reg = <0x101c0000 0x800>;
 586                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 587                                 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 588                                 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 589                                 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 590                                 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 591                                 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 592                                 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 593                                 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 594                                 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 595                                 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 596                                 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 597                                 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
 599                         clock-names = "fin_pll", "mct";
 600                 };
 601
 602                 ppmu_d0_cpu: ppmu@10480000 {
 603                         compatible = "samsung,exynos-ppmu-v2";
 604                         reg = <0x10480000 0x2000>;
 605                         status = "disabled";
 606                 };
 607
 608                 ppmu_d0_general: ppmu@10490000 {
 609                         compatible = "samsung,exynos-ppmu-v2";
 610                         reg = <0x10490000 0x2000>;
 611                         status = "disabled";
 612                 };
 613
 614                 ppmu_d1_cpu: ppmu@104b0000 {
 615                         compatible = "samsung,exynos-ppmu-v2";
 616                         reg = <0x104b0000 0x2000>;
 617                         status = "disabled";
 618                 };
 619
 620                 ppmu_d1_general: ppmu@104c0000 {
 621                         compatible = "samsung,exynos-ppmu-v2";
 622                         reg = <0x104c0000 0x2000>;
 623                         status = "disabled";
 624                 };
 625
 626                 pinctrl_alive: pinctrl@10580000 {
 627                         compatible = "samsung,exynos5433-pinctrl";
 628                         reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
 629
 630                         wakeup-interrupt-controller {
 631                                 compatible = "samsung,exynos7-wakeup-eint";
 632                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 633                         };
 634                 };
 635
 636                 pinctrl_aud: pinctrl@114b0000 {
 637                         compatible = "samsung,exynos5433-pinctrl";
 638                         reg = <0x114b0000 0x1000>;
 639                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 640                 };
 641
 642                 pinctrl_cpif: pinctrl@10fe0000 {
 643                         compatible = "samsung,exynos5433-pinctrl";
 644                         reg = <0x10fe0000 0x1000>;
 645                         interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 646                 };
 647
 648                 pinctrl_ese: pinctrl@14ca0000 {
 649                         compatible = "samsung,exynos5433-pinctrl";
 650                         reg = <0x14ca0000 0x1000>;
 651                         interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
 652                 };
 653
 654                 pinctrl_finger: pinctrl@14cb0000 {
 655                         compatible = "samsung,exynos5433-pinctrl";
 656                         reg = <0x14cb0000 0x1000>;
 657                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
 658                 };
 659
 660                 pinctrl_fsys: pinctrl@15690000 {
 661                         compatible = "samsung,exynos5433-pinctrl";
 662                         reg = <0x15690000 0x1000>;
 663                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 664                 };
 665
 666                 pinctrl_imem: pinctrl@11090000 {
 667                         compatible = "samsung,exynos5433-pinctrl";
 668                         reg = <0x11090000 0x1000>;
 669                         interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
 670                 };
 671
 672                 pinctrl_nfc: pinctrl@14cd0000 {
 673                         compatible = "samsung,exynos5433-pinctrl";
 674                         reg = <0x14cd0000 0x1000>;
 675                         interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 676                 };
 677
 678                 pinctrl_peric: pinctrl@14cc0000 {
 679                         compatible = "samsung,exynos5433-pinctrl";
 680                         reg = <0x14cc0000 0x1100>;
 681                         interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 682                 };
 683
 684                 pinctrl_touch: pinctrl@14ce0000 {
 685                         compatible = "samsung,exynos5433-pinctrl";
 686                         reg = <0x14ce0000 0x1100>;
 687                         interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 688                 };
 689
 690                 pmu_system_controller: system-controller@105c0000 {
 691                         compatible = "samsung,exynos5433-pmu", "syscon";
 692                         reg = <0x105c0000 0x5008>;
 693                         #clock-cells = <1>;
 694                         clock-names = "clkout16";
 695                         clocks = <&xxti>;
 696                 };
 697
 698                 gic: interrupt-controller@11001000 {
 699                         compatible = "arm,gic-400";
 700                         #interrupt-cells = <3>;
 701                         interrupt-controller;
 702                         reg = <0x11001000 0x1000>,
 703                                 <0x11002000 0x2000>,
 704                                 <0x11004000 0x2000>,
 705                                 <0x11006000 0x2000>;
 706                         interrupts = <GIC_PPI 9 0xf04>;
 707                 };
 708
 709                 mipi_phy: video-phy {
 710                         compatible = "samsung,exynos5433-mipi-video-phy";
 711                         #phy-cells = <1>;
 712                         samsung,pmu-syscon = <&pmu_system_controller>;
 713                         samsung,cam0-sysreg = <&syscon_cam0>;
 714                         samsung,cam1-sysreg = <&syscon_cam1>;
 715                         samsung,disp-sysreg = <&syscon_disp>;
 716                 };
 717
 718                 decon: decon@13800000 {
 719                         compatible = "samsung,exynos5433-decon";
 720                         reg = <0x13800000 0x2104>;
 721                         clocks = <&cmu_disp CLK_PCLK_DECON>,
 722                                 <&cmu_disp CLK_ACLK_DECON>,
 723                                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
 724                                 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
 725                                 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 726                                 <&cmu_disp CLK_SCLK_DECON_VCLK>,
 727                                 <&cmu_disp CLK_SCLK_DECON_ECLK>;
 728                         clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 729                                 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 730                                 "sclk_decon_vclk", "sclk_decon_eclk";
 731                         interrupt-names = "fifo", "vsync", "lcd_sys";
 732                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 733                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 734                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 735                         samsung,disp-sysreg = <&syscon_disp>;
 736                         status = "disabled";
 737                         iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
 738                         iommu-names = "m0", "m1";
 739
 740                         ports {
 741                                 #address-cells = <1>;
 742                                 #size-cells = <0>;
 743
 744                                 port@0 {
 745                                         reg = <0>;
 746                                         decon_to_mic: endpoint {
 747                                                 remote-endpoint =
 748                                                         <&mic_to_decon>;
 749                                         };
 750                                 };
 751                         };
 752                 };
 753
 754                 decon_tv: decon@13880000 {
 755                         compatible = "samsung,exynos5433-decon-tv";
 756                         reg = <0x13880000 0x20b8>;
 757                         clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
 758                                  <&cmu_disp CLK_ACLK_DECON_TV>,
 759                                  <&cmu_disp CLK_ACLK_SMMU_TV0X>,
 760                                  <&cmu_disp CLK_ACLK_XIU_TV0X>,
 761                                  <&cmu_disp CLK_PCLK_SMMU_TV0X>,
 762                                  <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
 763                                  <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
 764                         clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 765                                       "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 766                                       "sclk_decon_vclk", "sclk_decon_eclk";
 767                         samsung,disp-sysreg = <&syscon_disp>;
 768                         interrupt-names = "fifo", "vsync", "lcd_sys";
 769                         interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 770                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 771                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 772                         status = "disabled";
 773                         iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
 774                         iommu-names = "m0", "m1";
 775                 };
 776
 777                 dsi: dsi@13900000 {
 778                         compatible = "samsung,exynos5433-mipi-dsi";
 779                         reg = <0x13900000 0xC0>;
 780                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 781                         phys = <&mipi_phy 1>;
 782                         phy-names = "dsim";
 783                         clocks = <&cmu_disp CLK_PCLK_DSIM0>,
 784                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
 785                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
 786                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
 787                                 <&cmu_disp CLK_SCLK_DSIM0>;
 788                         clock-names = "bus_clk",
 789                                         "phyclk_mipidphy0_bitclkdiv8",
 790                                         "phyclk_mipidphy0_rxclkesc0",
 791                                         "sclk_rgb_vclk_to_dsim0",
 792                                         "sclk_mipi";
 793                         status = "disabled";
 794                         #address-cells = <1>;
 795                         #size-cells = <0>;
 796
 797                         ports {
 798                                 #address-cells = <1>;
 799                                 #size-cells = <0>;
 800
 801                                 port@0 {
 802                                         reg = <0>;
 803                                         dsi_to_mic: endpoint {
 804                                                 remote-endpoint = <&mic_to_dsi>;
 805                                         };
 806                                 };
 807                         };
 808                 };
 809
 810                 mic: mic@13930000 {
 811                         compatible = "samsung,exynos5433-mic";
 812                         reg = <0x13930000 0x48>;
 813                         clocks = <&cmu_disp CLK_PCLK_MIC0>,
 814                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
 815                         clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
 816                         samsung,disp-syscon = <&syscon_disp>;
 817                         status = "disabled";
 818
 819                         ports {
 820                                 #address-cells = <1>;
 821                                 #size-cells = <0>;
 822
 823                                 port@0 {
 824                                         reg = <0>;
 825                                         mic_to_decon: endpoint {
 826                                                 remote-endpoint =
 827                                                         <&decon_to_mic>;
 828                                         };
 829                                 };
 830
 831                                 port@1 {
 832                                         reg = <1>;
 833                                         mic_to_dsi: endpoint {
 834                                                 remote-endpoint = <&dsi_to_mic>;
 835                                         };
 836                                 };
 837                         };
 838                 };
 839
 840                 hdmi: hdmi@13970000 {
 841                         compatible = "samsung,exynos5433-hdmi";
 842                         reg = <0x13970000 0x70000>;
 843                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 844                         clocks = <&cmu_disp CLK_PCLK_HDMI>,
 845                                 <&cmu_disp CLK_PCLK_HDMIPHY>,
 846                                 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
 847                                 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
 848                                 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
 849                                 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
 850                                 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
 851                                 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
 852                                 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
 853                         clock-names = "hdmi_pclk", "hdmi_i_pclk",
 854                                 "i_tmds_clk", "i_pixel_clk",
 855                                 "tmds_clko", "tmds_clko_user",
 856                                 "pixel_clko", "pixel_clko_user",
 857                                 "oscclk", "i_spdif_clk";
 858                         phy = <&hdmiphy>;
 859                         ddc = <&hsi2c_11>;
 860                         samsung,syscon-phandle = <&pmu_system_controller>;
 861                         samsung,sysreg-phandle = <&syscon_disp>;
 862                         status = "disabled";
 863                 };
 864
 865                 hdmiphy: hdmiphy@13af0000 {
 866                         reg = <0x13af0000 0x80>;
 867                 };
 868
 869                 syscon_disp: syscon@13b80000 {
 870                         compatible = "syscon";
 871                         reg = <0x13b80000 0x1010>;
 872                 };
 873
 874                 syscon_cam0: syscon@120f0000 {
 875                         compatible = "syscon";
 876                         reg = <0x120f0000 0x1020>;
 877                 };
 878
 879                 syscon_cam1: syscon@145f0000 {
 880                         compatible = "syscon";
 881                         reg = <0x145f0000 0x1038>;
 882                 };
 883
 884                 gsc_0: video-scaler@13C00000 {
 885                         compatible = "samsung,exynos5433-gsc";
 886                         reg = <0x13c00000 0x1000>;
 887                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
 888                         clock-names = "pclk", "aclk", "aclk_xiu",
 889                                       "aclk_gsclbend";
 890                         clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
 891                                  <&cmu_gscl CLK_ACLK_GSCL0>,
 892                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 893                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 894                         iommus = <&sysmmu_gscl0>;
 895                 };
 896
 897                 gsc_1: video-scaler@13C10000 {
 898                         compatible = "samsung,exynos5433-gsc";
 899                         reg = <0x13c10000 0x1000>;
 900                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
 901                         clock-names = "pclk", "aclk", "aclk_xiu",
 902                                       "aclk_gsclbend";
 903                         clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
 904                                  <&cmu_gscl CLK_ACLK_GSCL1>,
 905                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 906                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 907                         iommus = <&sysmmu_gscl1>;
 908                 };
 909
 910                 gsc_2: video-scaler@13C20000 {
 911                         compatible = "samsung,exynos5433-gsc";
 912                         reg = <0x13c20000 0x1000>;
 913                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 914                         clock-names = "pclk", "aclk", "aclk_xiu",
 915                                       "aclk_gsclbend";
 916                         clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
 917                                  <&cmu_gscl CLK_ACLK_GSCL2>,
 918                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 919                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 920                         iommus = <&sysmmu_gscl2>;
 921                 };
 922
 923                 jpeg: codec@15020000 {
 924                         compatible = "samsung,exynos5433-jpeg";
 925                         reg = <0x15020000 0x10000>;
 926                         interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
 927                         clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
 928                         clocks = <&cmu_mscl CLK_PCLK_JPEG>,
 929                                  <&cmu_mscl CLK_ACLK_JPEG>,
 930                                  <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
 931                                  <&cmu_mscl CLK_SCLK_JPEG>;
 932                         iommus = <&sysmmu_jpeg>;
 933                 };
 934
 935                 mfc: codec@152E0000 {
 936                         compatible = "samsung,exynos5433-mfc";
 937                         reg = <0x152E0000 0x10000>;
 938                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 939                         clock-names = "pclk", "aclk", "aclk_xiu";
 940                         clocks = <&cmu_mfc CLK_PCLK_MFC>,
 941                                  <&cmu_mfc CLK_ACLK_MFC>,
 942                                  <&cmu_mfc CLK_ACLK_XIU_MFCX>;
 943                         iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
 944                         iommu-names = "left", "right";
 945                 };
 946
 947                 sysmmu_decon0x: sysmmu@13a00000 {
 948                         compatible = "samsung,exynos-sysmmu";
 949                         reg = <0x13a00000 0x1000>;
 950                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 951                         clock-names = "pclk", "aclk";
 952                         clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 953                                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
 954                         #iommu-cells = <0>;
 955                 };
 956
 957                 sysmmu_decon1x: sysmmu@13a10000 {
 958                         compatible = "samsung,exynos-sysmmu";
 959                         reg = <0x13a10000 0x1000>;
 960                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 961                         clock-names = "pclk", "aclk";
 962                         clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 963                                 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
 964                         #iommu-cells = <0>;
 965                 };
 966
 967                 sysmmu_tv0x: sysmmu@13a20000 {
 968                         compatible = "samsung,exynos-sysmmu";
 969                         reg = <0x13a20000 0x1000>;
 970                         interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 971                         clock-names = "pclk", "aclk";
 972                         clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
 973                                 <&cmu_disp CLK_ACLK_SMMU_TV0X>;
 974                         #iommu-cells = <0>;
 975                 };
 976
 977                 sysmmu_tv1x: sysmmu@13a30000 {
 978                         compatible = "samsung,exynos-sysmmu";
 979                         reg = <0x13a30000 0x1000>;
 980                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 981                         clock-names = "pclk", "aclk";
 982                         clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
 983                                 <&cmu_disp CLK_ACLK_SMMU_TV1X>;
 984                         #iommu-cells = <0>;
 985                 };
 986
 987                 sysmmu_gscl0: sysmmu@13c80000 {
 988                         compatible = "samsung,exynos-sysmmu";
 989                         reg = <0x13C80000 0x1000>;
 990                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 991                         clock-names = "aclk", "pclk";
 992                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
 993                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
 994                         #iommu-cells = <0>;
 995                 };
 996
 997                 sysmmu_gscl1: sysmmu@13c90000 {
 998                         compatible = "samsung,exynos-sysmmu";
 999                         reg = <0x13C90000 0x1000>;
1000                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1001                         clock-names = "aclk", "pclk";
1002                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1003                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1004                         #iommu-cells = <0>;
1005                 };
1006
1007                 sysmmu_gscl2: sysmmu@13ca0000 {
1008                         compatible = "samsung,exynos-sysmmu";
1009                         reg = <0x13CA0000 0x1000>;
1010                         interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1011                         clock-names = "aclk", "pclk";
1012                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1013                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1014                         #iommu-cells = <0>;
1015                 };
1016
1017                 sysmmu_jpeg: sysmmu@15060000 {
1018                         compatible = "samsung,exynos-sysmmu";
1019                         reg = <0x15060000 0x1000>;
1020                         interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1021                         clock-names = "pclk", "aclk";
1022                         clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
1023                                  <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
1024                         #iommu-cells = <0>;
1025                 };
1026
1027                 sysmmu_mfc_0: sysmmu@15200000 {
1028                         compatible = "samsung,exynos-sysmmu";
1029                         reg = <0x15200000 0x1000>;
1030                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1031                         clock-names = "pclk", "aclk";
1032                         clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
1033                                  <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
1034                         #iommu-cells = <0>;
1035                 };
1036
1037                 sysmmu_mfc_1: sysmmu@15210000 {
1038                         compatible = "samsung,exynos-sysmmu";
1039                         reg = <0x15210000 0x1000>;
1040                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1041                         clock-names = "pclk", "aclk";
1042                         clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
1043                                  <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
1044                         #iommu-cells = <0>;
1045                 };
1046
1047                 serial_0: serial@14c10000 {
1048                         compatible = "samsung,exynos5433-uart";
1049                         reg = <0x14c10000 0x100>;
1050                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1051                         clocks = <&cmu_peric CLK_PCLK_UART0>,
1052                                 <&cmu_peric CLK_SCLK_UART0>;
1053                         clock-names = "uart", "clk_uart_baud0";
1054                         pinctrl-names = "default";
1055                         pinctrl-0 = <&uart0_bus>;
1056                         status = "disabled";
1057                 };
1058
1059                 serial_1: serial@14c20000 {
1060                         compatible = "samsung,exynos5433-uart";
1061                         reg = <0x14c20000 0x100>;
1062                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1063                         clocks = <&cmu_peric CLK_PCLK_UART1>,
1064                                 <&cmu_peric CLK_SCLK_UART1>;
1065                         clock-names = "uart", "clk_uart_baud0";
1066                         pinctrl-names = "default";
1067                         pinctrl-0 = <&uart1_bus>;
1068                         status = "disabled";
1069                 };
1070
1071                 serial_2: serial@14c30000 {
1072                         compatible = "samsung,exynos5433-uart";
1073                         reg = <0x14c30000 0x100>;
1074                         interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1075                         clocks = <&cmu_peric CLK_PCLK_UART2>,
1076                                 <&cmu_peric CLK_SCLK_UART2>;
1077                         clock-names = "uart", "clk_uart_baud0";
1078                         pinctrl-names = "default";
1079                         pinctrl-0 = <&uart2_bus>;
1080                         status = "disabled";
1081                 };
1082
1083                 spi_0: spi@14d20000 {
1084                         compatible = "samsung,exynos5433-spi";
1085                         reg = <0x14d20000 0x100>;
1086                         interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1087                         dmas = <&pdma0 9>, <&pdma0 8>;
1088                         dma-names = "tx", "rx";
1089                         #address-cells = <1>;
1090                         #size-cells = <0>;
1091                         clocks = <&cmu_peric CLK_PCLK_SPI0>,
1092                                 <&cmu_peric CLK_SCLK_SPI0>,
1093                                 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1094                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1095                         samsung,spi-src-clk = <0>;
1096                         pinctrl-names = "default";
1097                         pinctrl-0 = <&spi0_bus>;
1098                         num-cs = <1>;
1099                         status = "disabled";
1100                 };
1101
1102                 spi_1: spi@14d30000 {
1103                         compatible = "samsung,exynos5433-spi";
1104                         reg = <0x14d30000 0x100>;
1105                         interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1106                         dmas = <&pdma0 11>, <&pdma0 10>;
1107                         dma-names = "tx", "rx";
1108                         #address-cells = <1>;
1109                         #size-cells = <0>;
1110                         clocks = <&cmu_peric CLK_PCLK_SPI1>,
1111                                 <&cmu_peric CLK_SCLK_SPI1>,
1112                                 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1113                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1114                         samsung,spi-src-clk = <0>;
1115                         pinctrl-names = "default";
1116                         pinctrl-0 = <&spi1_bus>;
1117                         num-cs = <1>;
1118                         status = "disabled";
1119                 };
1120
1121                 spi_2: spi@14d40000 {
1122                         compatible = "samsung,exynos5433-spi";
1123                         reg = <0x14d40000 0x100>;
1124                         interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1125                         dmas = <&pdma0 13>, <&pdma0 12>;
1126                         dma-names = "tx", "rx";
1127                         #address-cells = <1>;
1128                         #size-cells = <0>;
1129                         clocks = <&cmu_peric CLK_PCLK_SPI2>,
1130                                 <&cmu_peric CLK_SCLK_SPI2>,
1131                                 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1132                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1133                         samsung,spi-src-clk = <0>;
1134                         pinctrl-names = "default";
1135                         pinctrl-0 = <&spi2_bus>;
1136                         num-cs = <1>;
1137                         status = "disabled";
1138                 };
1139
1140                 spi_3: spi@14d50000 {
1141                         compatible = "samsung,exynos5433-spi";
1142                         reg = <0x14d50000 0x100>;
1143                         interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1144                         dmas = <&pdma0 23>, <&pdma0 22>;
1145                         dma-names = "tx", "rx";
1146                         #address-cells = <1>;
1147                         #size-cells = <0>;
1148                         clocks = <&cmu_peric CLK_PCLK_SPI3>,
1149                                 <&cmu_peric CLK_SCLK_SPI3>,
1150                                 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1151                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1152                         samsung,spi-src-clk = <0>;
1153                         pinctrl-names = "default";
1154                         pinctrl-0 = <&spi3_bus>;
1155                         num-cs = <1>;
1156                         status = "disabled";
1157                 };
1158
1159                 spi_4: spi@14d00000 {
1160                         compatible = "samsung,exynos5433-spi";
1161                         reg = <0x14d00000 0x100>;
1162                         interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1163                         dmas = <&pdma0 25>, <&pdma0 24>;
1164                         dma-names = "tx", "rx";
1165                         #address-cells = <1>;
1166                         #size-cells = <0>;
1167                         clocks = <&cmu_peric CLK_PCLK_SPI4>,
1168                                 <&cmu_peric CLK_SCLK_SPI4>,
1169                                 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1170                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1171                         samsung,spi-src-clk = <0>;
1172                         pinctrl-names = "default";
1173                         pinctrl-0 = <&spi4_bus>;
1174                         num-cs = <1>;
1175                         status = "disabled";
1176                 };
1177
1178                 adc: adc@14d10000 {
1179                         compatible = "samsung,exynos7-adc";
1180                         reg = <0x14d10000 0x100>;
1181                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1182                         clock-names = "adc";
1183                         clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1184                         #io-channel-cells = <1>;
1185                         io-channel-ranges;
1186                         status = "disabled";
1187                 };
1188
1189                 pwm: pwm@14dd0000 {
1190                         compatible = "samsung,exynos4210-pwm";
1191                         reg = <0x14dd0000 0x100>;
1192                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1193                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1194                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1195                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1197                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1198                         clocks = <&cmu_peric CLK_PCLK_PWM>;
1199                         clock-names = "timers";
1200                         #pwm-cells = <3>;
1201                         status = "disabled";
1202                 };
1203
1204                 hsi2c_0: hsi2c@14e40000 {
1205                         compatible = "samsung,exynos7-hsi2c";
1206                         reg = <0x14e40000 0x1000>;
1207                         interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1208                         #address-cells = <1>;
1209                         #size-cells = <0>;
1210                         pinctrl-names = "default";
1211                         pinctrl-0 = <&hs_i2c0_bus>;
1212                         clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1213                         clock-names = "hsi2c";
1214                         status = "disabled";
1215                 };
1216
1217                 hsi2c_1: hsi2c@14e50000 {
1218                         compatible = "samsung,exynos7-hsi2c";
1219                         reg = <0x14e50000 0x1000>;
1220                         interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1221                         #address-cells = <1>;
1222                         #size-cells = <0>;
1223                         pinctrl-names = "default";
1224                         pinctrl-0 = <&hs_i2c1_bus>;
1225                         clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1226                         clock-names = "hsi2c";
1227                         status = "disabled";
1228                 };
1229
1230                 hsi2c_2: hsi2c@14e60000 {
1231                         compatible = "samsung,exynos7-hsi2c";
1232                         reg = <0x14e60000 0x1000>;
1233                         interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1234                         #address-cells = <1>;
1235                         #size-cells = <0>;
1236                         pinctrl-names = "default";
1237                         pinctrl-0 = <&hs_i2c2_bus>;
1238                         clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1239                         clock-names = "hsi2c";
1240                         status = "disabled";
1241                 };
1242
1243                 hsi2c_3: hsi2c@14e70000 {
1244                         compatible = "samsung,exynos7-hsi2c";
1245                         reg = <0x14e70000 0x1000>;
1246                         interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1247                         #address-cells = <1>;
1248                         #size-cells = <0>;
1249                         pinctrl-names = "default";
1250                         pinctrl-0 = <&hs_i2c3_bus>;
1251                         clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1252                         clock-names = "hsi2c";
1253                         status = "disabled";
1254                 };
1255
1256                 hsi2c_4: hsi2c@14ec0000 {
1257                         compatible = "samsung,exynos7-hsi2c";
1258                         reg = <0x14ec0000 0x1000>;
1259                         interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1260                         #address-cells = <1>;
1261                         #size-cells = <0>;
1262                         pinctrl-names = "default";
1263                         pinctrl-0 = <&hs_i2c4_bus>;
1264                         clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1265                         clock-names = "hsi2c";
1266                         status = "disabled";
1267                 };
1268
1269                 hsi2c_5: hsi2c@14ed0000 {
1270                         compatible = "samsung,exynos7-hsi2c";
1271                         reg = <0x14ed0000 0x1000>;
1272                         interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1273                         #address-cells = <1>;
1274                         #size-cells = <0>;
1275                         pinctrl-names = "default";
1276                         pinctrl-0 = <&hs_i2c5_bus>;
1277                         clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1278                         clock-names = "hsi2c";
1279                         status = "disabled";
1280                 };
1281
1282                 hsi2c_6: hsi2c@14ee0000 {
1283                         compatible = "samsung,exynos7-hsi2c";
1284                         reg = <0x14ee0000 0x1000>;
1285                         interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1286                         #address-cells = <1>;
1287                         #size-cells = <0>;
1288                         pinctrl-names = "default";
1289                         pinctrl-0 = <&hs_i2c6_bus>;
1290                         clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1291                         clock-names = "hsi2c";
1292                         status = "disabled";
1293                 };
1294
1295                 hsi2c_7: hsi2c@14ef0000 {
1296                         compatible = "samsung,exynos7-hsi2c";
1297                         reg = <0x14ef0000 0x1000>;
1298                         interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1299                         #address-cells = <1>;
1300                         #size-cells = <0>;
1301                         pinctrl-names = "default";
1302                         pinctrl-0 = <&hs_i2c7_bus>;
1303                         clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1304                         clock-names = "hsi2c";
1305                         status = "disabled";
1306                 };
1307
1308                 hsi2c_8: hsi2c@14d90000 {
1309                         compatible = "samsung,exynos7-hsi2c";
1310                         reg = <0x14d90000 0x1000>;
1311                         interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1312                         #address-cells = <1>;
1313                         #size-cells = <0>;
1314                         pinctrl-names = "default";
1315                         pinctrl-0 = <&hs_i2c8_bus>;
1316                         clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1317                         clock-names = "hsi2c";
1318                         status = "disabled";
1319                 };
1320
1321                 hsi2c_9: hsi2c@14da0000 {
1322                         compatible = "samsung,exynos7-hsi2c";
1323                         reg = <0x14da0000 0x1000>;
1324                         interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1325                         #address-cells = <1>;
1326                         #size-cells = <0>;
1327                         pinctrl-names = "default";
1328                         pinctrl-0 = <&hs_i2c9_bus>;
1329                         clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1330                         clock-names = "hsi2c";
1331                         status = "disabled";
1332                 };
1333
1334                 hsi2c_10: hsi2c@14de0000 {
1335                         compatible = "samsung,exynos7-hsi2c";
1336                         reg = <0x14de0000 0x1000>;
1337                         interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1338                         #address-cells = <1>;
1339                         #size-cells = <0>;
1340                         pinctrl-names = "default";
1341                         pinctrl-0 = <&hs_i2c10_bus>;
1342                         clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1343                         clock-names = "hsi2c";
1344                         status = "disabled";
1345                 };
1346
1347                 hsi2c_11: hsi2c@14df0000 {
1348                         compatible = "samsung,exynos7-hsi2c";
1349                         reg = <0x14df0000 0x1000>;
1350                         interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1351                         #address-cells = <1>;
1352                         #size-cells = <0>;
1353                         pinctrl-names = "default";
1354                         pinctrl-0 = <&hs_i2c11_bus>;
1355                         clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1356                         clock-names = "hsi2c";
1357                         status = "disabled";
1358                 };
1359
1360                 usbdrd30: usbdrd {
1361                         compatible = "samsung,exynos5250-dwusb3";
1362                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1363                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
1364                         clock-names = "usbdrd30", "usbdrd30_susp_clk";
1365                         #address-cells = <1>;
1366                         #size-cells = <1>;
1367                         ranges;
1368                         status = "disabled";
1369
1370                         dwc3@15400000 {
1371                                 compatible = "snps,dwc3";
1372                                 reg = <0x15400000 0x10000>;
1373                                 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1374                                 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1375                                 phy-names = "usb2-phy", "usb3-phy";
1376                         };
1377                 };
1378
1379                 usbdrd30_phy: phy@15500000 {
1380                         compatible = "samsung,exynos5433-usbdrd-phy";
1381                         reg = <0x15500000 0x100>;
1382                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1383                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1384                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1385                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
1386                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1387                                         "itp";
1388                         #phy-cells = <1>;
1389                         samsung,pmu-syscon = <&pmu_system_controller>;
1390                         status = "disabled";
1391                 };
1392
1393                 usbhost30_phy: phy@15580000 {
1394                         compatible = "samsung,exynos5433-usbdrd-phy";
1395                         reg = <0x15580000 0x100>;
1396                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1397                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1398                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1399                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
1400                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1401                                         "itp";
1402                         #phy-cells = <1>;
1403                         samsung,pmu-syscon = <&pmu_system_controller>;
1404                         status = "disabled";
1405                 };
1406
1407                 usbhost30: usbhost {
1408                         compatible = "samsung,exynos5250-dwusb3";
1409                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1410                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
1411                         clock-names = "usbdrd30", "usbdrd30_susp_clk";
1412                         #address-cells = <1>;
1413                         #size-cells = <1>;
1414                         ranges;
1415                         status = "disabled";
1416
1417                         usbdrd_dwc3_0: dwc3@15a00000 {
1418                                 compatible = "snps,dwc3";
1419                                 reg = <0x15a00000 0x10000>;
1420                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1421                                 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1422                                 phy-names = "usb2-phy", "usb3-phy";
1423                         };
1424                 };
1425
1426                 mshc_0: mshc@15540000 {
1427                         compatible = "samsung,exynos7-dw-mshc-smu";
1428                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1429                         #address-cells = <1>;
1430                         #size-cells = <0>;
1431                         reg = <0x15540000 0x2000>;
1432                         clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1433                                 <&cmu_fsys CLK_SCLK_MMC0>;
1434                         clock-names = "biu", "ciu";
1435                         fifo-depth = <0x40>;
1436                         status = "disabled";
1437                 };
1438
1439                 mshc_1: mshc@15550000 {
1440                         compatible = "samsung,exynos7-dw-mshc-smu";
1441                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1442                         #address-cells = <1>;
1443                         #size-cells = <0>;
1444                         reg = <0x15550000 0x2000>;
1445                         clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1446                                 <&cmu_fsys CLK_SCLK_MMC1>;
1447                         clock-names = "biu", "ciu";
1448                         fifo-depth = <0x40>;
1449                         status = "disabled";
1450                 };
1451
1452                 mshc_2: mshc@15560000 {
1453                         compatible = "samsung,exynos7-dw-mshc-smu";
1454                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1455                         #address-cells = <1>;
1456                         #size-cells = <0>;
1457                         reg = <0x15560000 0x2000>;
1458                         clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1459                                 <&cmu_fsys CLK_SCLK_MMC2>;
1460                         clock-names = "biu", "ciu";
1461                         fifo-depth = <0x40>;
1462                         status = "disabled";
1463                 };
1464
1465                 amba {
1466                         compatible = "simple-bus";
1467                         #address-cells = <1>;
1468                         #size-cells = <1>;
1469                         ranges;
1470
1471                         pdma0: pdma@15610000 {
1472                                 compatible = "arm,pl330", "arm,primecell";
1473                                 reg = <0x15610000 0x1000>;
1474                                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1475                                 clocks = <&cmu_fsys CLK_PDMA0>;
1476                                 clock-names = "apb_pclk";
1477                                 #dma-cells = <1>;
1478                                 #dma-channels = <8>;
1479                                 #dma-requests = <32>;
1480                         };
1481
1482                         pdma1: pdma@15600000 {
1483                                 compatible = "arm,pl330", "arm,primecell";
1484                                 reg = <0x15600000 0x1000>;
1485                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1486                                 clocks = <&cmu_fsys CLK_PDMA1>;
1487                                 clock-names = "apb_pclk";
1488                                 #dma-cells = <1>;
1489                                 #dma-channels = <8>;
1490                                 #dma-requests = <32>;
1491                         };
1492                 };
1493
1494                 audio-subsystem@11400000 {
1495                         compatible = "samsung,exynos5433-lpass";
1496                         reg = <0x11400000 0x100>, <0x11500000 0x08>;
1497                         clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1498                         clock-names = "sfr0_ctrl";
1499                         samsung,pmu-syscon = <&pmu_system_controller>;
1500                         #address-cells = <1>;
1501                         #size-cells = <1>;
1502                         ranges;
1503
1504                         adma: adma@11420000 {
1505                                 compatible = "arm,pl330", "arm,primecell";
1506                                 reg = <0x11420000 0x1000>;
1507                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1508                                 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1509                                 clock-names = "apb_pclk";
1510                                 #dma-cells = <1>;
1511                                 #dma-channels = <8>;
1512                                 #dma-requests = <32>;
1513                         };
1514
1515                         i2s0: i2s0@11440000 {
1516                                 compatible = "samsung,exynos7-i2s";
1517                                 reg = <0x11440000 0x100>;
1518                                 dmas = <&adma 0 &adma 2>;
1519                                 dma-names = "tx", "rx";
1520                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1521                                 #address-cells = <1>;
1522                                 #size-cells = <0>;
1523                                 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1524                                         <&cmu_aud CLK_SCLK_AUD_I2S>,
1525                                         <&cmu_aud CLK_SCLK_I2S_BCLK>;
1526                                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1527                                 pinctrl-names = "default";
1528                                 pinctrl-0 = <&i2s0_bus>;
1529                                 status = "disabled";
1530                         };
1531
1532                         serial_3: serial@11460000 {
1533                                 compatible = "samsung,exynos5433-uart";
1534                                 reg = <0x11460000 0x100>;
1535                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1536                                 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1537                                         <&cmu_aud CLK_SCLK_AUD_UART>;
1538                                 clock-names = "uart", "clk_uart_baud0";
1539                                 pinctrl-names = "default";
1540                                 pinctrl-0 = <&uart_aud_bus>;
1541                                 status = "disabled";
1542                         };
1543                 };
1544         };
1545
1546         timer: timer {
1547                 compatible = "arm,armv8-timer";
1548                 interrupts = <GIC_PPI 13
1549                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1550                         <GIC_PPI 14
1551                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1552                         <GIC_PPI 11
1553                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1554                         <GIC_PPI 10
1555                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1556         };
1557 };
1558
1559 #include "exynos5433-bus.dtsi"
1560 #include "exynos5433-pinctrl.dtsi"
1561 #include "exynos5433-tmu.dtsi"