2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 * Copyright (C) 2016 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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47 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 model = "Marvell Armada 37xx SoC";
51 compatible = "marvell,armada3700";
52 interrupt-parent = <&gic>;
65 compatible = "arm,cortex-a53", "arm,armv8";
67 enable-method = "psci";
72 compatible = "arm,psci-0.2";
77 compatible = "arm,armv8-timer";
78 interrupts = <GIC_PPI 13
79 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
89 compatible = "simple-bus";
94 internal-regs@d0000000 {
97 compatible = "simple-bus";
98 /* 32M internal register @ 0xd000_0000 */
99 ranges = <0x0 0x0 0xd0000000 0x2000000>;
102 compatible = "marvell,armada-3700-spi";
103 #address-cells = <1>;
105 reg = <0x10600 0xA00>;
106 clocks = <&nb_periph_clk 7>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
113 compatible = "marvell,armada-3700-i2c";
114 reg = <0x11000 0x24>;
115 #address-cells = <1>;
117 clocks = <&nb_periph_clk 10>;
118 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
124 compatible = "marvell,armada-3700-i2c";
125 reg = <0x11080 0x24>;
126 #address-cells = <1>;
128 clocks = <&nb_periph_clk 9>;
129 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
134 uart0: serial@12000 {
135 compatible = "marvell,armada-3700-uart";
136 reg = <0x12000 0x400>;
137 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
141 nb_periph_clk: nb-periph-clk@13000 {
142 compatible = "marvell,armada-3700-periph-clock-nb";
143 reg = <0x13000 0x100>;
144 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
145 <&tbg 3>, <&xtalclk>;
149 sb_periph_clk: sb-periph-clk@18000 {
150 compatible = "marvell,armada-3700-periph-clock-sb";
151 reg = <0x18000 0x100>;
152 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
153 <&tbg 3>, <&xtalclk>;
158 compatible = "marvell,armada-3700-tbg-clock";
159 reg = <0x13200 0x100>;
164 pinctrl_nb: pinctrl@13800 {
165 compatible = "marvell,armada3710-nb-pinctrl",
166 "syscon", "simple-mfd";
167 reg = <0x13800 0x100>, <0x13C00 0x20>;
170 gpio-ranges = <&pinctrl_nb 0 0 36>;
173 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
189 compatible = "marvell,armada-3700-xtal-clock";
190 clock-output-names = "xtal";
194 spi_quad_pins: spi-quad-pins {
199 i2c1_pins: i2c1-pins {
204 i2c2_pins: i2c2-pins {
209 uart1_pins: uart1-pins {
214 uart2_pins: uart2-pins {
220 pinctrl_sb: pinctrl@18800 {
221 compatible = "marvell,armada3710-sb-pinctrl",
222 "syscon", "simple-mfd";
223 reg = <0x18800 0x100>, <0x18C00 0x20>;
226 gpio-ranges = <&pinctrl_sb 0 0 29>;
229 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
236 rgmii_pins: mii-pins {
243 eth0: ethernet@30000 {
244 compatible = "marvell,armada-3700-neta";
245 reg = <0x30000 0x4000>;
246 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&sb_periph_clk 8>;
252 #address-cells = <1>;
254 compatible = "marvell,orion-mdio";
258 eth1: ethernet@40000 {
259 compatible = "marvell,armada-3700-neta";
260 reg = <0x40000 0x4000>;
261 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&sb_periph_clk 7>;
267 compatible = "marvell,armada3700-xhci",
269 reg = <0x58000 0x4000>;
270 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&sb_periph_clk 12>;
276 compatible = "marvell,armada-3700-ehci";
277 reg = <0x5e000 0x2000>;
278 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
283 compatible = "marvell,armada-3700-xor";
288 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
291 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
295 sdhci0: sdhci@d8000 {
296 compatible = "marvell,armada-3700-sdhci",
297 "marvell,sdhci-xenon";
300 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&nb_periph_clk 0>;
302 clock-names = "core";
307 compatible = "marvell,armada-3700-ahci";
308 reg = <0xe0000 0x2000>;
309 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
313 gic: interrupt-controller@1d00000 {
314 compatible = "arm,gic-v3";
315 #interrupt-cells = <3>;
316 interrupt-controller;
317 reg = <0x1d00000 0x10000>, /* GICD */
318 <0x1d40000 0x40000>; /* GICR */
322 pcie0: pcie@d0070000 {
323 compatible = "marvell,armada-3700-pcie";
326 reg = <0 0xd0070000 0 0x20000>;
327 #address-cells = <3>;
329 bus-range = <0x00 0xff>;
330 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
331 #interrupt-cells = <1>;
332 msi-parent = <&pcie0>;
334 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
335 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
336 interrupt-map-mask = <0 0 0 7>;
337 interrupt-map = <0 0 0 1 &pcie_intc 0>,
338 <0 0 0 2 &pcie_intc 1>,
339 <0 0 0 3 &pcie_intc 2>,
340 <0 0 0 4 &pcie_intc 3>;
341 pcie_intc: interrupt-controller {
342 interrupt-controller;
343 #interrupt-cells = <1>;