2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
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14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
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22 * obtaining a copy of this software and associated documentation
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44 * Device Tree file for Marvell Armada CP110 Slave.
51 compatible = "simple-bus";
52 interrupt-parent = <&gic>;
55 config-space@f4000000 {
58 compatible = "simple-bus";
59 interrupt-parent = <&gic>;
60 ranges = <0x0 0x0 0xf4000000 0x2000000>;
62 cps_syscon0: system-controller@440000 {
63 compatible = "marvell,cp110-system-controller0",
65 reg = <0x440000 0x1000>;
67 core-clock-output-names =
68 "cps-apll", "cps-ppv2-core", "cps-eip",
69 "cps-core", "cps-nand-core";
70 gate-clock-output-names =
71 "cps-audio", "cps-communit", "cps-nand",
72 "cps-ppv2", "cps-sdio", "cps-mg-domain",
73 "cps-mg-core", "cps-xor1", "cps-xor0",
74 "cps-gop-dp", "none", "cps-pcie_x10",
75 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
76 "cps-sata", "cps-sata-usb", "cps-main",
77 "cps-sd-mmc", "none", "none",
78 "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
79 "cps-usb3dev", "cps-eip150", "cps-eip197";
82 cps_sata0: sata@540000 {
83 compatible = "marvell,armada-8k-ahci",
85 reg = <0x540000 0x30000>;
86 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
87 clocks = <&cps_syscon0 1 15>;
91 cps_usb3_0: usb3@500000 {
92 compatible = "marvell,armada-8k-xhci",
94 reg = <0x500000 0x4000>;
96 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&cps_syscon0 1 22>;
101 cps_usb3_1: usb3@510000 {
102 compatible = "marvell,armada-8k-xhci",
104 reg = <0x510000 0x4000>;
106 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&cps_syscon0 1 23>;
111 cps_xor0: xor@6a0000 {
112 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
113 reg = <0x6a0000 0x1000>,
116 msi-parent = <&gic_v2m0>;
117 clocks = <&cps_syscon0 1 8>;
120 cps_xor1: xor@6c0000 {
121 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
122 reg = <0x6c0000 0x1000>,
125 msi-parent = <&gic_v2m0>;
126 clocks = <&cps_syscon0 1 7>;
129 cps_spi0: spi@700600 {
130 compatible = "marvell,armada-380-spi";
131 reg = <0x700600 0x50>;
132 #address-cells = <0x1>;
135 clocks = <&cps_syscon0 1 21>;
139 cps_spi1: spi@700680 {
140 compatible = "marvell,armada-380-spi";
141 reg = <0x700680 0x50>;
142 #address-cells = <1>;
145 clocks = <&cps_syscon0 1 21>;
149 cps_i2c0: i2c@701000 {
150 compatible = "marvell,mv78230-i2c";
151 reg = <0x701000 0x20>;
152 #address-cells = <1>;
154 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&cps_syscon0 1 21>;
159 cps_i2c1: i2c@701100 {
160 compatible = "marvell,mv78230-i2c";
161 reg = <0x701100 0x20>;
162 #address-cells = <1>;
164 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&cps_syscon0 1 21>;
169 cps_trng: trng@760000 {
170 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
171 reg = <0x760000 0x7d>;
172 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cps_syscon0 1 25>;
178 cps_pcie0: pcie@f4600000 {
179 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
180 reg = <0 0xf4600000 0 0x10000>,
181 <0 0xfaf00000 0 0x80000>;
182 reg-names = "ctrl", "config";
183 #address-cells = <3>;
185 #interrupt-cells = <1>;
188 msi-parent = <&gic_v2m0>;
190 bus-range = <0 0xff>;
193 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
194 /* non-prefetchable memory */
195 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
198 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cps_syscon0 1 13>;
204 cps_pcie1: pcie@f4620000 {
205 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
206 reg = <0 0xf4620000 0 0x10000>,
207 <0 0xfbf00000 0 0x80000>;
208 reg-names = "ctrl", "config";
209 #address-cells = <3>;
211 #interrupt-cells = <1>;
214 msi-parent = <&gic_v2m0>;
216 bus-range = <0 0xff>;
219 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
220 /* non-prefetchable memory */
221 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
222 interrupt-map-mask = <0 0 0 0>;
223 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
224 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cps_syscon0 1 11>;
231 cps_pcie2: pcie@f4640000 {
232 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
233 reg = <0 0xf4640000 0 0x10000>,
234 <0 0xfcf00000 0 0x80000>;
235 reg-names = "ctrl", "config";
236 #address-cells = <3>;
238 #interrupt-cells = <1>;
241 msi-parent = <&gic_v2m0>;
243 bus-range = <0 0xff>;
246 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
247 /* non-prefetchable memory */
248 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
249 interrupt-map-mask = <0 0 0 0>;
250 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
251 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cps_syscon0 1 12>;