arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/power/mt8173-power.h>
  18 #include <dt-bindings/reset-controller/mt8173-resets.h>
  19 #include "mt8173-pinfunc.h"
  20
  21 / {
  22         compatible = "mediatek,mt8173";
  23         interrupt-parent = <&sysirq>;
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu-map {
  32                         cluster0 {
  33                                 core0 {
  34                                         cpu = <&cpu0>;
  35                                 };
  36                                 core1 {
  37                                         cpu = <&cpu1>;
  38                                 };
  39                         };
  40
  41                         cluster1 {
  42                                 core0 {
  43                                         cpu = <&cpu2>;
  44                                 };
  45                                 core1 {
  46                                         cpu = <&cpu3>;
  47                                 };
  48                         };
  49                 };
  50
  51                 cpu0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x000>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                 };
  58
  59                 cpu1: cpu@1 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a53";
  62                         reg = <0x001>;
  63                         enable-method = "psci";
  64                         cpu-idle-states = <&CPU_SLEEP_0>;
  65                 };
  66
  67                 cpu2: cpu@100 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a57";
  70                         reg = <0x100>;
  71                         enable-method = "psci";
  72                         cpu-idle-states = <&CPU_SLEEP_0>;
  73                 };
  74
  75                 cpu3: cpu@101 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a57";
  78                         reg = <0x101>;
  79                         enable-method = "psci";
  80                         cpu-idle-states = <&CPU_SLEEP_0>;
  81                 };
  82
  83                 idle-states {
  84                         entry-method = "arm,psci";
  85
  86                         CPU_SLEEP_0: cpu-sleep-0 {
  87                                 compatible = "arm,idle-state";
  88                                 local-timer-stop;
  89                                 entry-latency-us = <639>;
  90                                 exit-latency-us = <680>;
  91                                 min-residency-us = <1088>;
  92                                 arm,psci-suspend-param = <0x0010000>;
  93                         };
  94                 };
  95         };
  96
  97         psci {
  98                 compatible = "arm,psci";
  99                 method = "smc";
 100                 cpu_suspend   = <0x84000001>;
 101                 cpu_off       = <0x84000002>;
 102                 cpu_on        = <0x84000003>;
 103         };
 104
 105         clk26m: oscillator@0 {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <26000000>;
 109                 clock-output-names = "clk26m";
 110         };
 111
 112         clk32k: oscillator@1 {
 113                 compatible = "fixed-clock";
 114                 #clock-cells = <0>;
 115                 clock-frequency = <32000>;
 116                 clock-output-names = "clk32k";
 117         };
 118
 119         cpum_ck: oscillator@2 {
 120                 compatible = "fixed-clock";
 121                 #clock-cells = <0>;
 122                 clock-frequency = <0>;
 123                 clock-output-names = "cpum_ck";
 124         };
 125
 126         timer {
 127                 compatible = "arm,armv8-timer";
 128                 interrupt-parent = <&gic>;
 129                 interrupts = <GIC_PPI 13
 130                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 131                              <GIC_PPI 14
 132                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 133                              <GIC_PPI 11
 134                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 135                              <GIC_PPI 10
 136                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 137         };
 138
 139         soc {
 140                 #address-cells = <2>;
 141                 #size-cells = <2>;
 142                 compatible = "simple-bus";
 143                 ranges;
 144
 145                 topckgen: clock-controller@10000000 {
 146                         compatible = "mediatek,mt8173-topckgen";
 147                         reg = <0 0x10000000 0 0x1000>;
 148                         #clock-cells = <1>;
 149                 };
 150
 151                 infracfg: power-controller@10001000 {
 152                         compatible = "mediatek,mt8173-infracfg", "syscon";
 153                         reg = <0 0x10001000 0 0x1000>;
 154                         #clock-cells = <1>;
 155                         #reset-cells = <1>;
 156                 };
 157
 158                 pericfg: power-controller@10003000 {
 159                         compatible = "mediatek,mt8173-pericfg", "syscon";
 160                         reg = <0 0x10003000 0 0x1000>;
 161                         #clock-cells = <1>;
 162                         #reset-cells = <1>;
 163                 };
 164
 165                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 166                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 167                         reg = <0 0x10005000 0 0x1000>;
 168                 };
 169
 170                 pio: pinctrl@0x10005000 {
 171                         compatible = "mediatek,mt8173-pinctrl";
 172                         reg = <0 0x1000b000 0 0x1000>;
 173                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 174                         pins-are-numbered;
 175                         gpio-controller;
 176                         #gpio-cells = <2>;
 177                         interrupt-controller;
 178                         #interrupt-cells = <2>;
 179                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 180                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 182
 183                         i2c0_pins_a: i2c0 {
 184                                 pins1 {
 185                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 186                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 187                                         bias-disable;
 188                                 };
 189                         };
 190
 191                         i2c1_pins_a: i2c1 {
 192                                 pins1 {
 193                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 194                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 195                                         bias-disable;
 196                                 };
 197                         };
 198
 199                         i2c2_pins_a: i2c2 {
 200                                 pins1 {
 201                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 202                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 203                                         bias-disable;
 204                                 };
 205                         };
 206
 207                         i2c3_pins_a: i2c3 {
 208                                 pins1 {
 209                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 210                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 211                                         bias-disable;
 212                                 };
 213                         };
 214
 215                         i2c4_pins_a: i2c4 {
 216                                 pins1 {
 217                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 218                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 219                                         bias-disable;
 220                                 };
 221                         };
 222
 223                         i2c6_pins_a: i2c6 {
 224                                 pins1 {
 225                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 226                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 227                                         bias-disable;
 228                                 };
 229                         };
 230                 };
 231
 232                 scpsys: scpsys@10006000 {
 233                         compatible = "mediatek,mt8173-scpsys";
 234                         #power-domain-cells = <1>;
 235                         reg = <0 0x10006000 0 0x1000>;
 236                         clocks = <&clk26m>,
 237                                  <&topckgen CLK_TOP_MM_SEL>;
 238                         clock-names = "mfg", "mm";
 239                         infracfg = <&infracfg>;
 240                 };
 241
 242                 watchdog: watchdog@10007000 {
 243                         compatible = "mediatek,mt8173-wdt",
 244                                      "mediatek,mt6589-wdt";
 245                         reg = <0 0x10007000 0 0x100>;
 246                 };
 247
 248                 pwrap: pwrap@1000d000 {
 249                         compatible = "mediatek,mt8173-pwrap";
 250                         reg = <0 0x1000d000 0 0x1000>;
 251                         reg-names = "pwrap";
 252                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 253                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 254                         reset-names = "pwrap";
 255                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 256                         clock-names = "spi", "wrap";
 257                 };
 258
 259                 sysirq: intpol-controller@10200620 {
 260                         compatible = "mediatek,mt8173-sysirq",
 261                                      "mediatek,mt6577-sysirq";
 262                         interrupt-controller;
 263                         #interrupt-cells = <3>;
 264                         interrupt-parent = <&gic>;
 265                         reg = <0 0x10200620 0 0x20>;
 266                 };
 267
 268                 apmixedsys: clock-controller@10209000 {
 269                         compatible = "mediatek,mt8173-apmixedsys";
 270                         reg = <0 0x10209000 0 0x1000>;
 271                         #clock-cells = <1>;
 272                 };
 273
 274                 gic: interrupt-controller@10220000 {
 275                         compatible = "arm,gic-400";
 276                         #interrupt-cells = <3>;
 277                         interrupt-parent = <&gic>;
 278                         interrupt-controller;
 279                         reg = <0 0x10221000 0 0x1000>,
 280                               <0 0x10222000 0 0x2000>,
 281                               <0 0x10224000 0 0x2000>,
 282                               <0 0x10226000 0 0x2000>;
 283                         interrupts = <GIC_PPI 9
 284                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 285                 };
 286
 287                 uart0: serial@11002000 {
 288                         compatible = "mediatek,mt8173-uart",
 289                                      "mediatek,mt6577-uart";
 290                         reg = <0 0x11002000 0 0x400>;
 291                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 292                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 293                         clock-names = "baud", "bus";
 294                         status = "disabled";
 295                 };
 296
 297                 uart1: serial@11003000 {
 298                         compatible = "mediatek,mt8173-uart",
 299                                      "mediatek,mt6577-uart";
 300                         reg = <0 0x11003000 0 0x400>;
 301                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 302                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 303                         clock-names = "baud", "bus";
 304                         status = "disabled";
 305                 };
 306
 307                 uart2: serial@11004000 {
 308                         compatible = "mediatek,mt8173-uart",
 309                                      "mediatek,mt6577-uart";
 310                         reg = <0 0x11004000 0 0x400>;
 311                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 312                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 313                         clock-names = "baud", "bus";
 314                         status = "disabled";
 315                 };
 316
 317                 uart3: serial@11005000 {
 318                         compatible = "mediatek,mt8173-uart",
 319                                      "mediatek,mt6577-uart";
 320                         reg = <0 0x11005000 0 0x400>;
 321                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 322                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 323                         clock-names = "baud", "bus";
 324                         status = "disabled";
 325                 };
 326
 327                 i2c0: i2c@11007000 {
 328                         compatible = "mediatek,mt8173-i2c";
 329                         reg = <0 0x11007000 0 0x70>,
 330                               <0 0x11000100 0 0x80>;
 331                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 332                         clock-div = <16>;
 333                         clocks = <&pericfg CLK_PERI_I2C0>,
 334                                  <&pericfg CLK_PERI_AP_DMA>;
 335                         clock-names = "main", "dma";
 336                         pinctrl-names = "default";
 337                         pinctrl-0 = <&i2c0_pins_a>;
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                         status = "disabled";
 341                 };
 342
 343                 i2c1: i2c@11008000 {
 344                         compatible = "mediatek,mt8173-i2c";
 345                         reg = <0 0x11008000 0 0x70>,
 346                               <0 0x11000180 0 0x80>;
 347                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 348                         clock-div = <16>;
 349                         clocks = <&pericfg CLK_PERI_I2C1>,
 350                                  <&pericfg CLK_PERI_AP_DMA>;
 351                         clock-names = "main", "dma";
 352                         pinctrl-names = "default";
 353                         pinctrl-0 = <&i2c1_pins_a>;
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         status = "disabled";
 357                 };
 358
 359                 i2c2: i2c@11009000 {
 360                         compatible = "mediatek,mt8173-i2c";
 361                         reg = <0 0x11009000 0 0x70>,
 362                               <0 0x11000200 0 0x80>;
 363                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 364                         clock-div = <16>;
 365                         clocks = <&pericfg CLK_PERI_I2C2>,
 366                                  <&pericfg CLK_PERI_AP_DMA>;
 367                         clock-names = "main", "dma";
 368                         pinctrl-names = "default";
 369                         pinctrl-0 = <&i2c2_pins_a>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         status = "disabled";
 373                 };
 374
 375                 spi: spi@1100a000 {
 376                         compatible = "mediatek,mt8173-spi";
 377                         #address-cells = <1>;
 378                         #size-cells = <0>;
 379                         reg = <0 0x1100a000 0 0x1000>;
 380                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 381                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 382                                  <&topckgen CLK_TOP_SPI_SEL>,
 383                                  <&pericfg CLK_PERI_SPI0>;
 384                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 385                         status = "disabled";
 386                 };
 387
 388                 i2c3: i2c@11010000 {
 389                         compatible = "mediatek,mt8173-i2c";
 390                         reg = <0 0x11010000 0 0x70>,
 391                               <0 0x11000280 0 0x80>;
 392                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 393                         clock-div = <16>;
 394                         clocks = <&pericfg CLK_PERI_I2C3>,
 395                                  <&pericfg CLK_PERI_AP_DMA>;
 396                         clock-names = "main", "dma";
 397                         pinctrl-names = "default";
 398                         pinctrl-0 = <&i2c3_pins_a>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         status = "disabled";
 402                 };
 403
 404                 i2c4: i2c@11011000 {
 405                         compatible = "mediatek,mt8173-i2c";
 406                         reg = <0 0x11011000 0 0x70>,
 407                               <0 0x11000300 0 0x80>;
 408                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 409                         clock-div = <16>;
 410                         clocks = <&pericfg CLK_PERI_I2C4>,
 411                                  <&pericfg CLK_PERI_AP_DMA>;
 412                         clock-names = "main", "dma";
 413                         pinctrl-names = "default";
 414                         pinctrl-0 = <&i2c4_pins_a>;
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         status = "disabled";
 418                 };
 419
 420                 i2c6: i2c@11013000 {
 421                         compatible = "mediatek,mt8173-i2c";
 422                         reg = <0 0x11013000 0 0x70>,
 423                               <0 0x11000080 0 0x80>;
 424                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 425                         clock-div = <16>;
 426                         clocks = <&pericfg CLK_PERI_I2C6>,
 427                                  <&pericfg CLK_PERI_AP_DMA>;
 428                         clock-names = "main", "dma";
 429                         pinctrl-names = "default";
 430                         pinctrl-0 = <&i2c6_pins_a>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         status = "disabled";
 434                 };
 435
 436                 afe: audio-controller@11220000  {
 437                         compatible = "mediatek,mt8173-afe-pcm";
 438                         reg = <0 0x11220000 0 0x1000>;
 439                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 440                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 441                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 442                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 443                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 444                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 445                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 446                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 447                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 448                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 449                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 450                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 451                         clock-names = "infra_sys_audio_clk",
 452                                       "top_pdn_audio",
 453                                       "top_pdn_aud_intbus",
 454                                       "bck0",
 455                                       "bck1",
 456                                       "i2s0_m",
 457                                       "i2s1_m",
 458                                       "i2s2_m",
 459                                       "i2s3_m",
 460                                       "i2s3_b";
 461                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 462                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 463                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 464                                                  <&topckgen CLK_TOP_APLL2>;
 465                 };
 466
 467                 mmc0: mmc@11230000 {
 468                         compatible = "mediatek,mt8173-mmc",
 469                                      "mediatek,mt8135-mmc";
 470                         reg = <0 0x11230000 0 0x1000>;
 471                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 472                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 473                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 474                         clock-names = "source", "hclk";
 475                         status = "disabled";
 476                 };
 477
 478                 mmc1: mmc@11240000 {
 479                         compatible = "mediatek,mt8173-mmc",
 480                                      "mediatek,mt8135-mmc";
 481                         reg = <0 0x11240000 0 0x1000>;
 482                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 483                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 484                                  <&topckgen CLK_TOP_AXI_SEL>;
 485                         clock-names = "source", "hclk";
 486                         status = "disabled";
 487                 };
 488
 489                 mmc2: mmc@11250000 {
 490                         compatible = "mediatek,mt8173-mmc",
 491                                      "mediatek,mt8135-mmc";
 492                         reg = <0 0x11250000 0 0x1000>;
 493                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 494                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 495                                  <&topckgen CLK_TOP_AXI_SEL>;
 496                         clock-names = "source", "hclk";
 497                         status = "disabled";
 498                 };
 499
 500                 mmc3: mmc@11260000 {
 501                         compatible = "mediatek,mt8173-mmc",
 502                                      "mediatek,mt8135-mmc";
 503                         reg = <0 0x11260000 0 0x1000>;
 504                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 505                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 506                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 507                         clock-names = "source", "hclk";
 508                         status = "disabled";
 509                 };
 510
 511                 mmsys: clock-controller@14000000 {
 512                         compatible = "mediatek,mt8173-mmsys", "syscon";
 513                         reg = <0 0x14000000 0 0x1000>;
 514                         #clock-cells = <1>;
 515                 };
 516
 517                 imgsys: clock-controller@15000000 {
 518                         compatible = "mediatek,mt8173-imgsys", "syscon";
 519                         reg = <0 0x15000000 0 0x1000>;
 520                         #clock-cells = <1>;
 521                 };
 522
 523                 vdecsys: clock-controller@16000000 {
 524                         compatible = "mediatek,mt8173-vdecsys", "syscon";
 525                         reg = <0 0x16000000 0 0x1000>;
 526                         #clock-cells = <1>;
 527                 };
 528
 529                 vencsys: clock-controller@18000000 {
 530                         compatible = "mediatek,mt8173-vencsys", "syscon";
 531                         reg = <0 0x18000000 0 0x1000>;
 532                         #clock-cells = <1>;
 533                 };
 534
 535                 vencltsys: clock-controller@19000000 {
 536                         compatible = "mediatek,mt8173-vencltsys", "syscon";
 537                         reg = <0 0x19000000 0 0x1000>;
 538                         #clock-cells = <1>;
 539                 };
 540         };
 541 };
 542