1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 compatible = "nvidia,tegra210";
9 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra210-host1x", "simple-bus";
15 reg = <0x0 0x50000000 0x0 0x00034000>;
16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
18 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
19 clock-names = "host1x";
20 resets = <&tegra_car 28>;
21 reset-names = "host1x";
26 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
28 dpaux1: dpaux@54040000 {
29 compatible = "nvidia,tegra210-dpaux";
30 reg = <0x0 0x54040000 0x0 0x00040000>;
31 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
33 <&tegra_car TEGRA210_CLK_PLL_DP>;
34 clock-names = "dpaux", "parent";
35 resets = <&tegra_car 207>;
36 reset-names = "dpaux";
39 state_dpaux1_aux: pinmux-aux {
44 state_dpaux1_i2c: pinmux-i2c {
49 state_dpaux1_off: pinmux-off {
61 compatible = "nvidia,tegra210-vi";
62 reg = <0x0 0x54080000 0x0 0x00040000>;
63 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
68 compatible = "nvidia,tegra210-tsec";
69 reg = <0x0 0x54100000 0x0 0x00040000>;
73 compatible = "nvidia,tegra210-dc";
74 reg = <0x0 0x54200000 0x0 0x00040000>;
75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
76 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
77 <&tegra_car TEGRA210_CLK_PLL_P>;
78 clock-names = "dc", "parent";
79 resets = <&tegra_car 27>;
82 iommus = <&mc TEGRA_SWGROUP_DC>;
88 compatible = "nvidia,tegra210-dc";
89 reg = <0x0 0x54240000 0x0 0x00040000>;
90 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
92 <&tegra_car TEGRA210_CLK_PLL_P>;
93 clock-names = "dc", "parent";
94 resets = <&tegra_car 26>;
97 iommus = <&mc TEGRA_SWGROUP_DCB>;
103 compatible = "nvidia,tegra210-dsi";
104 reg = <0x0 0x54300000 0x0 0x00040000>;
105 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
106 <&tegra_car TEGRA210_CLK_DSIALP>,
107 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
108 clock-names = "dsi", "lp", "parent";
109 resets = <&tegra_car 48>;
111 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
115 #address-cells = <1>;
120 compatible = "nvidia,tegra210-vic";
121 reg = <0x0 0x54340000 0x0 0x00040000>;
126 compatible = "nvidia,tegra210-nvjpg";
127 reg = <0x0 0x54380000 0x0 0x00040000>;
132 compatible = "nvidia,tegra210-dsi";
133 reg = <0x0 0x54400000 0x0 0x00040000>;
134 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
135 <&tegra_car TEGRA210_CLK_DSIBLP>,
136 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
137 clock-names = "dsi", "lp", "parent";
138 resets = <&tegra_car 82>;
140 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
144 #address-cells = <1>;
149 compatible = "nvidia,tegra210-nvdec";
150 reg = <0x0 0x54480000 0x0 0x00040000>;
155 compatible = "nvidia,tegra210-nvenc";
156 reg = <0x0 0x544c0000 0x0 0x00040000>;
161 compatible = "nvidia,tegra210-tsec";
162 reg = <0x0 0x54500000 0x0 0x00040000>;
167 compatible = "nvidia,tegra210-sor";
168 reg = <0x0 0x54540000 0x0 0x00040000>;
169 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
171 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
172 <&tegra_car TEGRA210_CLK_PLL_DP>,
173 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
174 clock-names = "sor", "parent", "dp", "safe";
175 resets = <&tegra_car 182>;
177 pinctrl-0 = <&state_dpaux_aux>;
178 pinctrl-1 = <&state_dpaux_i2c>;
179 pinctrl-2 = <&state_dpaux_off>;
180 pinctrl-names = "aux", "i2c", "off";
185 compatible = "nvidia,tegra210-sor1";
186 reg = <0x0 0x54580000 0x0 0x00040000>;
187 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
189 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
190 <&tegra_car TEGRA210_CLK_PLL_DP>,
191 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
192 clock-names = "sor", "parent", "dp", "safe";
193 resets = <&tegra_car 183>;
195 pinctrl-0 = <&state_dpaux1_aux>;
196 pinctrl-1 = <&state_dpaux1_i2c>;
197 pinctrl-2 = <&state_dpaux1_off>;
198 pinctrl-names = "aux", "i2c", "off";
202 dpaux: dpaux@545c0000 {
203 compatible = "nvidia,tegra124-dpaux";
204 reg = <0x0 0x545c0000 0x0 0x00040000>;
205 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
207 <&tegra_car TEGRA210_CLK_PLL_DP>;
208 clock-names = "dpaux", "parent";
209 resets = <&tegra_car 181>;
210 reset-names = "dpaux";
213 state_dpaux_aux: pinmux-aux {
218 state_dpaux_i2c: pinmux-i2c {
223 state_dpaux_off: pinmux-off {
229 #address-cells = <1>;
235 compatible = "nvidia,tegra210-isp";
236 reg = <0x0 0x54600000 0x0 0x00040000>;
237 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
242 compatible = "nvidia,tegra210-isp";
243 reg = <0x0 0x54680000 0x0 0x00040000>;
244 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
249 compatible = "nvidia,tegra210-i2c-vi";
250 reg = <0x0 0x546c0000 0x0 0x00040000>;
251 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
256 gic: interrupt-controller@50041000 {
257 compatible = "arm,gic-400";
258 #interrupt-cells = <3>;
259 interrupt-controller;
260 reg = <0x0 0x50041000 0x0 0x1000>,
261 <0x0 0x50042000 0x0 0x2000>,
262 <0x0 0x50044000 0x0 0x2000>,
263 <0x0 0x50046000 0x0 0x2000>;
264 interrupts = <GIC_PPI 9
265 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
266 interrupt-parent = <&gic>;
270 compatible = "nvidia,gm20b";
271 reg = <0x0 0x57000000 0x0 0x01000000>,
272 <0x0 0x58000000 0x0 0x01000000>;
273 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "stall", "nonstall";
276 clocks = <&tegra_car TEGRA210_CLK_GPU>,
277 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
278 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
279 clock-names = "gpu", "pwr", "ref";
280 resets = <&tegra_car 184>;
283 iommus = <&mc TEGRA_SWGROUP_GPU>;
288 lic: interrupt-controller@60004000 {
289 compatible = "nvidia,tegra210-ictlr";
290 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
291 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
292 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
293 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
294 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
295 <0x0 0x60004500 0x0 0x40>; /* senary controller */
296 interrupt-controller;
297 #interrupt-cells = <3>;
298 interrupt-parent = <&gic>;
302 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
303 reg = <0x0 0x60005000 0x0 0x400>;
304 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
311 clock-names = "timer";
314 tegra_car: clock@60006000 {
315 compatible = "nvidia,tegra210-car";
316 reg = <0x0 0x60006000 0x0 0x1000>;
321 flow-controller@60007000 {
322 compatible = "nvidia,tegra210-flowctrl";
323 reg = <0x0 0x60007000 0x0 0x1000>;
326 gpio: gpio@6000d000 {
327 compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
328 reg = <0x0 0x6000d000 0x0 0x1000>;
329 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
339 #interrupt-cells = <2>;
340 interrupt-controller;
343 apbdma: dma@60020000 {
344 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
345 reg = <0x0 0x60020000 0x0 0x1400>;
346 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
380 resets = <&tegra_car 34>;
386 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
387 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
388 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
391 pinmux: pinmux@700008d4 {
392 compatible = "nvidia,tegra210-pinmux";
393 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
394 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
398 * There are two serial driver i.e. 8250 based simple serial
399 * driver and APB DMA based serial driver for higher baudrate
400 * and performance. To enable the 8250 based driver, the compatible
401 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
402 * the APB DMA based serial driver, the compatible is
403 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
405 uarta: serial@70006000 {
406 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
407 reg = <0x0 0x70006000 0x0 0x40>;
409 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
411 clock-names = "serial";
412 resets = <&tegra_car 6>;
413 reset-names = "serial";
414 dmas = <&apbdma 8>, <&apbdma 8>;
415 dma-names = "rx", "tx";
419 uartb: serial@70006040 {
420 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
421 reg = <0x0 0x70006040 0x0 0x40>;
423 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
425 clock-names = "serial";
426 resets = <&tegra_car 7>;
427 reset-names = "serial";
428 dmas = <&apbdma 9>, <&apbdma 9>;
429 dma-names = "rx", "tx";
433 uartc: serial@70006200 {
434 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
435 reg = <0x0 0x70006200 0x0 0x40>;
437 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
439 clock-names = "serial";
440 resets = <&tegra_car 55>;
441 reset-names = "serial";
442 dmas = <&apbdma 10>, <&apbdma 10>;
443 dma-names = "rx", "tx";
447 uartd: serial@70006300 {
448 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
449 reg = <0x0 0x70006300 0x0 0x40>;
451 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
453 clock-names = "serial";
454 resets = <&tegra_car 65>;
455 reset-names = "serial";
456 dmas = <&apbdma 19>, <&apbdma 19>;
457 dma-names = "rx", "tx";
462 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
463 reg = <0x0 0x7000a000 0x0 0x100>;
465 clocks = <&tegra_car TEGRA210_CLK_PWM>;
467 resets = <&tegra_car 17>;
473 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
474 reg = <0x0 0x7000c000 0x0 0x100>;
475 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
478 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
479 clock-names = "div-clk";
480 resets = <&tegra_car 12>;
482 dmas = <&apbdma 21>, <&apbdma 21>;
483 dma-names = "rx", "tx";
488 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
489 reg = <0x0 0x7000c400 0x0 0x100>;
490 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
493 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
494 clock-names = "div-clk";
495 resets = <&tegra_car 54>;
497 dmas = <&apbdma 22>, <&apbdma 22>;
498 dma-names = "rx", "tx";
503 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
504 reg = <0x0 0x7000c500 0x0 0x100>;
505 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
506 #address-cells = <1>;
508 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
509 clock-names = "div-clk";
510 resets = <&tegra_car 67>;
512 dmas = <&apbdma 23>, <&apbdma 23>;
513 dma-names = "rx", "tx";
518 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
519 reg = <0x0 0x7000c700 0x0 0x100>;
520 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
521 #address-cells = <1>;
523 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
524 clock-names = "div-clk";
525 resets = <&tegra_car 103>;
527 dmas = <&apbdma 26>, <&apbdma 26>;
528 dma-names = "rx", "tx";
529 pinctrl-0 = <&state_dpaux1_i2c>;
530 pinctrl-1 = <&state_dpaux1_off>;
531 pinctrl-names = "default", "idle";
536 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
537 reg = <0x0 0x7000d000 0x0 0x100>;
538 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
539 #address-cells = <1>;
541 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
542 clock-names = "div-clk";
543 resets = <&tegra_car 47>;
545 dmas = <&apbdma 24>, <&apbdma 24>;
546 dma-names = "rx", "tx";
551 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
552 reg = <0x0 0x7000d100 0x0 0x100>;
553 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
556 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
557 clock-names = "div-clk";
558 resets = <&tegra_car 166>;
560 dmas = <&apbdma 30>, <&apbdma 30>;
561 dma-names = "rx", "tx";
562 pinctrl-0 = <&state_dpaux_i2c>;
563 pinctrl-1 = <&state_dpaux_off>;
564 pinctrl-names = "default", "idle";
569 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
570 reg = <0x0 0x7000d400 0x0 0x200>;
571 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
572 #address-cells = <1>;
574 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
576 resets = <&tegra_car 41>;
578 dmas = <&apbdma 15>, <&apbdma 15>;
579 dma-names = "rx", "tx";
584 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
585 reg = <0x0 0x7000d600 0x0 0x200>;
586 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
587 #address-cells = <1>;
589 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
591 resets = <&tegra_car 44>;
593 dmas = <&apbdma 16>, <&apbdma 16>;
594 dma-names = "rx", "tx";
599 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
600 reg = <0x0 0x7000d800 0x0 0x200>;
601 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
602 #address-cells = <1>;
604 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
606 resets = <&tegra_car 46>;
608 dmas = <&apbdma 17>, <&apbdma 17>;
609 dma-names = "rx", "tx";
614 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
615 reg = <0x0 0x7000da00 0x0 0x200>;
616 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
617 #address-cells = <1>;
619 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
621 resets = <&tegra_car 68>;
623 dmas = <&apbdma 18>, <&apbdma 18>;
624 dma-names = "rx", "tx";
629 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
630 reg = <0x0 0x7000e000 0x0 0x100>;
631 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_CLK_RTC>;
637 compatible = "nvidia,tegra210-pmc";
638 reg = <0x0 0x7000e400 0x0 0x400>;
639 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
640 clock-names = "pclk", "clk32k_in";
644 clocks = <&tegra_car TEGRA210_CLK_APE>,
645 <&tegra_car TEGRA210_CLK_APB2APE>;
646 resets = <&tegra_car 198>;
647 #power-domain-cells = <0>;
651 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
652 clock-names = "xusb-ss";
653 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
654 reset-names = "xusb-ss";
655 #power-domain-cells = <0>;
659 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
660 clock-names = "xusb-dev";
661 resets = <&tegra_car 95>;
662 reset-names = "xusb-dev";
663 #power-domain-cells = <0>;
667 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
668 clock-names = "xusb-host";
669 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
670 reset-names = "xusb-host";
671 #power-domain-cells = <0>;
677 compatible = "nvidia,tegra210-efuse";
678 reg = <0x0 0x7000f800 0x0 0x400>;
679 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
680 clock-names = "fuse";
681 resets = <&tegra_car 39>;
682 reset-names = "fuse";
685 mc: memory-controller@70019000 {
686 compatible = "nvidia,tegra210-mc";
687 reg = <0x0 0x70019000 0x0 0x1000>;
688 clocks = <&tegra_car TEGRA210_CLK_MC>;
691 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
697 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
698 reg = <0x0 0x70030000 0x0 0x10000>;
699 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&tegra_car TEGRA210_CLK_HDA>,
701 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
702 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
703 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
704 resets = <&tegra_car 125>, /* hda */
705 <&tegra_car 128>, /* hda2hdmi */
706 <&tegra_car 111>; /* hda2codec_2x */
707 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
712 compatible = "nvidia,tegra210-xusb";
713 reg = <0x0 0x70090000 0x0 0x8000>,
714 <0x0 0x70098000 0x0 0x1000>,
715 <0x0 0x70099000 0x0 0x1000>;
716 reg-names = "hcd", "fpci", "ipfs";
718 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
722 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
723 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
724 <&tegra_car TEGRA210_CLK_XUSB_SS>,
725 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
726 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
727 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
728 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
729 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
730 <&tegra_car TEGRA210_CLK_CLK_M>,
731 <&tegra_car TEGRA210_CLK_PLL_E>;
732 clock-names = "xusb_host", "xusb_host_src",
733 "xusb_falcon_src", "xusb_ss",
734 "xusb_ss_div2", "xusb_ss_src",
735 "xusb_hs_src", "xusb_fs_src",
736 "pll_u_480m", "clk_m", "pll_e";
737 resets = <&tegra_car 89>, <&tegra_car 156>,
739 reset-names = "xusb_host", "xusb_ss", "xusb_src";
741 nvidia,xusb-padctl = <&padctl>;
746 padctl: padctl@7009f000 {
747 compatible = "nvidia,tegra210-xusb-padctl";
748 reg = <0x0 0x7009f000 0x0 0x1000>;
749 resets = <&tegra_car 142>;
750 reset-names = "padctl";
756 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
784 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
802 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
804 resets = <&tegra_car 205>;
847 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
849 resets = <&tegra_car 204>;
902 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
903 reg = <0x0 0x700b0000 0x0 0x200>;
904 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
906 clock-names = "sdhci";
907 resets = <&tegra_car 14>;
908 reset-names = "sdhci";
913 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
914 reg = <0x0 0x700b0200 0x0 0x200>;
915 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
917 clock-names = "sdhci";
918 resets = <&tegra_car 9>;
919 reset-names = "sdhci";
924 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
925 reg = <0x0 0x700b0400 0x0 0x200>;
926 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
928 clock-names = "sdhci";
929 resets = <&tegra_car 69>;
930 reset-names = "sdhci";
935 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
936 reg = <0x0 0x700b0600 0x0 0x200>;
937 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
939 clock-names = "sdhci";
940 resets = <&tegra_car 15>;
941 reset-names = "sdhci";
945 mipi: mipi@700e3000 {
946 compatible = "nvidia,tegra210-mipi";
947 reg = <0x0 0x700e3000 0x0 0x100>;
948 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
949 clock-names = "mipi-cal";
950 #nvidia,mipi-calibrate-cells = <1>;
954 compatible = "nvidia,tegra210-aconnect";
955 clocks = <&tegra_car TEGRA210_CLK_APE>,
956 <&tegra_car TEGRA210_CLK_APB2APE>;
957 clock-names = "ape", "apb2ape";
958 power-domains = <&pd_audio>;
959 #address-cells = <1>;
961 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
966 compatible = "nvidia,tegra210-qspi";
967 reg = <0x0 0x70410000 0x0 0x1000>;
968 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
969 #address-cells = <1>;
971 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
972 clock-names = "qspi";
973 resets = <&tegra_car 211>;
974 reset-names = "qspi";
975 dmas = <&apbdma 5>, <&apbdma 5>;
976 dma-names = "rx", "tx";
981 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
982 reg = <0x0 0x7d000000 0x0 0x4000>;
983 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&tegra_car TEGRA210_CLK_USBD>;
987 resets = <&tegra_car 22>;
989 nvidia,phy = <&phy1>;
993 phy1: usb-phy@7d000000 {
994 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
995 reg = <0x0 0x7d000000 0x0 0x4000>,
996 <0x0 0x7d000000 0x0 0x4000>;
998 clocks = <&tegra_car TEGRA210_CLK_USBD>,
999 <&tegra_car TEGRA210_CLK_PLL_U>,
1000 <&tegra_car TEGRA210_CLK_USBD>;
1001 clock-names = "reg", "pll_u", "utmi-pads";
1002 resets = <&tegra_car 22>, <&tegra_car 22>;
1003 reset-names = "usb", "utmi-pads";
1004 nvidia,hssync-start-delay = <0>;
1005 nvidia,idle-wait-delay = <17>;
1006 nvidia,elastic-limit = <16>;
1007 nvidia,term-range-adj = <6>;
1008 nvidia,xcvr-setup = <9>;
1009 nvidia,xcvr-lsfslew = <0>;
1010 nvidia,xcvr-lsrslew = <3>;
1011 nvidia,hssquelch-level = <2>;
1012 nvidia,hsdiscon-level = <5>;
1013 nvidia,xcvr-hsslew = <12>;
1014 nvidia,has-utmi-pad-registers;
1015 status = "disabled";
1019 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1020 reg = <0x0 0x7d004000 0x0 0x4000>;
1021 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1024 clock-names = "usb";
1025 resets = <&tegra_car 58>;
1026 reset-names = "usb";
1027 nvidia,phy = <&phy2>;
1028 status = "disabled";
1031 phy2: usb-phy@7d004000 {
1032 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1033 reg = <0x0 0x7d004000 0x0 0x4000>,
1034 <0x0 0x7d000000 0x0 0x4000>;
1036 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1037 <&tegra_car TEGRA210_CLK_PLL_U>,
1038 <&tegra_car TEGRA210_CLK_USBD>;
1039 clock-names = "reg", "pll_u", "utmi-pads";
1040 resets = <&tegra_car 58>, <&tegra_car 22>;
1041 reset-names = "usb", "utmi-pads";
1042 nvidia,hssync-start-delay = <0>;
1043 nvidia,idle-wait-delay = <17>;
1044 nvidia,elastic-limit = <16>;
1045 nvidia,term-range-adj = <6>;
1046 nvidia,xcvr-setup = <9>;
1047 nvidia,xcvr-lsfslew = <0>;
1048 nvidia,xcvr-lsrslew = <3>;
1049 nvidia,hssquelch-level = <2>;
1050 nvidia,hsdiscon-level = <5>;
1051 nvidia,xcvr-hsslew = <12>;
1052 status = "disabled";
1056 #address-cells = <1>;
1060 device_type = "cpu";
1061 compatible = "arm,cortex-a57";
1066 device_type = "cpu";
1067 compatible = "arm,cortex-a57";
1072 device_type = "cpu";
1073 compatible = "arm,cortex-a57";
1078 device_type = "cpu";
1079 compatible = "arm,cortex-a57";
1085 compatible = "arm,armv8-timer";
1086 interrupts = <GIC_PPI 13
1087 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1089 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1091 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1093 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1094 interrupt-parent = <&gic>;