arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17 #include <dt-bindings/clock/qcom,rpmcc.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19 #include <dt-bindings/arm/qcom-ids.h>
  20
  21 / {
  22         model = "Qualcomm Technologies, Inc. MSM8916";
  23         compatible = "qcom,msm8916";
  24         qcom,msm-id =   <QCOM_ID_MSM8916 0>,
  25                         <QCOM_ID_MSM8216 0>,
  26                         <QCOM_ID_MSM8116 0>,
  27                         <QCOM_ID_MSM8616 0>,
  28                         <QCOM_ID_APQ8016 0>;
  29
  30
  31         interrupt-parent = <&intc>;
  32
  33         #address-cells = <2>;
  34         #size-cells = <2>;
  35
  36         aliases {
  37                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  38                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  39         };
  40
  41         chosen { };
  42
  43         memory {
  44                 device_type = "memory";
  45                 /* We expect the bootloader to fill in the reg */
  46                 reg = <0 0 0 0>;
  47         };
  48
  49         reserved-memory {
  50                 #address-cells = <2>;
  51                 #size-cells = <2>;
  52                 ranges;
  53
  54                 reserve_aligned@86000000 {
  55                         reg = <0x0 0x86000000 0x0 0x0300000>;
  56                         no-map;
  57                 };
  58
  59                 smem_mem: smem_region@86300000 {
  60                         reg = <0x0 0x86300000 0x0 0x0100000>;
  61                         no-map;
  62                 };
  63
  64                 hypervisor_mem: hypervisor_region@86400000 {
  65                         no-map;
  66                         reg = <0x0 0x86400000 0x0 0x0400000>;
  67                 };
  68
  69                 modem_adsp_mem: modem_adsp_region@86800000 {
  70                         no-map;
  71                         reg = <0x0 0x86800000 0x0 0x04800000>;
  72                 };
  73
  74                 rmtfs@86700000 {
  75                         reg = <0x0 0x86700000 0x0 0xe0000>;
  76                         no-map;
  77                 };
  78
  79                 peripheral_mem: peripheral_region@8b600000 {
  80                         no-map;
  81                         reg = <0x0 0x8b600000 0x0 0x0600000>;
  82                 };
  83
  84                 wcnss_mem: wcnss@89300000 {
  85                         reg = <0x0 0x89300000 0x0 0x600000>;
  86                         no-map;
  87                 };
  88
  89                 vidc_mem: vidc_region@8f800000 {
  90                         no-map;
  91                         reg = <0 0x8f800000 0 0x800000>;
  92                 };
  93
  94                 mba_mem: mba@8ea00000 {
  95                         no-map;
  96                         reg = <0 0x8ea00000 0 0x100000>;
  97                 };
  98         };
  99
 100         cpus {
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103
 104                 CPU0: cpu@0 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a53", "arm,armv8";
 107                         reg = <0x0>;
 108                         enable-method = "qcom,arm-cortex-acc";
 109                         qcom,acc = <&acc0>;
 110                         next-level-cache = <&L2_0>;
 111                         clocks = <&a53cc 1>;
 112                         clock-latency = <200000>;
 113                         cpu-supply = <&pm8916_spmi_s2>;
 114                         /* cooling options */
 115                         cooling-min-level = <0>;
 116                         cooling-max-level = <7>;
 117                         #cooling-cells = <2>;
 118                         L2_0: l2-cache {
 119                               compatible = "arm,arch-cache";
 120                               cache-level = <2>;
 121                               power-domain = <&l2ccc_0>;
 122                         };
 123                 };
 124
 125                 CPU1: cpu@1 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a53", "arm,armv8";
 128                         reg = <0x1>;
 129                         enable-method = "qcom,arm-cortex-acc";
 130                         qcom,acc = <&acc1>;
 131                         next-level-cache = <&L2_0>;
 132                         clocks = <&a53cc 1>;
 133                         clock-latency = <200000>;
 134                         cpu-supply = <&pm8916_spmi_s2>;
 135                         /* cooling options */
 136                         cooling-min-level = <0>;
 137                         cooling-max-level = <7>;
 138                         #cooling-cells = <2>;
 139                 };
 140
 141                 CPU2: cpu@2 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-a53", "arm,armv8";
 144                         reg = <0x2>;
 145                         enable-method = "qcom,arm-cortex-acc";
 146                         qcom,acc = <&acc2>;
 147                         next-level-cache = <&L2_0>;
 148                         clocks = <&a53cc 1>;
 149                         clock-latency = <200000>;
 150                         cpu-supply = <&pm8916_spmi_s2>;
 151                         /* cooling options */
 152                         cooling-min-level = <0>;
 153                         cooling-max-level = <7>;
 154                         #cooling-cells = <2>;
 155                 };
 156
 157                 CPU3: cpu@3 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a53", "arm,armv8";
 160                         reg = <0x3>;
 161                         enable-method = "qcom,arm-cortex-acc";
 162                         qcom,acc = <&acc3>;
 163                         next-level-cache = <&L2_0>;
 164                         clocks = <&a53cc 1>;
 165                         clock-latency = <200000>;
 166                         cpu-supply = <&pm8916_spmi_s2>;
 167                         /* cooling options */
 168                         cooling-min-level = <0>;
 169                         cooling-max-level = <7>;
 170                         #cooling-cells = <2>;
 171                 };
 172         };
 173
 174         cpu-pmu {
 175                 compatible = "arm,armv8-pmuv3";
 176                 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
 177         };
 178
 179         thermal-zones {
 180                 cpu-thermal0 {
 181                         polling-delay-passive = <250>;
 182                         polling-delay = <1000>;
 183
 184                         thermal-sensors = <&tsens 4>;
 185
 186                         trips {
 187                                 cpu_alert0: trip@0 {
 188                                         temperature = <75000>;
 189                                         hysteresis = <2000>;
 190                                         type = "passive";
 191                                 };
 192                                 cpu_crit0: trip@1 {
 193                                         temperature = <100000>;
 194                                         hysteresis = <2000>;
 195                                         type = "critical";
 196                                 };
 197                         };
 198
 199                         cooling-maps {
 200                                 map0 {
 201                                         trip = <&cpu_alert0>;
 202                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 203                                 };
 204                         };
 205                 };
 206
 207                 cpu-thermal1 {
 208                         polling-delay-passive = <250>;
 209                         polling-delay = <1000>;
 210
 211                         thermal-sensors = <&tsens 3>;
 212
 213                         trips {
 214                                 cpu_alert1: trip@0 {
 215                                         temperature = <75000>;
 216                                         hysteresis = <2000>;
 217                                         type = "passive";
 218                                 };
 219                                 cpu_crit1: trip@1 {
 220                                         temperature = <100000>;
 221                                         hysteresis = <2000>;
 222                                         type = "critical";
 223                                 };
 224                         };
 225
 226                         cooling-maps {
 227                                 map0 {
 228                                         trip = <&cpu_alert1>;
 229                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 230                                 };
 231                         };
 232                 };
 233         };
 234
 235         timer {
 236                 compatible = "arm,armv8-timer";
 237                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 238                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 239                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 240                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 241         };
 242
 243         clocks {
 244                 xo_board: xo_board {
 245                         compatible = "fixed-clock";
 246                         #clock-cells = <0>;
 247                         clock-frequency = <19200000>;
 248                         clock-output-names = "xo_board";
 249                 };
 250
 251                 sleep_clk: sleep_clk {
 252                         compatible = "fixed-clock";
 253                         #clock-cells = <0>;
 254                         clock-frequency = <32768>;
 255                 };
 256         };
 257
 258         firmware {
 259                 compatible = "simple-bus";
 260
 261                 scm: scm {
 262                         compatible = "qcom,scm";
 263                         clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 264                         clock-names = "core", "bus", "iface";
 265                         #reset-cells = <1>;
 266                 };
 267         };
 268
 269         soc: soc {
 270                 #address-cells = <1>;
 271                 #size-cells = <1>;
 272                 ranges = <0 0 0 0xffffffff>;
 273                 compatible = "simple-bus";
 274
 275                 restart@4ab000 {
 276                         compatible = "qcom,pshold";
 277                         reg = <0x4ab000 0x4>;
 278                 };
 279
 280                 msmgpio: pinctrl@1000000 {
 281                         compatible = "qcom,msm8916-pinctrl";
 282                         reg = <0x1000000 0x300000>;
 283                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 284                         gpio-controller;
 285                         #gpio-cells = <2>;
 286                         interrupt-controller;
 287                         #interrupt-cells = <2>;
 288                 };
 289
 290                 gcc: qcom,gcc@1800000 {
 291                         compatible = "qcom,gcc-msm8916";
 292                         #clock-cells = <1>;
 293                         #reset-cells = <1>;
 294                         #power-domain-cells = <1>;
 295                         reg = <0x1800000 0x80000>;
 296                 };
 297
 298                 tcsr_mutex_regs: syscon@1905000 {
 299                         compatible = "syscon";
 300                         reg = <0x1905000 0x20000>;
 301                 };
 302
 303                 tcsr_mutex: hwlock {
 304                         compatible = "qcom,tcsr-mutex";
 305                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 306                         #hwlock-cells = <1>;
 307                 };
 308
 309                 rpm_msg_ram: memory@60000 {
 310                         compatible = "qcom,rpm-msg-ram";
 311                         reg = <0x60000 0x8000>;
 312                 };
 313
 314                 blsp1_uart1: serial@78af000 {
 315                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 316                         reg = <0x78af000 0x200>;
 317                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 318                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 319                         clock-names = "core", "iface";
 320                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 321                         dma-names = "rx", "tx";
 322                         status = "disabled";
 323                 };
 324
 325                 apcs: syscon@b011000 {
 326                         compatible = "syscon";
 327                         reg = <0x0b011000 0x1000>;
 328                 };
 329
 330                 a53cc: qcom,a53cc@0b016000 {
 331                         compatible = "qcom,clock-a53-msm8916";
 332                         reg = <0x0b016000 0x40>;
 333                         #clock-cells = <1>;
 334                         qcom,apcs = <&apcs>;
 335                 };
 336
 337                 blsp1_uart2: serial@78b0000 {
 338                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 339                         reg = <0x78b0000 0x200>;
 340                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 341                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 342                         clock-names = "core", "iface";
 343                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 344                         dma-names = "rx", "tx";
 345                         status = "disabled";
 346                 };
 347
 348                 blsp_dma: dma@7884000 {
 349                         compatible = "qcom,bam-v1.7.0";
 350                         reg = <0x07884000 0x23000>;
 351                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 352                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 353                         clock-names = "bam_clk";
 354                         #dma-cells = <1>;
 355                         qcom,ee = <0>;
 356                         status = "disabled";
 357                 };
 358
 359                 blsp_spi1: spi@78b5000 {
 360                         compatible = "qcom,spi-qup-v2.2.1";
 361                         reg = <0x078b5000 0x600>;
 362                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 363                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 364                                  <&gcc GCC_BLSP1_AHB_CLK>;
 365                         clock-names = "core", "iface";
 366                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 367                         dma-names = "rx", "tx";
 368                         pinctrl-names = "default", "sleep";
 369                         pinctrl-0 = <&spi1_default>;
 370                         pinctrl-1 = <&spi1_sleep>;
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         status = "disabled";
 374                 };
 375
 376                 blsp_spi2: spi@78b6000 {
 377                         compatible = "qcom,spi-qup-v2.2.1";
 378                         reg = <0x078b6000 0x600>;
 379                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 380                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 381                                  <&gcc GCC_BLSP1_AHB_CLK>;
 382                         clock-names = "core", "iface";
 383                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 384                         dma-names = "rx", "tx";
 385                         pinctrl-names = "default", "sleep";
 386                         pinctrl-0 = <&spi2_default>;
 387                         pinctrl-1 = <&spi2_sleep>;
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                         status = "disabled";
 391                 };
 392
 393                 blsp_spi3: spi@78b7000 {
 394                         compatible = "qcom,spi-qup-v2.2.1";
 395                         reg = <0x078b7000 0x600>;
 396                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 397                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 398                                  <&gcc GCC_BLSP1_AHB_CLK>;
 399                         clock-names = "core", "iface";
 400                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 401                         dma-names = "rx", "tx";
 402                         pinctrl-names = "default", "sleep";
 403                         pinctrl-0 = <&spi3_default>;
 404                         pinctrl-1 = <&spi3_sleep>;
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         status = "disabled";
 408                 };
 409
 410                 blsp_spi4: spi@78b8000 {
 411                         compatible = "qcom,spi-qup-v2.2.1";
 412                         reg = <0x078b8000 0x600>;
 413                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 415                                  <&gcc GCC_BLSP1_AHB_CLK>;
 416                         clock-names = "core", "iface";
 417                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 418                         dma-names = "rx", "tx";
 419                         pinctrl-names = "default", "sleep";
 420                         pinctrl-0 = <&spi4_default>;
 421                         pinctrl-1 = <&spi4_sleep>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         status = "disabled";
 425                 };
 426
 427                 blsp_spi5: spi@78b9000 {
 428                         compatible = "qcom,spi-qup-v2.2.1";
 429                         reg = <0x078b9000 0x600>;
 430                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 432                                  <&gcc GCC_BLSP1_AHB_CLK>;
 433                         clock-names = "core", "iface";
 434                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 435                         dma-names = "rx", "tx";
 436                         pinctrl-names = "default", "sleep";
 437                         pinctrl-0 = <&spi5_default>;
 438                         pinctrl-1 = <&spi5_sleep>;
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         status = "disabled";
 442                 };
 443
 444                 blsp_spi6: spi@78ba000 {
 445                         compatible = "qcom,spi-qup-v2.2.1";
 446                         reg = <0x078ba000 0x600>;
 447                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 448                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 449                                  <&gcc GCC_BLSP1_AHB_CLK>;
 450                         clock-names = "core", "iface";
 451                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 452                         dma-names = "rx", "tx";
 453                         pinctrl-names = "default", "sleep";
 454                         pinctrl-0 = <&spi6_default>;
 455                         pinctrl-1 = <&spi6_sleep>;
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         status = "disabled";
 459                 };
 460
 461                 blsp_i2c2: i2c@78b6000 {
 462                         compatible = "qcom,i2c-qup-v2.2.1";
 463                         reg = <0x78b6000 0x1000>;
 464                         interrupts = <GIC_SPI 96 0>;
 465                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 466                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 467                         clock-names = "iface", "core";
 468                         pinctrl-names = "default", "sleep";
 469                         pinctrl-0 = <&i2c2_default>;
 470                         pinctrl-1 = <&i2c2_sleep>;
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         status = "disabled";
 474                 };
 475
 476                 blsp_i2c4: i2c@78b8000 {
 477                         compatible = "qcom,i2c-qup-v2.2.1";
 478                         reg = <0x78b8000 0x1000>;
 479                         interrupts = <GIC_SPI 98 0>;
 480                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 481                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 482                         clock-names = "iface", "core";
 483                         pinctrl-names = "default", "sleep";
 484                         pinctrl-0 = <&i2c4_default>;
 485                         pinctrl-1 = <&i2c4_sleep>;
 486                         #address-cells = <1>;
 487                         #size-cells = <0>;
 488                         status = "disabled";
 489                 };
 490
 491                 blsp_i2c6: i2c@78ba000 {
 492                         compatible = "qcom,i2c-qup-v2.2.1";
 493                         reg = <0x78ba000 0x1000>;
 494                         interrupts = <GIC_SPI 100 0>;
 495                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 496                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 497                         clock-names = "iface", "core";
 498                         pinctrl-names = "default", "sleep";
 499                         pinctrl-0 = <&i2c6_default>;
 500                         pinctrl-1 = <&i2c6_sleep>;
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         status = "disabled";
 504                 };
 505
 506                 sdhc_1: sdhci@07824000 {
 507                         compatible = "qcom,sdhci-msm-v4";
 508                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 509                         reg-names = "hc_mem", "core_mem";
 510
 511                         interrupts = <0 123 0>, <0 138 0>;
 512                         interrupt-names = "hc_irq", "pwr_irq";
 513                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 514                                  <&gcc GCC_SDCC1_AHB_CLK>;
 515                         clock-names = "core", "iface";
 516                         bus-width = <8>;
 517                         non-removable;
 518                         status = "disabled";
 519                 };
 520
 521                 sdhc_2: sdhci@07864000 {
 522                         compatible = "qcom,sdhci-msm-v4";
 523                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 524                         reg-names = "hc_mem", "core_mem";
 525
 526                         interrupts = <0 125 0>, <0 221 0>;
 527                         interrupt-names = "hc_irq", "pwr_irq";
 528                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 529                                  <&gcc GCC_SDCC2_AHB_CLK>;
 530                         clock-names = "core", "iface";
 531                         bus-width = <4>;
 532                         status = "disabled";
 533                 };
 534
 535                 usb_dev: usb@78d9000 {
 536                         compatible = "qcom,ci-hdrc";
 537                         reg = <0x78d9000 0x400>;
 538                         dr_mode = "peripheral";
 539                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 540                         usb-phy = <&usb_otg>;
 541                         status = "disabled";
 542                 };
 543
 544                 usb_host: ehci@78d9000 {
 545                         compatible = "qcom,ehci-host";
 546                         reg = <0x78d9000 0x400>;
 547                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 548                         usb-phy = <&usb_otg>;
 549                         status = "disabled";
 550                 };
 551
 552                 usb_otg: phy@78d9000 {
 553                         compatible = "qcom,usb-otg-snps";
 554                         reg = <0x78d9000 0x400>;
 555                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 556                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 557
 558                         v1p8-supply = <&pm8916_l7>;
 559                         v3p3-supply = <&pm8916_l13>;
 560                         qcom,vdd-levels = <1 5 7>;
 561                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 562                         dr_mode = "peripheral";
 563                         qcom,otg-control = <2>; // PMIC
 564                         qcom,manual-pullup;
 565
 566                         qcom,msm-bus,name = "usb2";
 567                         qcom,msm-bus,num-cases = <3>;
 568                         qcom,msm-bus,num-paths = <1>;
 569                         qcom,msm-bus,vectors-KBps =
 570                                         <87 512 0 0>,
 571                                         <87 512 80000 0>,
 572                                         <87 512 6000  6000>;
 573
 574                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 575                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 576                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 577                         clock-names = "iface", "core", "sleep";
 578
 579                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 580                                  <&gcc GCC_USB_HS_BCR>;
 581                         reset-names = "phy", "link";
 582                         status = "disabled";
 583                 };
 584
 585                 intc: interrupt-controller@b000000 {
 586                         compatible = "qcom,msm-qgic2";
 587                         interrupt-controller;
 588                         #interrupt-cells = <3>;
 589                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 590                 };
 591
 592                 l2ccc_0: clock-controller@b011000 {
 593                         compatible = "qcom,8916-l2ccc";
 594                         reg = <0x0b011000 0x1000>;
 595                 };
 596
 597                 timer@b020000 {
 598                         #address-cells = <1>;
 599                         #size-cells = <1>;
 600                         ranges;
 601                         compatible = "arm,armv7-timer-mem";
 602                         reg = <0xb020000 0x1000>;
 603                         clock-frequency = <19200000>;
 604
 605                         frame@b021000 {
 606                                 frame-number = <0>;
 607                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 608                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 609                                 reg = <0xb021000 0x1000>,
 610                                       <0xb022000 0x1000>;
 611                         };
 612
 613                         frame@b023000 {
 614                                 frame-number = <1>;
 615                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 616                                 reg = <0xb023000 0x1000>;
 617                                 status = "disabled";
 618                         };
 619
 620                         frame@b024000 {
 621                                 frame-number = <2>;
 622                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 623                                 reg = <0xb024000 0x1000>;
 624                                 status = "disabled";
 625                         };
 626
 627                         frame@b025000 {
 628                                 frame-number = <3>;
 629                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 630                                 reg = <0xb025000 0x1000>;
 631                                 status = "disabled";
 632                         };
 633
 634                         frame@b026000 {
 635                                 frame-number = <4>;
 636                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 637                                 reg = <0xb026000 0x1000>;
 638                                 status = "disabled";
 639                         };
 640
 641                         frame@b027000 {
 642                                 frame-number = <5>;
 643                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 644                                 reg = <0xb027000 0x1000>;
 645                                 status = "disabled";
 646                         };
 647
 648                         frame@b028000 {
 649                                 frame-number = <6>;
 650                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 651                                 reg = <0xb028000 0x1000>;
 652                                 status = "disabled";
 653                         };
 654                 };
 655
 656                 spmi_bus: spmi@200f000 {
 657                         compatible = "qcom,spmi-pmic-arb";
 658                         reg = <0x200f000 0x001000>,
 659                               <0x2400000 0x400000>,
 660                               <0x2c00000 0x400000>,
 661                               <0x3800000 0x200000>,
 662                               <0x200a000 0x002100>;
 663                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 664                         interrupt-names = "periph_irq";
 665                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 666                         qcom,ee = <0>;
 667                         qcom,channel = <0>;
 668                         #address-cells = <2>;
 669                         #size-cells = <0>;
 670                         interrupt-controller;
 671                         #interrupt-cells = <4>;
 672                 };
 673
 674                 rng@22000 {
 675                         compatible = "qcom,prng";
 676                         reg = <0x00022000 0x200>;
 677                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 678                         clock-names = "core";
 679                 };
 680                 acc0: clock-controller@b088000 {
 681                         compatible = "qcom,arm-cortex-acc";
 682                         reg = <0x0b088000 0x1000>,
 683                               <0x0b008000 0x1000>;
 684                 };
 685
 686                 acc1: clock-controller@b098000 {
 687                         compatible = "qcom,arm-cortex-acc";
 688                         reg = <0x0b098000 0x1000>,
 689                               <0x0b008000 0x1000>;
 690                 };
 691
 692                 acc2: clock-controller@b0a8000 {
 693                         compatible = "qcom,arm-cortex-acc";
 694                         reg = <0x0b0a8000 0x1000>,
 695                               <0x0b008000 0x1000>;
 696                 };
 697
 698                 acc3: clock-controller@b0b8000 {
 699                         compatible = "qcom,arm-cortex-acc";
 700                         reg = <0x0b0b8000 0x1000>,
 701                               <0x0b008000 0x1000>;
 702                 };
 703
 704                 /* Audio */
 705
 706                 wcd_digital: codec-digital{
 707                         compatible = "syscon", "qcom,apq8016-wcd-digital-codec";
 708                         reg = <0x0771c000 0x400>;
 709                 };
 710
 711                 lpass: lpass-cpu@07700000 {
 712                         status = "disabled";
 713                         compatible = "qcom,lpass-cpu-apq8016";
 714                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 715                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 716                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 717                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 718                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 719                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 720                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 721
 722                         clock-names = "ahbix-clk",
 723                                         "pcnoc-mport-clk",
 724                                         "pcnoc-sway-clk",
 725                                         "mi2s-bit-clk0",
 726                                         "mi2s-bit-clk1",
 727                                         "mi2s-bit-clk2",
 728                                         "mi2s-bit-clk3";
 729                         #sound-dai-cells = <1>;
 730
 731                         interrupts = <0 160 0>;
 732                         interrupt-names = "lpass-irq-lpaif";
 733                         reg = <0x07708000 0x10000>, <0x07702000 0x4>, <0x07702004 0x4>;
 734                         reg-names = "lpass-lpaif", "mic-iomux", "spkr-iomux";
 735                 };
 736
 737                 sound: sound {
 738                         status = "disabled";
 739                         compatible = "qcom,apq8016-sbc-sndcard";
 740                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
 741                         reg-names = "mic-iomux", "spkr-iomux";
 742                 };
 743
 744                 tcsr: syscon@1937000 {
 745                         compatible = "qcom,tcsr-msm8916", "syscon";
 746                         reg = <0x1937000 0x30000>;
 747                 };
 748
 749                 uqfprom: eeprom@58000 {
 750                         compatible = "qcom,qfprom-msm8916";
 751                         reg = <0x58000 0x7000>;
 752                 };
 753
 754                 cpr@b018000 {
 755                         compatible = "qcom,cpr";
 756                         reg = <0xb018000 0x1000>;
 757                         interrupts = <0 15 1>, <0 16 1>, <0 17 1>;
 758                         vdd-mx-supply = <&pm8916_l3>;
 759                         acc-syscon = <&tcsr>;
 760                         eeprom = <&uqfprom>;
 761
 762                         qcom,cpr-ref-clk = <19200>;
 763                         qcom,cpr-timer-delay-us = <5000>;
 764                         qcom,cpr-timer-cons-up = <0>;
 765                         qcom,cpr-timer-cons-down = <2>;
 766                         qcom,cpr-up-threshold = <0>;
 767                         qcom,cpr-down-threshold = <2>;
 768                         qcom,cpr-idle-clocks = <15>;
 769                         qcom,cpr-gcnt-us = <1>;
 770                         qcom,vdd-apc-step-up-limit = <1>;
 771                         qcom,vdd-apc-step-down-limit = <1>;
 772                         qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
 773                 };
 774
 775                 qfprom: qfprom@5c000 {
 776                         compatible = "qcom,qfprom";
 777                         reg = <0x5c000 0x1000>;
 778                         #address-cells = <1>;
 779                         #size-cells = <1>;
 780                         tsens_caldata: caldata@d0 {
 781                                 reg = <0xd0 0x8>;
 782                         };
 783                         tsens_calsel: calsel@ec {
 784                                 reg = <0xec 0x4>;
 785                         };
 786                 };
 787
 788                 tsens: thermal-sensor@4a8000 {
 789                         compatible = "qcom,msm8916-tsens";
 790                         reg = <0x4a8000 0x2000>;
 791                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 792                         nvmem-cell-names = "calib", "calib_sel";
 793                         qcom,tsens-slopes = <3200 3200 3200 3200 3200>;
 794                         qcom,sensor-id = <0 1 2 4 5>;
 795                         #thermal-sensor-cells = <1>;
 796                 };
 797
 798                 q6-smp2p {
 799                         compatible = "qcom,smp2p";
 800                         qcom,smem = <435>, <428>;
 801                         interrupts = <0 27 1>;
 802                         qcom,ipc = <&apcs 8 14>;
 803
 804                         qcom,local-pid = <0>;
 805                         qcom,remote-pid = <1>;
 806
 807                         q6_smp2p_out: master-kernel {
 808                                 qcom,entry-name = "master-kernel";
 809                                 qcom,outbound;
 810
 811                                 gpio-controller;
 812                                 #gpio-cells = <2>;
 813                         };
 814
 815                         q6_smp2p_in: slave-kernel {
 816                                 qcom,entry-name = "slave-kernel";
 817                                 qcom,inbound;
 818
 819                                 interrupt-controller;
 820                                 #interrupt-cells = <2>;
 821                         };
 822                 };
 823
 824                 wcnss-smp2p {
 825                         compatible = "qcom,smp2p";
 826                         qcom,smem = <451>, <431>;
 827
 828                         interrupts = <0 143 1>;
 829
 830                         qcom,ipc = <&apcs 8 18>;
 831
 832                         qcom,local-pid = <0>;
 833                         qcom,remote-pid = <4>;
 834
 835                         wcnss_smp2p_out: master-kernel {
 836                                 qcom,entry-name = "master-kernel";
 837                                 qcom,outbound;
 838
 839                                 gpio-controller;
 840                                 #gpio-cells = <2>;
 841                         };
 842
 843                         wcnss_smp2p_in: slave-kernel {
 844                                 qcom,entry-name = "slave-kernel";
 845                                 qcom,inbound;
 846
 847                                 interrupt-controller;
 848                                 #interrupt-cells = <2>;
 849                         };
 850                 };
 851
 852                 hexagon@4080000 {
 853                         compatible = "qcom,pil-q6v56-mss", "qcom,q6v5-pil";
 854                         reg = <0x04080000 0x100>,
 855                               <0x04020000 0x040>,
 856                               <0x01810000 0x004>,
 857                               <0x0194f000 0x010>,
 858                               <0x01950000 0x008>,
 859                               <0x01951000 0x008>;
 860
 861                         reg-names = "qdsp6_base", "rmb_base", "restart_reg_sec",
 862                                         "halt_base", "halt_modem", "halt_nc";
 863
 864                         interrupts-extended = <&intc 0 24 1>,
 865                                               <&hexagon_smp2p_in 0 0>,
 866                                               <&hexagon_smp2p_in 1 0>,
 867                                               <&hexagon_smp2p_in 2 0>,
 868                                               <&hexagon_smp2p_in 3 0>;
 869                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 870
 871                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>;
 872                         clock-names = "iface", "bus", "mem";
 873
 874                         qcom,state = <&hexagon_smp2p_out 0>;
 875                         qcom,state-names = "stop";
 876
 877                         resets = <&scm 0>;
 878                         reset-names = "mss_restart";
 879
 880                         mba {
 881                                 memory-region = <&mba_mem>;
 882                         };
 883
 884                         mpss {
 885                                 memory-region = <&modem_adsp_mem>;
 886                         };
 887                 };
 888
 889                 pronto: wcnss@a21b000 {
 890                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
 891                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
 892                         reg-names = "ccu", "dxe", "pmu";
 893
 894                         memory-region = <&wcnss_mem>;
 895
 896                         interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
 897                                 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 898                                 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 899                                 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 900                                 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 901                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 902
 903                         vddmx-supply = <&pm8916_l3>;
 904                         vddpx-supply = <&pm8916_l7>;
 905
 906                         qcom,state = <&wcnss_smp2p_out 0>;
 907                         qcom,state-names = "stop";
 908
 909                         pinctrl-names = "default";
 910                         pinctrl-0 = <&wcnss_default>;
 911
 912                         iris {
 913                                 compatible = "qcom,wcn3620";
 914
 915                                 clocks = <&rpmcc RPM_RF_CLK2>;
 916                                 clock-names = "xo";
 917
 918                                 vddxo-supply = <&pm8916_l7>;
 919                                 vddrfa-supply = <&pm8916_s3>;
 920                                 vddpa-supply = <&pm8916_l9>;
 921                                 vdddig-supply = <&pm8916_l5>;
 922                         };
 923                 };
 924
 925                 qcom,rpm-log@29dc00 {
 926                         compatible = "qcom,rpm-log";
 927                         reg = <0x29dc00 0x4000>;
 928                         qcom,rpm-addr-phys = <0x200000>;
 929                         qcom,offset-version = <4>;
 930                         qcom,offset-page-buffer-addr = <36>;
 931                         qcom,offset-log-len = <40>;
 932                         qcom,offset-log-len-mask = <44>;
 933                         qcom,offset-page-indices = <56>;
 934                 };
 935
 936                 vidc_rproc: vidc_tzpil@0 {
 937                         compatible = "qcom,tz-pil";
 938                         clocks = <&gcc GCC_CRYPTO_CLK>,
 939                                  <&gcc GCC_CRYPTO_AHB_CLK>,
 940                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 941                                  <&gcc CRYPTO_CLK_SRC>;
 942                         clock-names = "scm_core_clk", "scm_iface_clk",
 943                                       "scm_bus_clk", "scm_src_clk";
 944                         qcom,firmware-name = "venus";
 945                         qcom,pas-id = <9>;
 946                         memory-region = <&vidc_mem>;
 947                         status = "disabled";
 948                 };
 949
 950                 vidc: qcom,vidc@1d00000 {
 951                         compatible = "qcom,msm-vidc";
 952                         reg = <0x01d00000 0xff000>;
 953                         interrupts = <GIC_SPI 44 0>;
 954                         power-domains = <&gcc VENUS_GDSC>;
 955                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
 956                                  <&gcc GCC_VENUS0_AHB_CLK>,
 957                                  <&gcc GCC_VENUS0_AXI_CLK>;
 958                         clock-names = "core_clk", "iface_clk", "bus_clk";
 959                         qcom,hfi = "venus";
 960                         qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */
 961                         qcom,enable-idle-indicator;
 962                         rproc = <&vidc_rproc>;
 963                         qcom,iommu-cb = <&venus_ns>,
 964                                         <&venus_sec_bitstream>,
 965                                         <&venus_sec_pixel>,
 966                                         <&venus_sec_non_pixel>;
 967                         status = "disabled";
 968                 };
 969         };
 970
 971         smem {
 972                 compatible = "qcom,smem";
 973
 974                 memory-region = <&smem_mem>;
 975                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 976
 977                 hwlocks = <&tcsr_mutex 3>;
 978         };
 979         smd {
 980                 compatible = "qcom,smd";
 981
 982                 rpm {
 983                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 984                         qcom,ipc = <&apcs 8 0>;
 985                         qcom,smd-edge = <15>;
 986                         qcom,remote-pid = <0xffffffff>;
 987
 988                         rpm_requests {
 989                                 compatible = "qcom,rpm-msm8916";
 990                                 qcom,smd-channels = "rpm_requests";
 991                                 rpmcc: qcom,rpmcc {
 992                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
 993                                         #clock-cells = <1>;
 994                                 };
 995
 996                                 msm-bus {
 997                                                 compatible = "qcom,rpm-msm-bus";
 998                                 };
 999                                 pm8916-regulators {
1000                                         compatible = "qcom,rpm-pm8916-regulators";
1001
1002                                         pm8916_s1: s1 {};
1003                                         pm8916_s2: s2 {};
1004                                         pm8916_s3: s3 {};
1005                                         pm8916_s4: s4 {};
1006
1007                                         pm8916_l1: l1 {};
1008                                         pm8916_l2: l2 {};
1009                                         pm8916_l3: l3 {};
1010                                         pm8916_l4: l4 {};
1011                                         pm8916_l5: l5 {};
1012                                         pm8916_l6: l6 {};
1013                                         pm8916_l7: l7 {};
1014                                         pm8916_l8: l8 {};
1015                                         pm8916_l9: l9 {};
1016                                         pm8916_l10: l10 {};
1017                                         pm8916_l11: l11 {};
1018                                         pm8916_l12: l12 {};
1019                                         pm8916_l13: l13 {};
1020                                         pm8916_l14: l14 {};
1021                                         pm8916_l15: l15 {};
1022                                         pm8916_l16: l16 {};
1023                                         pm8916_l17: l17 {};
1024                                         pm8916_l18: l18 {};
1025                                 };
1026                         };
1027                 };
1028
1029                 qcom,smd-modem {
1030                         interrupts = <0 25 1>;
1031                         qcom,smd-edge = <0>;
1032                         qcom,ipc = <&apcs 8 12>;
1033                         qcom,remote-pid = <1>;
1034                         ipcrtr_requests {
1035                                 compatible = "qcom,ipcrtr";
1036                                 qcom,smd-channels = "IPCRTR";
1037                         };
1038                 };
1039
1040                 pronto {
1041                         interrupts = <0 142 1>;
1042
1043                         qcom,ipc = <&apcs 8 17>;
1044                         qcom,smd-edge = <6>;
1045                         qcom,remote-pid = <4>;
1046
1047                         wcnss {
1048                                 compatible = "qcom,wcnss";
1049                                 qcom,smd-channels = "WCNSS_CTRL";
1050
1051                                 qcom,mmio = <&pronto>;
1052
1053                                 bt {
1054                                         compatible = "qcom,btqcomsmd";
1055                                 };
1056
1057                                 wifi {
1058                                         compatible = "qcom,wcnss-wlan";
1059
1060                                         interrupts = <0 145 0>, <0 146 0>;
1061                                         interrupt-names = "tx", "rx";
1062
1063                                         qcom,state = <&apps_smsm 10>, <&apps_smsm 9>;
1064                                         qcom,state-names = "tx-enable", "tx-rings-empty";
1065                                 };
1066                         };
1067                 };
1068         };
1069
1070         hexagon-smp2p {
1071                 compatible = "qcom,smp2p";
1072                 qcom,smem = <435>, <428>;
1073
1074                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1075
1076                 qcom,ipc = <&apcs 8 14>;
1077
1078                 qcom,local-pid = <0>;
1079                 qcom,remote-pid = <1>;
1080
1081                 hexagon_smp2p_out: master-kernel {
1082                         qcom,entry-name = "master-kernel";
1083
1084                         #qcom,state-cells = <1>;
1085                 };
1086
1087                 hexagon_smp2p_in: slave-kernel {
1088                         qcom,entry-name = "slave-kernel";
1089
1090                         interrupt-controller;
1091                         #interrupt-cells = <2>;
1092                 };
1093         };
1094
1095         wcnss-smp2p {
1096                 compatible = "qcom,smp2p";
1097                 qcom,smem = <451>, <431>;
1098
1099                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1100
1101                 qcom,ipc = <&apcs 8 18>;
1102
1103                 qcom,local-pid = <0>;
1104                 qcom,remote-pid = <4>;
1105
1106                 wcnss_smp2p_out: master-kernel {
1107                         qcom,entry-name = "master-kernel";
1108
1109                         #qcom,state-cells = <1>;
1110                 };
1111
1112                 wcnss_smp2p_in: slave-kernel {
1113                         qcom,entry-name = "slave-kernel";
1114
1115                         interrupt-controller;
1116                         #interrupt-cells = <2>;
1117                 };
1118         };
1119
1120         smsm {
1121                 compatible = "qcom,smsm";
1122
1123                 #address-cells = <1>;
1124                 #size-cells = <0>;
1125
1126                 qcom,ipc-1 = <&apcs 0 13>;
1127                 qcom,ipc-6 = <&apcs 0 19>;
1128
1129                 apps_smsm: apps@0 {
1130                         reg = <0>;
1131
1132                         #qcom,state-cells = <1>;
1133                 };
1134
1135                 hexagon_smsm: hexagon@1 {
1136                         reg = <1>;
1137                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1138
1139                         interrupt-controller;
1140                         #interrupt-cells = <2>;
1141                 };
1142
1143                 wcnss_smsm: wcnss@6 {
1144                         reg = <6>;
1145                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1146
1147                         interrupt-controller;
1148                         #interrupt-cells = <2>;
1149                 };
1150         };
1151 };
1152
1153 #include "msm8916-pins.dtsi"
1154 #include "msm8916-iommu.dtsi"
1155 #include "msm8916-coresight.dtsi"
1156 #include "msm8916-bus.dtsi"