2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
19 model = "Qualcomm Technologies, Inc. MSM8916";
20 compatible = "qcom,msm8916";
22 interrupt-parent = <&intc>;
28 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
29 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
35 device_type = "memory";
36 /* We expect the bootloader to fill in the reg */
45 reserve_aligned@86000000 {
46 reg = <0x0 0x86000000 0x0 0x0300000>;
50 smem_mem: smem_region@86300000 {
51 reg = <0x0 0x86300000 0x0 0x0100000>;
62 compatible = "arm,cortex-a53", "arm,armv8";
64 next-level-cache = <&L2_0>;
69 compatible = "arm,cortex-a53", "arm,armv8";
71 next-level-cache = <&L2_0>;
76 compatible = "arm,cortex-a53", "arm,armv8";
78 next-level-cache = <&L2_0>;
83 compatible = "arm,cortex-a53", "arm,armv8";
85 next-level-cache = <&L2_0>;
95 compatible = "arm,armv8-timer";
96 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
97 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
98 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
104 compatible = "fixed-clock";
106 clock-frequency = <19200000>;
109 sleep_clk: sleep_clk {
110 compatible = "fixed-clock";
112 clock-frequency = <32768>;
117 compatible = "qcom,smem";
119 memory-region = <&smem_mem>;
120 qcom,rpm-msg-ram = <&rpm_msg_ram>;
122 hwlocks = <&tcsr_mutex 3>;
126 #address-cells = <1>;
128 ranges = <0 0 0 0xffffffff>;
129 compatible = "simple-bus";
132 compatible = "qcom,pshold";
133 reg = <0x4ab000 0x4>;
136 msmgpio: pinctrl@1000000 {
137 compatible = "qcom,msm8916-pinctrl";
138 reg = <0x1000000 0x300000>;
139 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
146 gcc: clock-controller@1800000 {
147 compatible = "qcom,gcc-msm8916";
150 #power-domain-cells = <1>;
151 reg = <0x1800000 0x80000>;
154 tcsr_mutex_regs: syscon@1905000 {
155 compatible = "syscon";
156 reg = <0x1905000 0x20000>;
160 compatible = "qcom,tcsr-mutex";
161 syscon = <&tcsr_mutex_regs 0 0x1000>;
165 rpm_msg_ram: memory@60000 {
166 compatible = "qcom,rpm-msg-ram";
167 reg = <0x60000 0x8000>;
170 blsp1_uart1: serial@78af000 {
171 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
172 reg = <0x78af000 0x200>;
173 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
175 clock-names = "core", "iface";
176 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
177 dma-names = "rx", "tx";
181 apcs: syscon@b011000 {
182 compatible = "syscon";
183 reg = <0x0b011000 0x1000>;
186 blsp1_uart2: serial@78b0000 {
187 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
188 reg = <0x78b0000 0x200>;
189 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
191 clock-names = "core", "iface";
192 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
193 dma-names = "rx", "tx";
197 blsp_dma: dma@7884000 {
198 compatible = "qcom,bam-v1.7.0";
199 reg = <0x07884000 0x23000>;
200 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
202 clock-names = "bam_clk";
208 blsp_spi1: spi@78b5000 {
209 compatible = "qcom,spi-qup-v2.2.1";
210 reg = <0x078b5000 0x600>;
211 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
213 <&gcc GCC_BLSP1_AHB_CLK>;
214 clock-names = "core", "iface";
215 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
216 dma-names = "rx", "tx";
217 pinctrl-names = "default", "sleep";
218 pinctrl-0 = <&spi1_default>;
219 pinctrl-1 = <&spi1_sleep>;
220 #address-cells = <1>;
225 blsp_spi2: spi@78b6000 {
226 compatible = "qcom,spi-qup-v2.2.1";
227 reg = <0x078b6000 0x600>;
228 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
230 <&gcc GCC_BLSP1_AHB_CLK>;
231 clock-names = "core", "iface";
232 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
233 dma-names = "rx", "tx";
234 pinctrl-names = "default", "sleep";
235 pinctrl-0 = <&spi2_default>;
236 pinctrl-1 = <&spi2_sleep>;
237 #address-cells = <1>;
242 blsp_spi3: spi@78b7000 {
243 compatible = "qcom,spi-qup-v2.2.1";
244 reg = <0x078b7000 0x600>;
245 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
247 <&gcc GCC_BLSP1_AHB_CLK>;
248 clock-names = "core", "iface";
249 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
250 dma-names = "rx", "tx";
251 pinctrl-names = "default", "sleep";
252 pinctrl-0 = <&spi3_default>;
253 pinctrl-1 = <&spi3_sleep>;
254 #address-cells = <1>;
259 blsp_spi4: spi@78b8000 {
260 compatible = "qcom,spi-qup-v2.2.1";
261 reg = <0x078b8000 0x600>;
262 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
264 <&gcc GCC_BLSP1_AHB_CLK>;
265 clock-names = "core", "iface";
266 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
267 dma-names = "rx", "tx";
268 pinctrl-names = "default", "sleep";
269 pinctrl-0 = <&spi4_default>;
270 pinctrl-1 = <&spi4_sleep>;
271 #address-cells = <1>;
276 blsp_spi5: spi@78b9000 {
277 compatible = "qcom,spi-qup-v2.2.1";
278 reg = <0x078b9000 0x600>;
279 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
281 <&gcc GCC_BLSP1_AHB_CLK>;
282 clock-names = "core", "iface";
283 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
284 dma-names = "rx", "tx";
285 pinctrl-names = "default", "sleep";
286 pinctrl-0 = <&spi5_default>;
287 pinctrl-1 = <&spi5_sleep>;
288 #address-cells = <1>;
293 blsp_spi6: spi@78ba000 {
294 compatible = "qcom,spi-qup-v2.2.1";
295 reg = <0x078ba000 0x600>;
296 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
298 <&gcc GCC_BLSP1_AHB_CLK>;
299 clock-names = "core", "iface";
300 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
301 dma-names = "rx", "tx";
302 pinctrl-names = "default", "sleep";
303 pinctrl-0 = <&spi6_default>;
304 pinctrl-1 = <&spi6_sleep>;
305 #address-cells = <1>;
310 blsp_i2c2: i2c@78b6000 {
311 compatible = "qcom,i2c-qup-v2.2.1";
312 reg = <0x78b6000 0x1000>;
313 interrupts = <GIC_SPI 96 0>;
314 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
315 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
316 clock-names = "iface", "core";
317 pinctrl-names = "default", "sleep";
318 pinctrl-0 = <&i2c2_default>;
319 pinctrl-1 = <&i2c2_sleep>;
320 #address-cells = <1>;
325 blsp_i2c4: i2c@78b8000 {
326 compatible = "qcom,i2c-qup-v2.2.1";
327 reg = <0x78b8000 0x1000>;
328 interrupts = <GIC_SPI 98 0>;
329 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
330 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
331 clock-names = "iface", "core";
332 pinctrl-names = "default", "sleep";
333 pinctrl-0 = <&i2c4_default>;
334 pinctrl-1 = <&i2c4_sleep>;
335 #address-cells = <1>;
340 blsp_i2c6: i2c@78ba000 {
341 compatible = "qcom,i2c-qup-v2.2.1";
342 reg = <0x78ba000 0x1000>;
343 interrupts = <GIC_SPI 100 0>;
344 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
345 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
346 clock-names = "iface", "core";
347 pinctrl-names = "default", "sleep";
348 pinctrl-0 = <&i2c6_default>;
349 pinctrl-1 = <&i2c6_sleep>;
350 #address-cells = <1>;
355 sdhc_1: sdhci@07824000 {
356 compatible = "qcom,sdhci-msm-v4";
357 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
358 reg-names = "hc_mem", "core_mem";
360 interrupts = <0 123 0>, <0 138 0>;
361 interrupt-names = "hc_irq", "pwr_irq";
362 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
363 <&gcc GCC_SDCC1_AHB_CLK>;
364 clock-names = "core", "iface";
370 sdhc_2: sdhci@07864000 {
371 compatible = "qcom,sdhci-msm-v4";
372 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
373 reg-names = "hc_mem", "core_mem";
375 interrupts = <0 125 0>, <0 221 0>;
376 interrupt-names = "hc_irq", "pwr_irq";
377 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
378 <&gcc GCC_SDCC2_AHB_CLK>;
379 clock-names = "core", "iface";
384 usb_dev: usb@78d9000 {
385 compatible = "qcom,ci-hdrc";
386 reg = <0x78d9000 0x400>;
387 dr_mode = "peripheral";
388 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
389 usb-phy = <&usb_otg>;
393 usb_host: ehci@78d9000 {
394 compatible = "qcom,ehci-host";
395 reg = <0x78d9000 0x400>;
396 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
397 usb-phy = <&usb_otg>;
401 usb_otg: phy@78d9000 {
402 compatible = "qcom,usb-otg-snps";
403 reg = <0x78d9000 0x400>;
404 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
405 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
407 qcom,vdd-levels = <1 5 7>;
408 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
409 dr_mode = "peripheral";
410 qcom,otg-control = <2>; // PMIC
412 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
413 <&gcc GCC_USB_HS_SYSTEM_CLK>,
414 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
415 clock-names = "iface", "core", "sleep";
417 resets = <&gcc GCC_USB2A_PHY_BCR>,
418 <&gcc GCC_USB_HS_BCR>;
419 reset-names = "phy", "link";
423 intc: interrupt-controller@b000000 {
424 compatible = "qcom,msm-qgic2";
425 interrupt-controller;
426 #interrupt-cells = <3>;
427 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
431 #address-cells = <1>;
434 compatible = "arm,armv7-timer-mem";
435 reg = <0xb020000 0x1000>;
436 clock-frequency = <19200000>;
440 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
442 reg = <0xb021000 0x1000>,
448 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
449 reg = <0xb023000 0x1000>;
455 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
456 reg = <0xb024000 0x1000>;
462 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
463 reg = <0xb025000 0x1000>;
469 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
470 reg = <0xb026000 0x1000>;
476 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
477 reg = <0xb027000 0x1000>;
483 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
484 reg = <0xb028000 0x1000>;
489 spmi_bus: spmi@200f000 {
490 compatible = "qcom,spmi-pmic-arb";
491 reg = <0x200f000 0x001000>,
492 <0x2400000 0x400000>,
493 <0x2c00000 0x400000>,
494 <0x3800000 0x200000>,
495 <0x200a000 0x002100>;
496 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
497 interrupt-names = "periph_irq";
498 interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
501 #address-cells = <2>;
503 interrupt-controller;
504 #interrupt-cells = <4>;
508 compatible = "qcom,prng";
509 reg = <0x00022000 0x200>;
510 clocks = <&gcc GCC_PRNG_AHB_CLK>;
511 clock-names = "core";
516 compatible = "qcom,smd";
519 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
520 qcom,ipc = <&apcs 8 0>;
521 qcom,smd-edge = <15>;
524 compatible = "qcom,rpm-msm8916";
525 qcom,smd-channels = "rpm_requests";
528 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
532 smd_rpm_regulators: pm8916-regulators {
533 compatible = "qcom,rpm-pm8916-regulators";
563 #include "msm8916-pins.dtsi"