arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8916";
  20         compatible = "qcom,msm8916";
  21
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  29                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  30         };
  31
  32         chosen { };
  33
  34         memory {
  35                 device_type = "memory";
  36                 /* We expect the bootloader to fill in the reg */
  37                 reg = <0 0 0 0>;
  38         };
  39
  40         reserved-memory {
  41                 #address-cells = <2>;
  42                 #size-cells = <2>;
  43                 ranges;
  44
  45                 reserve_aligned@86000000 {
  46                         reg = <0x0 0x86000000 0x0 0x0300000>;
  47                         no-map;
  48                 };
  49
  50                 smem_mem: smem_region@86300000 {
  51                         reg = <0x0 0x86300000 0x0 0x0100000>;
  52                         no-map;
  53                 };
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 CPU0: cpu@0 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53", "arm,armv8";
  63                         reg = <0x0>;
  64                 };
  65
  66                 CPU1: cpu@1 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a53", "arm,armv8";
  69                         reg = <0x1>;
  70                 };
  71
  72                 CPU2: cpu@2 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x2>;
  76                 };
  77
  78                 CPU3: cpu@3 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53", "arm,armv8";
  81                         reg = <0x3>;
  82                 };
  83         };
  84
  85         timer {
  86                 compatible = "arm,armv8-timer";
  87                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  88                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  91         };
  92
  93         clocks {
  94                 xo_board: xo_board {
  95                         compatible = "fixed-clock";
  96                         #clock-cells = <0>;
  97                         clock-frequency = <19200000>;
  98                 };
  99
 100                 sleep_clk: sleep_clk {
 101                         compatible = "fixed-clock";
 102                         #clock-cells = <0>;
 103                         clock-frequency = <32768>;
 104                 };
 105         };
 106
 107         smem {
 108                 compatible = "qcom,smem";
 109
 110                 memory-region = <&smem_mem>;
 111                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 112
 113                 hwlocks = <&tcsr_mutex 3>;
 114         };
 115
 116         soc: soc {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 ranges = <0 0 0 0xffffffff>;
 120                 compatible = "simple-bus";
 121
 122                 restart@4ab000 {
 123                         compatible = "qcom,pshold";
 124                         reg = <0x4ab000 0x4>;
 125                 };
 126
 127                 msmgpio: pinctrl@1000000 {
 128                         compatible = "qcom,msm8916-pinctrl";
 129                         reg = <0x1000000 0x300000>;
 130                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 131                         gpio-controller;
 132                         #gpio-cells = <2>;
 133                         interrupt-controller;
 134                         #interrupt-cells = <2>;
 135                 };
 136
 137                 gcc: qcom,gcc@1800000 {
 138                         compatible = "qcom,gcc-msm8916";
 139                         #clock-cells = <1>;
 140                         #reset-cells = <1>;
 141                         #power-domain-cells = <1>;
 142                         reg = <0x1800000 0x80000>;
 143                 };
 144
 145                 tcsr_mutex_regs: syscon@1905000 {
 146                         compatible = "syscon";
 147                         reg = <0x1905000 0x20000>;
 148                 };
 149
 150                 tcsr_mutex: hwlock {
 151                         compatible = "qcom,tcsr-mutex";
 152                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 153                         #hwlock-cells = <1>;
 154                 };
 155
 156                 rpm_msg_ram: memory@60000 {
 157                         compatible = "qcom,rpm-msg-ram";
 158                         reg = <0x60000 0x8000>;
 159                 };
 160
 161                 blsp1_uart1: serial@78af000 {
 162                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 163                         reg = <0x78af000 0x200>;
 164                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 165                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 166                         clock-names = "core", "iface";
 167                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 168                         dma-names = "rx", "tx";
 169                         status = "disabled";
 170                 };
 171
 172                 apcs: syscon@b011000 {
 173                         compatible = "syscon";
 174                         reg = <0x0b011000 0x1000>;
 175                 };
 176
 177                 blsp1_uart2: serial@78b0000 {
 178                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 179                         reg = <0x78b0000 0x200>;
 180                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 181                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 182                         clock-names = "core", "iface";
 183                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 184                         dma-names = "rx", "tx";
 185                         status = "disabled";
 186                 };
 187
 188                 blsp_dma: dma@7884000 {
 189                         compatible = "qcom,bam-v1.7.0";
 190                         reg = <0x07884000 0x23000>;
 191                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 192                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 193                         clock-names = "bam_clk";
 194                         #dma-cells = <1>;
 195                         qcom,ee = <0>;
 196                         status = "disabled";
 197                 };
 198
 199                 blsp_spi1: spi@78b5000 {
 200                         compatible = "qcom,spi-qup-v2.2.1";
 201                         reg = <0x078b5000 0x600>;
 202                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 203                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 204                                  <&gcc GCC_BLSP1_AHB_CLK>;
 205                         clock-names = "core", "iface";
 206                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 207                         dma-names = "rx", "tx";
 208                         pinctrl-names = "default", "sleep";
 209                         pinctrl-0 = <&spi1_default>;
 210                         pinctrl-1 = <&spi1_sleep>;
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                         status = "disabled";
 214                 };
 215
 216                 blsp_spi2: spi@78b6000 {
 217                         compatible = "qcom,spi-qup-v2.2.1";
 218                         reg = <0x078b6000 0x600>;
 219                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 220                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 221                                  <&gcc GCC_BLSP1_AHB_CLK>;
 222                         clock-names = "core", "iface";
 223                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 224                         dma-names = "rx", "tx";
 225                         pinctrl-names = "default", "sleep";
 226                         pinctrl-0 = <&spi2_default>;
 227                         pinctrl-1 = <&spi2_sleep>;
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         status = "disabled";
 231                 };
 232
 233                 blsp_spi3: spi@78b7000 {
 234                         compatible = "qcom,spi-qup-v2.2.1";
 235                         reg = <0x078b7000 0x600>;
 236                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 237                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 238                                  <&gcc GCC_BLSP1_AHB_CLK>;
 239                         clock-names = "core", "iface";
 240                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 241                         dma-names = "rx", "tx";
 242                         pinctrl-names = "default", "sleep";
 243                         pinctrl-0 = <&spi3_default>;
 244                         pinctrl-1 = <&spi3_sleep>;
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         status = "disabled";
 248                 };
 249
 250                 blsp_spi4: spi@78b8000 {
 251                         compatible = "qcom,spi-qup-v2.2.1";
 252                         reg = <0x078b8000 0x600>;
 253                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 254                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 255                                  <&gcc GCC_BLSP1_AHB_CLK>;
 256                         clock-names = "core", "iface";
 257                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 258                         dma-names = "rx", "tx";
 259                         pinctrl-names = "default", "sleep";
 260                         pinctrl-0 = <&spi4_default>;
 261                         pinctrl-1 = <&spi4_sleep>;
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         status = "disabled";
 265                 };
 266
 267                 blsp_spi5: spi@78b9000 {
 268                         compatible = "qcom,spi-qup-v2.2.1";
 269                         reg = <0x078b9000 0x600>;
 270                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 271                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 272                                  <&gcc GCC_BLSP1_AHB_CLK>;
 273                         clock-names = "core", "iface";
 274                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 275                         dma-names = "rx", "tx";
 276                         pinctrl-names = "default", "sleep";
 277                         pinctrl-0 = <&spi5_default>;
 278                         pinctrl-1 = <&spi5_sleep>;
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         status = "disabled";
 282                 };
 283
 284                 blsp_spi6: spi@78ba000 {
 285                         compatible = "qcom,spi-qup-v2.2.1";
 286                         reg = <0x078ba000 0x600>;
 287                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 289                                  <&gcc GCC_BLSP1_AHB_CLK>;
 290                         clock-names = "core", "iface";
 291                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 292                         dma-names = "rx", "tx";
 293                         pinctrl-names = "default", "sleep";
 294                         pinctrl-0 = <&spi6_default>;
 295                         pinctrl-1 = <&spi6_sleep>;
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298                         status = "disabled";
 299                 };
 300
 301                 blsp_i2c2: i2c@78b6000 {
 302                         compatible = "qcom,i2c-qup-v2.2.1";
 303                         reg = <0x78b6000 0x1000>;
 304                         interrupts = <GIC_SPI 96 0>;
 305                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 306                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 307                         clock-names = "iface", "core";
 308                         pinctrl-names = "default", "sleep";
 309                         pinctrl-0 = <&i2c2_default>;
 310                         pinctrl-1 = <&i2c2_sleep>;
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         status = "disabled";
 314                 };
 315
 316                 blsp_i2c4: i2c@78b8000 {
 317                         compatible = "qcom,i2c-qup-v2.2.1";
 318                         reg = <0x78b8000 0x1000>;
 319                         interrupts = <GIC_SPI 98 0>;
 320                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 321                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 322                         clock-names = "iface", "core";
 323                         pinctrl-names = "default", "sleep";
 324                         pinctrl-0 = <&i2c4_default>;
 325                         pinctrl-1 = <&i2c4_sleep>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         status = "disabled";
 329                 };
 330
 331                 blsp_i2c6: i2c@78ba000 {
 332                         compatible = "qcom,i2c-qup-v2.2.1";
 333                         reg = <0x78ba000 0x1000>;
 334                         interrupts = <GIC_SPI 100 0>;
 335                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 336                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 337                         clock-names = "iface", "core";
 338                         pinctrl-names = "default", "sleep";
 339                         pinctrl-0 = <&i2c6_default>;
 340                         pinctrl-1 = <&i2c6_sleep>;
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                         status = "disabled";
 344                 };
 345
 346                 sdhc_1: sdhci@07824000 {
 347                         compatible = "qcom,sdhci-msm-v4";
 348                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 349                         reg-names = "hc_mem", "core_mem";
 350
 351                         interrupts = <0 123 0>, <0 138 0>;
 352                         interrupt-names = "hc_irq", "pwr_irq";
 353                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 354                                  <&gcc GCC_SDCC1_AHB_CLK>;
 355                         clock-names = "core", "iface";
 356                         bus-width = <8>;
 357                         non-removable;
 358                         status = "disabled";
 359                 };
 360
 361                 sdhc_2: sdhci@07864000 {
 362                         compatible = "qcom,sdhci-msm-v4";
 363                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 364                         reg-names = "hc_mem", "core_mem";
 365
 366                         interrupts = <0 125 0>, <0 221 0>;
 367                         interrupt-names = "hc_irq", "pwr_irq";
 368                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 369                                  <&gcc GCC_SDCC2_AHB_CLK>;
 370                         clock-names = "core", "iface";
 371                         bus-width = <4>;
 372                         status = "disabled";
 373                 };
 374
 375                 usb_dev: usb@78d9000 {
 376                         compatible = "qcom,ci-hdrc";
 377                         reg = <0x78d9000 0x400>;
 378                         dr_mode = "peripheral";
 379                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 380                         usb-phy = <&usb_otg>;
 381                         status = "disabled";
 382                 };
 383
 384                 usb_host: ehci@78d9000 {
 385                         compatible = "qcom,ehci-host";
 386                         reg = <0x78d9000 0x400>;
 387                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 388                         usb-phy = <&usb_otg>;
 389                         status = "disabled";
 390                 };
 391
 392                 usb_otg: phy@78d9000 {
 393                         compatible = "qcom,usb-otg-snps";
 394                         reg = <0x78d9000 0x400>;
 395                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 396                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 397
 398                         qcom,vdd-levels = <1 5 7>;
 399                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 400                         dr_mode = "peripheral";
 401                         qcom,otg-control = <2>; // PMIC
 402
 403                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 404                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 405                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 406                         clock-names = "iface", "core", "sleep";
 407
 408                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 409                                  <&gcc GCC_USB_HS_BCR>;
 410                         reset-names = "phy", "link";
 411                         status = "disabled";
 412                 };
 413
 414                 intc: interrupt-controller@b000000 {
 415                         compatible = "qcom,msm-qgic2";
 416                         interrupt-controller;
 417                         #interrupt-cells = <3>;
 418                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 419                 };
 420
 421                 timer@b020000 {
 422                         #address-cells = <1>;
 423                         #size-cells = <1>;
 424                         ranges;
 425                         compatible = "arm,armv7-timer-mem";
 426                         reg = <0xb020000 0x1000>;
 427                         clock-frequency = <19200000>;
 428
 429                         frame@b021000 {
 430                                 frame-number = <0>;
 431                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 432                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 433                                 reg = <0xb021000 0x1000>,
 434                                       <0xb022000 0x1000>;
 435                         };
 436
 437                         frame@b023000 {
 438                                 frame-number = <1>;
 439                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 440                                 reg = <0xb023000 0x1000>;
 441                                 status = "disabled";
 442                         };
 443
 444                         frame@b024000 {
 445                                 frame-number = <2>;
 446                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 447                                 reg = <0xb024000 0x1000>;
 448                                 status = "disabled";
 449                         };
 450
 451                         frame@b025000 {
 452                                 frame-number = <3>;
 453                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 454                                 reg = <0xb025000 0x1000>;
 455                                 status = "disabled";
 456                         };
 457
 458                         frame@b026000 {
 459                                 frame-number = <4>;
 460                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 461                                 reg = <0xb026000 0x1000>;
 462                                 status = "disabled";
 463                         };
 464
 465                         frame@b027000 {
 466                                 frame-number = <5>;
 467                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 468                                 reg = <0xb027000 0x1000>;
 469                                 status = "disabled";
 470                         };
 471
 472                         frame@b028000 {
 473                                 frame-number = <6>;
 474                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 475                                 reg = <0xb028000 0x1000>;
 476                                 status = "disabled";
 477                         };
 478                 };
 479
 480                 spmi_bus: spmi@200f000 {
 481                         compatible = "qcom,spmi-pmic-arb";
 482                         reg = <0x200f000 0x001000>,
 483                               <0x2400000 0x400000>,
 484                               <0x2c00000 0x400000>,
 485                               <0x3800000 0x200000>,
 486                               <0x200a000 0x002100>;
 487                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 488                         interrupt-names = "periph_irq";
 489                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 490                         qcom,ee = <0>;
 491                         qcom,channel = <0>;
 492                         #address-cells = <2>;
 493                         #size-cells = <0>;
 494                         interrupt-controller;
 495                         #interrupt-cells = <4>;
 496                 };
 497
 498                 rng@22000 {
 499                         compatible = "qcom,prng";
 500                         reg = <0x00022000 0x200>;
 501                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 502                         clock-names = "core";
 503                 };
 504         };
 505
 506         smd {
 507                 compatible = "qcom,smd";
 508
 509                 rpm {
 510                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 511                         qcom,ipc = <&apcs 8 0>;
 512                         qcom,smd-edge = <15>;
 513
 514                         rpm_requests {
 515                                 compatible = "qcom,rpm-msm8916";
 516                                 qcom,smd-channels = "rpm_requests";
 517
 518                                 pm8916-regulators {
 519                                         compatible = "qcom,rpm-pm8916-regulators";
 520
 521                                         pm8916_s1: s1 {};
 522                                         pm8916_s2: s2 {};
 523                                         pm8916_s3: s3 {};
 524                                         pm8916_s4: s4 {};
 525
 526                                         pm8916_l1: l1 {};
 527                                         pm8916_l2: l2 {};
 528                                         pm8916_l3: l3 {};
 529                                         pm8916_l4: l4 {};
 530                                         pm8916_l5: l5 {};
 531                                         pm8916_l6: l6 {};
 532                                         pm8916_l7: l7 {};
 533                                         pm8916_l8: l8 {};
 534                                         pm8916_l9: l9 {};
 535                                         pm8916_l10: l10 {};
 536                                         pm8916_l11: l11 {};
 537                                         pm8916_l12: l12 {};
 538                                         pm8916_l13: l13 {};
 539                                         pm8916_l14: l14 {};
 540                                         pm8916_l15: l15 {};
 541                                         pm8916_l16: l16 {};
 542                                         pm8916_l17: l17 {};
 543                                         pm8916_l18: l18 {};
 544                                 };
 545                         };
 546                 };
 547         };
 548 };
 549
 550 #include "msm8916-pins.dtsi"