2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
19 model = "Qualcomm Technologies, Inc. MSM8916";
20 compatible = "qcom,msm8916";
22 interrupt-parent = <&intc>;
28 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
29 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
35 device_type = "memory";
36 /* We expect the bootloader to fill in the reg */
45 reserve_aligned@86000000 {
46 reg = <0x0 0x86000000 0x0 0x0300000>;
50 smem_mem: smem_region@86300000 {
51 reg = <0x0 0x86300000 0x0 0x0100000>;
62 compatible = "arm,cortex-a53", "arm,armv8";
68 compatible = "arm,cortex-a53", "arm,armv8";
74 compatible = "arm,cortex-a53", "arm,armv8";
80 compatible = "arm,cortex-a53", "arm,armv8";
86 compatible = "arm,armv8-timer";
87 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
95 compatible = "fixed-clock";
97 clock-frequency = <19200000>;
100 sleep_clk: sleep_clk {
101 compatible = "fixed-clock";
103 clock-frequency = <32768>;
108 compatible = "qcom,smem";
110 memory-region = <&smem_mem>;
111 qcom,rpm-msg-ram = <&rpm_msg_ram>;
113 hwlocks = <&tcsr_mutex 3>;
117 #address-cells = <1>;
119 ranges = <0 0 0 0xffffffff>;
120 compatible = "simple-bus";
123 compatible = "qcom,pshold";
124 reg = <0x4ab000 0x4>;
127 msmgpio: pinctrl@1000000 {
128 compatible = "qcom,msm8916-pinctrl";
129 reg = <0x1000000 0x300000>;
130 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
137 gcc: qcom,gcc@1800000 {
138 compatible = "qcom,gcc-msm8916";
141 #power-domain-cells = <1>;
142 reg = <0x1800000 0x80000>;
145 tcsr_mutex_regs: syscon@1905000 {
146 compatible = "syscon";
147 reg = <0x1905000 0x20000>;
151 compatible = "qcom,tcsr-mutex";
152 syscon = <&tcsr_mutex_regs 0 0x1000>;
156 rpm_msg_ram: memory@60000 {
157 compatible = "qcom,rpm-msg-ram";
158 reg = <0x60000 0x8000>;
161 blsp1_uart1: serial@78af000 {
162 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
163 reg = <0x78af000 0x200>;
164 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
166 clock-names = "core", "iface";
167 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
168 dma-names = "rx", "tx";
172 apcs: syscon@b011000 {
173 compatible = "syscon";
174 reg = <0x0b011000 0x1000>;
177 blsp1_uart2: serial@78b0000 {
178 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
179 reg = <0x78b0000 0x200>;
180 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
182 clock-names = "core", "iface";
183 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
184 dma-names = "rx", "tx";
188 blsp_dma: dma@7884000 {
189 compatible = "qcom,bam-v1.7.0";
190 reg = <0x07884000 0x23000>;
191 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
193 clock-names = "bam_clk";
199 blsp_spi1: spi@78b5000 {
200 compatible = "qcom,spi-qup-v2.2.1";
201 reg = <0x078b5000 0x600>;
202 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
204 <&gcc GCC_BLSP1_AHB_CLK>;
205 clock-names = "core", "iface";
206 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
207 dma-names = "rx", "tx";
208 pinctrl-names = "default", "sleep";
209 pinctrl-0 = <&spi1_default>;
210 pinctrl-1 = <&spi1_sleep>;
211 #address-cells = <1>;
216 blsp_spi2: spi@78b6000 {
217 compatible = "qcom,spi-qup-v2.2.1";
218 reg = <0x078b6000 0x600>;
219 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
221 <&gcc GCC_BLSP1_AHB_CLK>;
222 clock-names = "core", "iface";
223 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
224 dma-names = "rx", "tx";
225 pinctrl-names = "default", "sleep";
226 pinctrl-0 = <&spi2_default>;
227 pinctrl-1 = <&spi2_sleep>;
228 #address-cells = <1>;
233 blsp_spi3: spi@78b7000 {
234 compatible = "qcom,spi-qup-v2.2.1";
235 reg = <0x078b7000 0x600>;
236 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
238 <&gcc GCC_BLSP1_AHB_CLK>;
239 clock-names = "core", "iface";
240 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
241 dma-names = "rx", "tx";
242 pinctrl-names = "default", "sleep";
243 pinctrl-0 = <&spi3_default>;
244 pinctrl-1 = <&spi3_sleep>;
245 #address-cells = <1>;
250 blsp_spi4: spi@78b8000 {
251 compatible = "qcom,spi-qup-v2.2.1";
252 reg = <0x078b8000 0x600>;
253 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
255 <&gcc GCC_BLSP1_AHB_CLK>;
256 clock-names = "core", "iface";
257 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
258 dma-names = "rx", "tx";
259 pinctrl-names = "default", "sleep";
260 pinctrl-0 = <&spi4_default>;
261 pinctrl-1 = <&spi4_sleep>;
262 #address-cells = <1>;
267 blsp_spi5: spi@78b9000 {
268 compatible = "qcom,spi-qup-v2.2.1";
269 reg = <0x078b9000 0x600>;
270 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
272 <&gcc GCC_BLSP1_AHB_CLK>;
273 clock-names = "core", "iface";
274 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
275 dma-names = "rx", "tx";
276 pinctrl-names = "default", "sleep";
277 pinctrl-0 = <&spi5_default>;
278 pinctrl-1 = <&spi5_sleep>;
279 #address-cells = <1>;
284 blsp_spi6: spi@78ba000 {
285 compatible = "qcom,spi-qup-v2.2.1";
286 reg = <0x078ba000 0x600>;
287 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
289 <&gcc GCC_BLSP1_AHB_CLK>;
290 clock-names = "core", "iface";
291 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
292 dma-names = "rx", "tx";
293 pinctrl-names = "default", "sleep";
294 pinctrl-0 = <&spi6_default>;
295 pinctrl-1 = <&spi6_sleep>;
296 #address-cells = <1>;
301 blsp_i2c2: i2c@78b6000 {
302 compatible = "qcom,i2c-qup-v2.2.1";
303 reg = <0x78b6000 0x1000>;
304 interrupts = <GIC_SPI 96 0>;
305 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
306 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
307 clock-names = "iface", "core";
308 pinctrl-names = "default", "sleep";
309 pinctrl-0 = <&i2c2_default>;
310 pinctrl-1 = <&i2c2_sleep>;
311 #address-cells = <1>;
316 blsp_i2c4: i2c@78b8000 {
317 compatible = "qcom,i2c-qup-v2.2.1";
318 reg = <0x78b8000 0x1000>;
319 interrupts = <GIC_SPI 98 0>;
320 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
321 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
322 clock-names = "iface", "core";
323 pinctrl-names = "default", "sleep";
324 pinctrl-0 = <&i2c4_default>;
325 pinctrl-1 = <&i2c4_sleep>;
326 #address-cells = <1>;
331 blsp_i2c6: i2c@78ba000 {
332 compatible = "qcom,i2c-qup-v2.2.1";
333 reg = <0x78ba000 0x1000>;
334 interrupts = <GIC_SPI 100 0>;
335 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
336 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
337 clock-names = "iface", "core";
338 pinctrl-names = "default", "sleep";
339 pinctrl-0 = <&i2c6_default>;
340 pinctrl-1 = <&i2c6_sleep>;
341 #address-cells = <1>;
346 sdhc_1: sdhci@07824000 {
347 compatible = "qcom,sdhci-msm-v4";
348 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
349 reg-names = "hc_mem", "core_mem";
351 interrupts = <0 123 0>, <0 138 0>;
352 interrupt-names = "hc_irq", "pwr_irq";
353 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
354 <&gcc GCC_SDCC1_AHB_CLK>;
355 clock-names = "core", "iface";
361 sdhc_2: sdhci@07864000 {
362 compatible = "qcom,sdhci-msm-v4";
363 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
364 reg-names = "hc_mem", "core_mem";
366 interrupts = <0 125 0>, <0 221 0>;
367 interrupt-names = "hc_irq", "pwr_irq";
368 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
369 <&gcc GCC_SDCC2_AHB_CLK>;
370 clock-names = "core", "iface";
375 usb_dev: usb@78d9000 {
376 compatible = "qcom,ci-hdrc";
377 reg = <0x78d9000 0x400>;
378 dr_mode = "peripheral";
379 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
380 usb-phy = <&usb_otg>;
384 usb_host: ehci@78d9000 {
385 compatible = "qcom,ehci-host";
386 reg = <0x78d9000 0x400>;
387 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
388 usb-phy = <&usb_otg>;
392 usb_otg: phy@78d9000 {
393 compatible = "qcom,usb-otg-snps";
394 reg = <0x78d9000 0x400>;
395 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
396 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
398 qcom,vdd-levels = <1 5 7>;
399 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
400 dr_mode = "peripheral";
401 qcom,otg-control = <2>; // PMIC
403 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
404 <&gcc GCC_USB_HS_SYSTEM_CLK>,
405 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
406 clock-names = "iface", "core", "sleep";
408 resets = <&gcc GCC_USB2A_PHY_BCR>,
409 <&gcc GCC_USB_HS_BCR>;
410 reset-names = "phy", "link";
414 intc: interrupt-controller@b000000 {
415 compatible = "qcom,msm-qgic2";
416 interrupt-controller;
417 #interrupt-cells = <3>;
418 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
422 #address-cells = <1>;
425 compatible = "arm,armv7-timer-mem";
426 reg = <0xb020000 0x1000>;
427 clock-frequency = <19200000>;
431 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
433 reg = <0xb021000 0x1000>,
439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
440 reg = <0xb023000 0x1000>;
446 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
447 reg = <0xb024000 0x1000>;
453 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
454 reg = <0xb025000 0x1000>;
460 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
461 reg = <0xb026000 0x1000>;
467 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
468 reg = <0xb027000 0x1000>;
474 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
475 reg = <0xb028000 0x1000>;
480 spmi_bus: spmi@200f000 {
481 compatible = "qcom,spmi-pmic-arb";
482 reg = <0x200f000 0x001000>,
483 <0x2400000 0x400000>,
484 <0x2c00000 0x400000>,
485 <0x3800000 0x200000>,
486 <0x200a000 0x002100>;
487 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
488 interrupt-names = "periph_irq";
489 interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
492 #address-cells = <2>;
494 interrupt-controller;
495 #interrupt-cells = <4>;
499 compatible = "qcom,prng";
500 reg = <0x00022000 0x200>;
501 clocks = <&gcc GCC_PRNG_AHB_CLK>;
502 clock-names = "core";
507 compatible = "qcom,smd";
510 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
511 qcom,ipc = <&apcs 8 0>;
512 qcom,smd-edge = <15>;
515 compatible = "qcom,rpm-msm8916";
516 qcom,smd-channels = "rpm_requests";
519 compatible = "qcom,rpm-pm8916-regulators";
550 #include "msm8916-pins.dtsi"