arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8916";
  20         compatible = "qcom,msm8916";
  21
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  29                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  30         };
  31
  32         chosen { };
  33
  34         memory {
  35                 device_type = "memory";
  36                 /* We expect the bootloader to fill in the reg */
  37                 reg = <0 0 0 0>;
  38         };
  39
  40         reserved-memory {
  41                 #address-cells = <2>;
  42                 #size-cells = <2>;
  43                 ranges;
  44
  45                 tz-apps@86000000 {
  46                         reg = <0x0 0x86000000 0x0 0x300000>;
  47                         no-map;
  48                 };
  49
  50                 smem_mem: smem_region@86300000 {
  51                         reg = <0x0 0x86300000 0x0 0x100000>;
  52                         no-map;
  53                 };
  54
  55                 hypervisor@86400000 {
  56                         reg = <0x0 0x86400000 0x0 0x100000>;
  57                         no-map;
  58                 };
  59
  60                 tz@86500000 {
  61                         reg = <0x0 0x86500000 0x0 0x180000>;
  62                         no-map;
  63                 };
  64
  65                 reserved@8668000 {
  66                         reg = <0x0 0x86680000 0x0 0x80000>;
  67                         no-map;
  68                 };
  69
  70                 rmtfs@86700000 {
  71                         reg = <0x0 0x86700000 0x0 0xe0000>;
  72                         no-map;
  73                 };
  74
  75                 rfsa@867e00000 {
  76                         reg = <0x0 0x867e0000 0x0 0x20000>;
  77                         no-map;
  78                 };
  79
  80                 mpss_mem: mpss@86800000 {
  81                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  82                         no-map;
  83                 };
  84
  85                 wcnss@89300000 {
  86                         reg = <0x0 0x89300000 0x0 0x600000>;
  87                         no-map;
  88                 };
  89
  90                 mba_mem: mba@8ea00000 {
  91                         no-map;
  92                         reg = <0 0x8ea00000 0 0x100000>;
  93                 };
  94         };
  95
  96         cpus {
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 CPU0: cpu@0 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0>;
 104                         next-level-cache = <&L2_0>;
 105                         enable-method = "psci";
 106                         cpu-idle-states = <&CPU_SPC>;
 107                 };
 108
 109                 CPU1: cpu@1 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x1>;
 113                         next-level-cache = <&L2_0>;
 114                         enable-method = "psci";
 115                         cpu-idle-states = <&CPU_SPC>;
 116                 };
 117
 118                 CPU2: cpu@2 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a53", "arm,armv8";
 121                         reg = <0x2>;
 122                         next-level-cache = <&L2_0>;
 123                         enable-method = "psci";
 124                         cpu-idle-states = <&CPU_SPC>;
 125                 };
 126
 127                 CPU3: cpu@3 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x3>;
 131                         next-level-cache = <&L2_0>;
 132                         enable-method = "psci";
 133                         cpu-idle-states = <&CPU_SPC>;
 134                 };
 135
 136                 L2_0: l2-cache {
 137                       compatible = "cache";
 138                       cache-level = <2>;
 139                 };
 140
 141                 idle-states {
 142                         CPU_SPC: spc {
 143                                 compatible = "arm,idle-state";
 144                                 arm,psci-suspend-param = <0x40000002>;
 145                                 entry-latency-us = <130>;
 146                                 exit-latency-us = <150>;
 147                                 min-residency-us = <2000>;
 148                                 local-timer-stop;
 149                         };
 150                 };
 151         };
 152
 153         psci {
 154                 compatible = "arm,psci-1.0";
 155                 method = "smc";
 156         };
 157
 158         pmu {
 159                 compatible = "arm,armv8-pmuv3";
 160                 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
 161         };
 162
 163         thermal-zones {
 164                 cpu-thermal0 {
 165                         polling-delay-passive = <250>;
 166                         polling-delay = <1000>;
 167
 168                         thermal-sensors = <&tsens 4>;
 169
 170                         trips {
 171                                 cpu_alert0: trip0 {
 172                                         temperature = <75000>;
 173                                         hysteresis = <2000>;
 174                                         type = "passive";
 175                                 };
 176                                 cpu_crit0: trip1 {
 177                                         temperature = <110000>;
 178                                         hysteresis = <2000>;
 179                                         type = "critical";
 180                                 };
 181                         };
 182                 };
 183
 184                 cpu-thermal1 {
 185                         polling-delay-passive = <250>;
 186                         polling-delay = <1000>;
 187
 188                         thermal-sensors = <&tsens 3>;
 189
 190                         trips {
 191                                 cpu_alert1: trip0 {
 192                                         temperature = <75000>;
 193                                         hysteresis = <2000>;
 194                                         type = "passive";
 195                                 };
 196                                 cpu_crit1: trip1 {
 197                                         temperature = <110000>;
 198                                         hysteresis = <2000>;
 199                                         type = "critical";
 200                                 };
 201                         };
 202                 };
 203
 204         };
 205
 206         timer {
 207                 compatible = "arm,armv8-timer";
 208                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 211                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 212         };
 213
 214         clocks {
 215                 xo_board: xo_board {
 216                         compatible = "fixed-clock";
 217                         #clock-cells = <0>;
 218                         clock-frequency = <19200000>;
 219                 };
 220
 221                 sleep_clk: sleep_clk {
 222                         compatible = "fixed-clock";
 223                         #clock-cells = <0>;
 224                         clock-frequency = <32768>;
 225                 };
 226         };
 227
 228         smem {
 229                 compatible = "qcom,smem";
 230
 231                 memory-region = <&smem_mem>;
 232                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 233
 234                 hwlocks = <&tcsr_mutex 3>;
 235         };
 236
 237         firmware {
 238                 scm: scm {
 239                         compatible = "qcom,scm";
 240                         clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 241                         clock-names = "core", "bus", "iface";
 242                         #reset-cells = <1>;
 243                 };
 244         };
 245
 246         soc: soc {
 247                 #address-cells = <1>;
 248                 #size-cells = <1>;
 249                 ranges = <0 0 0 0xffffffff>;
 250                 compatible = "simple-bus";
 251
 252                 restart@4ab000 {
 253                         compatible = "qcom,pshold";
 254                         reg = <0x4ab000 0x4>;
 255                 };
 256
 257                 msmgpio: pinctrl@1000000 {
 258                         compatible = "qcom,msm8916-pinctrl";
 259                         reg = <0x1000000 0x300000>;
 260                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 261                         gpio-controller;
 262                         #gpio-cells = <2>;
 263                         interrupt-controller;
 264                         #interrupt-cells = <2>;
 265                 };
 266
 267                 gcc: clock-controller@1800000 {
 268                         compatible = "qcom,gcc-msm8916";
 269                         #clock-cells = <1>;
 270                         #reset-cells = <1>;
 271                         #power-domain-cells = <1>;
 272                         reg = <0x1800000 0x80000>;
 273                 };
 274
 275                 tcsr_mutex_regs: syscon@1905000 {
 276                         compatible = "syscon";
 277                         reg = <0x1905000 0x20000>;
 278                 };
 279
 280                 tcsr: syscon@1937000 {
 281                         compatible = "qcom,tcsr-msm8916", "syscon";
 282                         reg = <0x1937000 0x30000>;
 283                 };
 284
 285                 tcsr_mutex: hwlock {
 286                         compatible = "qcom,tcsr-mutex";
 287                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 288                         #hwlock-cells = <1>;
 289                 };
 290
 291                 rpm_msg_ram: memory@60000 {
 292                         compatible = "qcom,rpm-msg-ram";
 293                         reg = <0x60000 0x8000>;
 294                 };
 295
 296                 blsp1_uart1: serial@78af000 {
 297                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 298                         reg = <0x78af000 0x200>;
 299                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 300                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 301                         clock-names = "core", "iface";
 302                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 303                         dma-names = "rx", "tx";
 304                         status = "disabled";
 305                 };
 306
 307                 apcs: syscon@b011000 {
 308                         compatible = "syscon";
 309                         reg = <0x0b011000 0x1000>;
 310                 };
 311
 312                 blsp1_uart2: serial@78b0000 {
 313                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 314                         reg = <0x78b0000 0x200>;
 315                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 316                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 317                         clock-names = "core", "iface";
 318                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 319                         dma-names = "rx", "tx";
 320                         status = "disabled";
 321                 };
 322
 323                 blsp_dma: dma@7884000 {
 324                         compatible = "qcom,bam-v1.7.0";
 325                         reg = <0x07884000 0x23000>;
 326                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 327                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 328                         clock-names = "bam_clk";
 329                         #dma-cells = <1>;
 330                         qcom,ee = <0>;
 331                         status = "disabled";
 332                 };
 333
 334                 blsp_spi1: spi@78b5000 {
 335                         compatible = "qcom,spi-qup-v2.2.1";
 336                         reg = <0x078b5000 0x600>;
 337                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 338                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 339                                  <&gcc GCC_BLSP1_AHB_CLK>;
 340                         clock-names = "core", "iface";
 341                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 342                         dma-names = "rx", "tx";
 343                         pinctrl-names = "default", "sleep";
 344                         pinctrl-0 = <&spi1_default>;
 345                         pinctrl-1 = <&spi1_sleep>;
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         status = "disabled";
 349                 };
 350
 351                 blsp_spi2: spi@78b6000 {
 352                         compatible = "qcom,spi-qup-v2.2.1";
 353                         reg = <0x078b6000 0x600>;
 354                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 356                                  <&gcc GCC_BLSP1_AHB_CLK>;
 357                         clock-names = "core", "iface";
 358                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 359                         dma-names = "rx", "tx";
 360                         pinctrl-names = "default", "sleep";
 361                         pinctrl-0 = <&spi2_default>;
 362                         pinctrl-1 = <&spi2_sleep>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         status = "disabled";
 366                 };
 367
 368                 blsp_spi3: spi@78b7000 {
 369                         compatible = "qcom,spi-qup-v2.2.1";
 370                         reg = <0x078b7000 0x600>;
 371                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 373                                  <&gcc GCC_BLSP1_AHB_CLK>;
 374                         clock-names = "core", "iface";
 375                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 376                         dma-names = "rx", "tx";
 377                         pinctrl-names = "default", "sleep";
 378                         pinctrl-0 = <&spi3_default>;
 379                         pinctrl-1 = <&spi3_sleep>;
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         status = "disabled";
 383                 };
 384
 385                 blsp_spi4: spi@78b8000 {
 386                         compatible = "qcom,spi-qup-v2.2.1";
 387                         reg = <0x078b8000 0x600>;
 388                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 389                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 390                                  <&gcc GCC_BLSP1_AHB_CLK>;
 391                         clock-names = "core", "iface";
 392                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 393                         dma-names = "rx", "tx";
 394                         pinctrl-names = "default", "sleep";
 395                         pinctrl-0 = <&spi4_default>;
 396                         pinctrl-1 = <&spi4_sleep>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         status = "disabled";
 400                 };
 401
 402                 blsp_spi5: spi@78b9000 {
 403                         compatible = "qcom,spi-qup-v2.2.1";
 404                         reg = <0x078b9000 0x600>;
 405                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 406                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 407                                  <&gcc GCC_BLSP1_AHB_CLK>;
 408                         clock-names = "core", "iface";
 409                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 410                         dma-names = "rx", "tx";
 411                         pinctrl-names = "default", "sleep";
 412                         pinctrl-0 = <&spi5_default>;
 413                         pinctrl-1 = <&spi5_sleep>;
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         status = "disabled";
 417                 };
 418
 419                 blsp_spi6: spi@78ba000 {
 420                         compatible = "qcom,spi-qup-v2.2.1";
 421                         reg = <0x078ba000 0x600>;
 422                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 424                                  <&gcc GCC_BLSP1_AHB_CLK>;
 425                         clock-names = "core", "iface";
 426                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 427                         dma-names = "rx", "tx";
 428                         pinctrl-names = "default", "sleep";
 429                         pinctrl-0 = <&spi6_default>;
 430                         pinctrl-1 = <&spi6_sleep>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         status = "disabled";
 434                 };
 435
 436                 blsp_i2c2: i2c@78b6000 {
 437                         compatible = "qcom,i2c-qup-v2.2.1";
 438                         reg = <0x78b6000 0x1000>;
 439                         interrupts = <GIC_SPI 96 0>;
 440                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 441                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 442                         clock-names = "iface", "core";
 443                         pinctrl-names = "default", "sleep";
 444                         pinctrl-0 = <&i2c2_default>;
 445                         pinctrl-1 = <&i2c2_sleep>;
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         status = "disabled";
 449                 };
 450
 451                 blsp_i2c4: i2c@78b8000 {
 452                         compatible = "qcom,i2c-qup-v2.2.1";
 453                         reg = <0x78b8000 0x1000>;
 454                         interrupts = <GIC_SPI 98 0>;
 455                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 456                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 457                         clock-names = "iface", "core";
 458                         pinctrl-names = "default", "sleep";
 459                         pinctrl-0 = <&i2c4_default>;
 460                         pinctrl-1 = <&i2c4_sleep>;
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         status = "disabled";
 464                 };
 465
 466                 blsp_i2c6: i2c@78ba000 {
 467                         compatible = "qcom,i2c-qup-v2.2.1";
 468                         reg = <0x78ba000 0x1000>;
 469                         interrupts = <GIC_SPI 100 0>;
 470                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 471                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 472                         clock-names = "iface", "core";
 473                         pinctrl-names = "default", "sleep";
 474                         pinctrl-0 = <&i2c6_default>;
 475                         pinctrl-1 = <&i2c6_sleep>;
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         status = "disabled";
 479                 };
 480
 481                 lpass: lpass@07708000 {
 482                         status = "disabled";
 483                         compatible = "qcom,lpass-cpu-apq8016";
 484                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 485                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 486                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 487                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 488                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 489                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 490                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 491
 492                         clock-names = "ahbix-clk",
 493                                         "pcnoc-mport-clk",
 494                                         "pcnoc-sway-clk",
 495                                         "mi2s-bit-clk0",
 496                                         "mi2s-bit-clk1",
 497                                         "mi2s-bit-clk2",
 498                                         "mi2s-bit-clk3";
 499                         #sound-dai-cells = <1>;
 500
 501                         interrupts = <0 160 0>;
 502                         interrupt-names = "lpass-irq-lpaif";
 503                         reg = <0x07708000 0x10000>;
 504                         reg-names = "lpass-lpaif";
 505                 };
 506
 507                 lpass_codec: codec{
 508                         compatible = "qcom,msm8916-wcd-digital-codec";
 509                         reg = <0x0771c000 0x400>;
 510                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 511                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
 512                         clock-names = "ahbix-clk", "mclk";
 513                         #sound-dai-cells = <1>;
 514                 };
 515
 516                 sdhc_1: sdhci@07824000 {
 517                         compatible = "qcom,sdhci-msm-v4";
 518                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 519                         reg-names = "hc_mem", "core_mem";
 520
 521                         interrupts = <0 123 0>, <0 138 0>;
 522                         interrupt-names = "hc_irq", "pwr_irq";
 523                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 524                                  <&gcc GCC_SDCC1_AHB_CLK>,
 525                                  <&xo_board>;
 526                         clock-names = "core", "iface", "xo";
 527                         mmc-ddr-1_8v;
 528                         bus-width = <8>;
 529                         non-removable;
 530                         status = "disabled";
 531                 };
 532
 533                 sdhc_2: sdhci@07864000 {
 534                         compatible = "qcom,sdhci-msm-v4";
 535                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 536                         reg-names = "hc_mem", "core_mem";
 537
 538                         interrupts = <0 125 0>, <0 221 0>;
 539                         interrupt-names = "hc_irq", "pwr_irq";
 540                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 541                                  <&gcc GCC_SDCC2_AHB_CLK>,
 542                                  <&xo_board>;
 543                         clock-names = "core", "iface", "xo";
 544                         bus-width = <4>;
 545                         status = "disabled";
 546                 };
 547
 548                 usb_dev: usb@78d9000 {
 549                         compatible = "qcom,ci-hdrc";
 550                         reg = <0x78d9000 0x400>;
 551                         dr_mode = "peripheral";
 552                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 553                         usb-phy = <&usb_otg>;
 554                         status = "disabled";
 555                 };
 556
 557                 usb_host: ehci@78d9000 {
 558                         compatible = "qcom,ehci-host";
 559                         reg = <0x78d9000 0x400>;
 560                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 561                         usb-phy = <&usb_otg>;
 562                         status = "disabled";
 563                 };
 564
 565                 usb_otg: phy@78d9000 {
 566                         compatible = "qcom,usb-otg-snps";
 567                         reg = <0x78d9000 0x400>;
 568                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 569                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 570
 571                         qcom,vdd-levels = <500000 1000000 1320000>;
 572                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 573                         dr_mode = "peripheral";
 574                         qcom,otg-control = <2>; // PMIC
 575                         qcom,manual-pullup;
 576
 577                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 578                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 579                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 580                         clock-names = "iface", "core", "sleep";
 581
 582                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 583                                  <&gcc GCC_USB_HS_BCR>;
 584                         reset-names = "phy", "link";
 585                         status = "disabled";
 586                 };
 587
 588                 intc: interrupt-controller@b000000 {
 589                         compatible = "qcom,msm-qgic2";
 590                         interrupt-controller;
 591                         #interrupt-cells = <3>;
 592                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 593                 };
 594
 595                 timer@b020000 {
 596                         #address-cells = <1>;
 597                         #size-cells = <1>;
 598                         ranges;
 599                         compatible = "arm,armv7-timer-mem";
 600                         reg = <0xb020000 0x1000>;
 601                         clock-frequency = <19200000>;
 602
 603                         frame@b021000 {
 604                                 frame-number = <0>;
 605                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 606                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 607                                 reg = <0xb021000 0x1000>,
 608                                       <0xb022000 0x1000>;
 609                         };
 610
 611                         frame@b023000 {
 612                                 frame-number = <1>;
 613                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 614                                 reg = <0xb023000 0x1000>;
 615                                 status = "disabled";
 616                         };
 617
 618                         frame@b024000 {
 619                                 frame-number = <2>;
 620                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 621                                 reg = <0xb024000 0x1000>;
 622                                 status = "disabled";
 623                         };
 624
 625                         frame@b025000 {
 626                                 frame-number = <3>;
 627                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 628                                 reg = <0xb025000 0x1000>;
 629                                 status = "disabled";
 630                         };
 631
 632                         frame@b026000 {
 633                                 frame-number = <4>;
 634                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 635                                 reg = <0xb026000 0x1000>;
 636                                 status = "disabled";
 637                         };
 638
 639                         frame@b027000 {
 640                                 frame-number = <5>;
 641                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 642                                 reg = <0xb027000 0x1000>;
 643                                 status = "disabled";
 644                         };
 645
 646                         frame@b028000 {
 647                                 frame-number = <6>;
 648                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 649                                 reg = <0xb028000 0x1000>;
 650                                 status = "disabled";
 651                         };
 652                 };
 653
 654                 spmi_bus: spmi@200f000 {
 655                         compatible = "qcom,spmi-pmic-arb";
 656                         reg = <0x200f000 0x001000>,
 657                               <0x2400000 0x400000>,
 658                               <0x2c00000 0x400000>,
 659                               <0x3800000 0x200000>,
 660                               <0x200a000 0x002100>;
 661                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 662                         interrupt-names = "periph_irq";
 663                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 664                         qcom,ee = <0>;
 665                         qcom,channel = <0>;
 666                         #address-cells = <2>;
 667                         #size-cells = <0>;
 668                         interrupt-controller;
 669                         #interrupt-cells = <4>;
 670                 };
 671
 672                 rng@22000 {
 673                         compatible = "qcom,prng";
 674                         reg = <0x00022000 0x200>;
 675                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 676                         clock-names = "core";
 677                 };
 678
 679                 qfprom: qfprom@5c000 {
 680                         compatible = "qcom,qfprom";
 681                         reg = <0x5c000 0x1000>;
 682                         #address-cells = <1>;
 683                         #size-cells = <1>;
 684                         tsens_caldata: caldata@d0 {
 685                                 reg = <0xd0 0x8>;
 686                         };
 687                         tsens_calsel: calsel@ec {
 688                                 reg = <0xec 0x4>;
 689                         };
 690                 };
 691
 692                 tsens: thermal-sensor@4a8000 {
 693                         compatible = "qcom,msm8916-tsens";
 694                         reg = <0x4a8000 0x2000>;
 695                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 696                         nvmem-cell-names = "calib", "calib_sel";
 697                         #thermal-sensor-cells = <1>;
 698                 };
 699
 700                 mdss: mdss@1a00000 {
 701                         compatible = "qcom,mdss";
 702                         reg = <0x1a00000 0x1000>,
 703                               <0x1ac8000 0x3000>;
 704                         reg-names = "mdss_phys", "vbif_phys";
 705
 706                         power-domains = <&gcc MDSS_GDSC>;
 707
 708                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
 709                                  <&gcc GCC_MDSS_AXI_CLK>,
 710                                  <&gcc GCC_MDSS_VSYNC_CLK>;
 711                         clock-names = "iface_clk",
 712                                       "bus_clk",
 713                                       "vsync_clk";
 714
 715                         interrupts = <0 72 0>;
 716
 717                         interrupt-controller;
 718                         #interrupt-cells = <1>;
 719
 720                         #address-cells = <1>;
 721                         #size-cells = <1>;
 722                         ranges;
 723
 724                         mdp: mdp@1a01000 {
 725                                 compatible = "qcom,mdp5";
 726                                 reg = <0x1a01000 0x90000>;
 727                                 reg-names = "mdp_phys";
 728
 729                                 interrupt-parent = <&mdss>;
 730                                 interrupts = <0 0>;
 731
 732                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
 733                                          <&gcc GCC_MDSS_AXI_CLK>,
 734                                          <&gcc GCC_MDSS_MDP_CLK>,
 735                                          <&gcc GCC_MDSS_VSYNC_CLK>;
 736                                 clock-names = "iface_clk",
 737                                               "bus_clk",
 738                                               "core_clk",
 739                                               "vsync_clk";
 740
 741                                 ports {
 742                                         #address-cells = <1>;
 743                                         #size-cells = <0>;
 744
 745                                         port@0 {
 746                                                 reg = <0>;
 747                                                 mdp5_intf1_out: endpoint {
 748                                                         remote-endpoint = <&dsi0_in>;
 749                                                 };
 750                                         };
 751                                 };
 752                         };
 753
 754                         dsi0: dsi@1a98000 {
 755                                 compatible = "qcom,mdss-dsi-ctrl";
 756                                 reg = <0x1a98000 0x25c>;
 757                                 reg-names = "dsi_ctrl";
 758
 759                                 interrupt-parent = <&mdss>;
 760                                 interrupts = <4 0>;
 761
 762                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
 763                                                   <&gcc PCLK0_CLK_SRC>;
 764                                 assigned-clock-parents = <&dsi_phy0 0>,
 765                                                          <&dsi_phy0 1>;
 766
 767                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
 768                                          <&gcc GCC_MDSS_AHB_CLK>,
 769                                          <&gcc GCC_MDSS_AXI_CLK>,
 770                                          <&gcc GCC_MDSS_BYTE0_CLK>,
 771                                          <&gcc GCC_MDSS_PCLK0_CLK>,
 772                                          <&gcc GCC_MDSS_ESC0_CLK>;
 773                                 clock-names = "mdp_core_clk",
 774                                               "iface_clk",
 775                                               "bus_clk",
 776                                               "byte_clk",
 777                                               "pixel_clk",
 778                                               "core_clk";
 779                                 phys = <&dsi_phy0>;
 780                                 phy-names = "dsi-phy";
 781
 782                                 ports {
 783                                         #address-cells = <1>;
 784                                         #size-cells = <0>;
 785
 786                                         port@0 {
 787                                                 reg = <0>;
 788                                                 dsi0_in: endpoint {
 789                                                         remote-endpoint = <&mdp5_intf1_out>;
 790                                                 };
 791                                         };
 792
 793                                         port@1 {
 794                                                 reg = <1>;
 795                                                 dsi0_out: endpoint {
 796                                                 };
 797                                         };
 798                                 };
 799                         };
 800
 801                         dsi_phy0: dsi-phy@1a98300 {
 802                                 compatible = "qcom,dsi-phy-28nm-lp";
 803                                 reg = <0x1a98300 0xd4>,
 804                                       <0x1a98500 0x280>,
 805                                       <0x1a98780 0x30>;
 806                                 reg-names = "dsi_pll",
 807                                             "dsi_phy",
 808                                             "dsi_phy_regulator";
 809
 810                                 #clock-cells = <1>;
 811
 812                                 clocks = <&gcc GCC_MDSS_AHB_CLK>;
 813                                 clock-names = "iface_clk";
 814                         };
 815                 };
 816
 817
 818                 hexagon@4080000 {
 819                         compatible = "qcom,q6v5-pil";
 820                         reg = <0x04080000 0x100>,
 821                               <0x04020000 0x040>;
 822
 823                         reg-names = "qdsp6", "rmb";
 824
 825                         interrupts-extended = <&intc 0 24 1>,
 826                                               <&hexagon_smp2p_in 0 0>,
 827                                               <&hexagon_smp2p_in 1 0>,
 828                                               <&hexagon_smp2p_in 2 0>,
 829                                               <&hexagon_smp2p_in 3 0>;
 830                         interrupt-names = "wdog", "fatal", "ready",
 831                                           "handover", "stop-ack";
 832
 833                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
 834                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
 835                                  <&gcc GCC_BOOT_ROM_AHB_CLK>;
 836                         clock-names = "iface", "bus", "mem";
 837
 838                         qcom,smem-states = <&hexagon_smp2p_out 0>;
 839                         qcom,smem-state-names = "stop";
 840
 841                         resets = <&scm 0>;
 842                         reset-names = "mss_restart";
 843
 844                         mx-supply = <&pm8916_l3>;
 845                         pll-supply = <&pm8916_l7>;
 846
 847                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
 848
 849                         status = "disabled";
 850
 851                         mba {
 852                                 memory-region = <&mba_mem>;
 853                         };
 854
 855                         mpss {
 856                                 memory-region = <&mpss_mem>;
 857                         };
 858                 };
 859         };
 860
 861         smd {
 862                 compatible = "qcom,smd";
 863
 864                 rpm {
 865                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 866                         qcom,ipc = <&apcs 8 0>;
 867                         qcom,smd-edge = <15>;
 868
 869                         rpm_requests {
 870                                 compatible = "qcom,rpm-msm8916";
 871                                 qcom,smd-channels = "rpm_requests";
 872
 873                                 rpmcc: qcom,rpmcc {
 874                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
 875                                         #clock-cells = <1>;
 876                                 };
 877
 878                                 smd_rpm_regulators: pm8916-regulators {
 879                                         compatible = "qcom,rpm-pm8916-regulators";
 880
 881                                         pm8916_s1: s1 {};
 882                                         pm8916_s3: s3 {};
 883                                         pm8916_s4: s4 {};
 884
 885                                         pm8916_l1: l1 {};
 886                                         pm8916_l2: l2 {};
 887                                         pm8916_l3: l3 {};
 888                                         pm8916_l4: l4 {};
 889                                         pm8916_l5: l5 {};
 890                                         pm8916_l6: l6 {};
 891                                         pm8916_l7: l7 {};
 892                                         pm8916_l8: l8 {};
 893                                         pm8916_l9: l9 {};
 894                                         pm8916_l10: l10 {};
 895                                         pm8916_l11: l11 {};
 896                                         pm8916_l12: l12 {};
 897                                         pm8916_l13: l13 {};
 898                                         pm8916_l14: l14 {};
 899                                         pm8916_l15: l15 {};
 900                                         pm8916_l16: l16 {};
 901                                         pm8916_l17: l17 {};
 902                                         pm8916_l18: l18 {};
 903                                 };
 904                         };
 905                 };
 906
 907                 hexagon {
 908                         interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
 909
 910                         qcom,smd-edge = <0>;
 911                         qcom,ipc = <&apcs 8 12>;
 912                         qcom,remote-pid = <1>;
 913                 };
 914         };
 915
 916         hexagon-smp2p {
 917                 compatible = "qcom,smp2p";
 918                 qcom,smem = <435>, <428>;
 919
 920                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
 921
 922                 qcom,ipc = <&apcs 8 14>;
 923
 924                 qcom,local-pid = <0>;
 925                 qcom,remote-pid = <1>;
 926
 927                 hexagon_smp2p_out: master-kernel {
 928                         qcom,entry-name = "master-kernel";
 929
 930                         #qcom,smem-state-cells = <1>;
 931                 };
 932
 933                 hexagon_smp2p_in: slave-kernel {
 934                         qcom,entry-name = "slave-kernel";
 935
 936                         interrupt-controller;
 937                         #interrupt-cells = <2>;
 938                 };
 939         };
 940
 941         wcnss-smp2p {
 942                 compatible = "qcom,smp2p";
 943                 qcom,smem = <451>, <431>;
 944
 945                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 946
 947                 qcom,ipc = <&apcs 8 18>;
 948
 949                 qcom,local-pid = <0>;
 950                 qcom,remote-pid = <4>;
 951
 952                 wcnss_smp2p_out: master-kernel {
 953                         qcom,entry-name = "master-kernel";
 954
 955                         #qcom,smem-state-cells = <1>;
 956                 };
 957
 958                 wcnss_smp2p_in: slave-kernel {
 959                         qcom,entry-name = "slave-kernel";
 960
 961                         interrupt-controller;
 962                         #interrupt-cells = <2>;
 963                 };
 964         };
 965
 966         smsm {
 967                 compatible = "qcom,smsm";
 968
 969                 #address-cells = <1>;
 970                 #size-cells = <0>;
 971
 972                 qcom,ipc-1 = <&apcs 0 13>;
 973                 qcom,ipc-6 = <&apcs 0 19>;
 974
 975                 apps_smsm: apps@0 {
 976                         reg = <0>;
 977
 978                         #qcom,smem-state-cells = <1>;
 979                 };
 980
 981                 hexagon_smsm: hexagon@1 {
 982                         reg = <1>;
 983                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 984
 985                         interrupt-controller;
 986                         #interrupt-cells = <2>;
 987                 };
 988
 989                 wcnss_smsm: wcnss@6 {
 990                         reg = <6>;
 991                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 992
 993                         interrupt-controller;
 994                         #interrupt-cells = <2>;
 995                 };
 996         };
 997 };
 998
 999 #include "msm8916-pins.dtsi"