arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17 #include <dt-bindings/clock/qcom,rpmcc.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19 #include <dt-bindings/arm/qcom-ids.h>
  20
  21 / {
  22         model = "Qualcomm Technologies, Inc. MSM8916";
  23         compatible = "qcom,msm8916";
  24         qcom,msm-id =   <QCOM_ID_MSM8916 0>,
  25                         <QCOM_ID_MSM8216 0>,
  26                         <QCOM_ID_MSM8116 0>,
  27                         <QCOM_ID_MSM8616 0>,
  28                         <QCOM_ID_APQ8016 0>;
  29
  30
  31         interrupt-parent = <&intc>;
  32
  33         #address-cells = <2>;
  34         #size-cells = <2>;
  35
  36         aliases {
  37                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  38                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  39         };
  40
  41         chosen { };
  42
  43         memory {
  44                 device_type = "memory";
  45                 /* We expect the bootloader to fill in the reg */
  46                 reg = <0 0 0 0>;
  47         };
  48
  49         reserved-memory {
  50                 #address-cells = <2>;
  51                 #size-cells = <2>;
  52                 ranges;
  53
  54                 reserve_aligned@86000000 {
  55                         reg = <0x0 0x86000000 0x0 0x0300000>;
  56                         no-map;
  57                 };
  58
  59                 smem_mem: smem_region@86300000 {
  60                         reg = <0x0 0x86300000 0x0 0x0100000>;
  61                         no-map;
  62                 };
  63
  64                 hypervisor_mem: hypervisor_region@86400000 {
  65                         no-map;
  66                         reg = <0x0 0x86400000 0x0 0x0400000>;
  67                 };
  68
  69                 modem_adsp_mem: modem_adsp_region@86800000 {
  70                         no-map;
  71                         reg = <0x0 0x86800000 0x0 0x04800000>;
  72                 };
  73
  74                 peripheral_mem: peripheral_region@8b600000 {
  75                         no-map;
  76                         reg = <0x0 0x8b600000 0x0 0x0600000>;
  77                 };
  78
  79                 vidc_mem: vidc_region@8f800000 {
  80                         no-map;
  81                         reg = <0 0x8f800000 0 0x800000>;
  82                 };
  83         };
  84
  85         cpus {
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88
  89                 CPU0: cpu@0 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53", "arm,armv8";
  92                         reg = <0x0>;
  93                         enable-method = "qcom,arm-cortex-acc";
  94                         qcom,acc = <&acc0>;
  95                         next-level-cache = <&L2_0>;
  96                         clocks = <&a53cc 1>;
  97                         clock-latency = <200000>;
  98                         cpu-supply = <&pm8916_s2>;
  99                         /* cooling options */
 100                         cooling-min-level = <0>;
 101                         cooling-max-level = <7>;
 102                         #cooling-cells = <2>;
 103                         L2_0: l2-cache {
 104                               compatible = "arm,arch-cache";
 105                               cache-level = <2>;
 106                               power-domain = <&l2ccc_0>;
 107                         };
 108                 };
 109
 110                 CPU1: cpu@1 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a53", "arm,armv8";
 113                         reg = <0x1>;
 114                         enable-method = "qcom,arm-cortex-acc";
 115                         qcom,acc = <&acc1>;
 116                         next-level-cache = <&L2_0>;
 117                         clocks = <&a53cc 1>;
 118                         clock-latency = <200000>;
 119                         cpu-supply = <&pm8916_s2>;
 120                         /* cooling options */
 121                         cooling-min-level = <0>;
 122                         cooling-max-level = <7>;
 123                         #cooling-cells = <2>;
 124                 };
 125
 126                 CPU2: cpu@2 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x2>;
 130                         enable-method = "qcom,arm-cortex-acc";
 131                         qcom,acc = <&acc2>;
 132                         next-level-cache = <&L2_0>;
 133                         clocks = <&a53cc 1>;
 134                         clock-latency = <200000>;
 135                         cpu-supply = <&pm8916_s2>;
 136                         /* cooling options */
 137                         cooling-min-level = <0>;
 138                         cooling-max-level = <7>;
 139                         #cooling-cells = <2>;
 140                 };
 141
 142                 CPU3: cpu@3 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a53", "arm,armv8";
 145                         reg = <0x3>;
 146                         enable-method = "qcom,arm-cortex-acc";
 147                         qcom,acc = <&acc3>;
 148                         next-level-cache = <&L2_0>;
 149                         clocks = <&a53cc 1>;
 150                         clock-latency = <200000>;
 151                         cpu-supply = <&pm8916_s2>;
 152                         /* cooling options */
 153                         cooling-min-level = <0>;
 154                         cooling-max-level = <7>;
 155                         #cooling-cells = <2>;
 156                 };
 157         };
 158
 159         cpu-pmu {
 160                 compatible = "arm,armv8-pmuv3";
 161                 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
 162         };
 163
 164         thermal-zones {
 165                 cpu-thermal0 {
 166                         polling-delay-passive = <250>;
 167                         polling-delay = <1000>;
 168
 169                         thermal-sensors = <&tsens 4>;
 170
 171                         trips {
 172                                 cpu_alert0: trip@0 {
 173                                         temperature = <75000>;
 174                                         hysteresis = <2000>;
 175                                         type = "passive";
 176                                 };
 177                                 cpu_crit0: trip@1 {
 178                                         temperature = <100000>;
 179                                         hysteresis = <2000>;
 180                                         type = "critical";
 181                                 };
 182                         };
 183
 184                         cooling-maps {
 185                                 map0 {
 186                                         trip = <&cpu_alert0>;
 187                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 188                                 };
 189                         };
 190                 };
 191
 192                 cpu-thermal1 {
 193                         polling-delay-passive = <250>;
 194                         polling-delay = <1000>;
 195
 196                         thermal-sensors = <&tsens 3>;
 197
 198                         trips {
 199                                 cpu_alert1: trip@0 {
 200                                         temperature = <75000>;
 201                                         hysteresis = <2000>;
 202                                         type = "passive";
 203                                 };
 204                                 cpu_crit1: trip@1 {
 205                                         temperature = <100000>;
 206                                         hysteresis = <2000>;
 207                                         type = "critical";
 208                                 };
 209                         };
 210
 211                         cooling-maps {
 212                                 map0 {
 213                                         trip = <&cpu_alert1>;
 214                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 215                                 };
 216                         };
 217                 };
 218         };
 219
 220         timer {
 221                 compatible = "arm,armv8-timer";
 222                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 223                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 224                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 225                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 226         };
 227
 228         clocks {
 229                 xo_board: xo_board {
 230                         compatible = "fixed-clock";
 231                         #clock-cells = <0>;
 232                         clock-frequency = <19200000>;
 233                         clock-output-names = "xo_board";
 234                 };
 235
 236                 sleep_clk: sleep_clk {
 237                         compatible = "fixed-clock";
 238                         #clock-cells = <0>;
 239                         clock-frequency = <32768>;
 240                 };
 241         };
 242
 243         soc: soc {
 244                 #address-cells = <1>;
 245                 #size-cells = <1>;
 246                 ranges = <0 0 0 0xffffffff>;
 247                 compatible = "simple-bus";
 248
 249                 restart@4ab000 {
 250                         compatible = "qcom,pshold";
 251                         reg = <0x4ab000 0x4>;
 252                 };
 253
 254                 msmgpio: pinctrl@1000000 {
 255                         compatible = "qcom,msm8916-pinctrl";
 256                         reg = <0x1000000 0x300000>;
 257                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 258                         gpio-controller;
 259                         #gpio-cells = <2>;
 260                         interrupt-controller;
 261                         #interrupt-cells = <2>;
 262                 };
 263
 264                 gcc: qcom,gcc@1800000 {
 265                         compatible = "qcom,gcc-msm8916";
 266                         #clock-cells = <1>;
 267                         #reset-cells = <1>;
 268                         #power-domain-cells = <1>;
 269                         reg = <0x1800000 0x80000>;
 270                 };
 271
 272                 tcsr_mutex_regs: syscon@1905000 {
 273                         compatible = "syscon";
 274                         reg = <0x1905000 0x20000>;
 275                 };
 276
 277                 tcsr_mutex: hwlock {
 278                         compatible = "qcom,tcsr-mutex";
 279                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 280                         #hwlock-cells = <1>;
 281                 };
 282
 283                 rpm_msg_ram: memory@60000 {
 284                         compatible = "qcom,rpm-msg-ram";
 285                         reg = <0x60000 0x8000>;
 286                 };
 287
 288                 blsp1_uart1: serial@78af000 {
 289                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 290                         reg = <0x78af000 0x200>;
 291                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 292                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 293                         clock-names = "core", "iface";
 294                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 295                         dma-names = "rx", "tx";
 296                         status = "disabled";
 297                 };
 298
 299                 apcs: syscon@b011000 {
 300                         compatible = "syscon";
 301                         reg = <0x0b011000 0x1000>;
 302                 };
 303
 304                 a53cc: qcom,a53cc@0b016000 {
 305                         compatible = "qcom,clock-a53-msm8916";
 306                         reg = <0x0b016000 0x40>;
 307                         #clock-cells = <1>;
 308                         qcom,apcs = <&apcs>;
 309                 };
 310
 311                 blsp1_uart2: serial@78b0000 {
 312                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 313                         reg = <0x78b0000 0x200>;
 314                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 315                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 316                         clock-names = "core", "iface";
 317                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 318                         dma-names = "rx", "tx";
 319                         status = "disabled";
 320                 };
 321
 322                 blsp_dma: dma@7884000 {
 323                         compatible = "qcom,bam-v1.7.0";
 324                         reg = <0x07884000 0x23000>;
 325                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 326                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 327                         clock-names = "bam_clk";
 328                         #dma-cells = <1>;
 329                         qcom,ee = <0>;
 330                         status = "disabled";
 331                 };
 332
 333                 blsp_spi1: spi@78b5000 {
 334                         compatible = "qcom,spi-qup-v2.2.1";
 335                         reg = <0x078b5000 0x600>;
 336                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 338                                  <&gcc GCC_BLSP1_AHB_CLK>;
 339                         clock-names = "core", "iface";
 340                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 341                         dma-names = "rx", "tx";
 342                         pinctrl-names = "default", "sleep";
 343                         pinctrl-0 = <&spi1_default>;
 344                         pinctrl-1 = <&spi1_sleep>;
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         status = "disabled";
 348                 };
 349
 350                 blsp_spi2: spi@78b6000 {
 351                         compatible = "qcom,spi-qup-v2.2.1";
 352                         reg = <0x078b6000 0x600>;
 353                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 354                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 355                                  <&gcc GCC_BLSP1_AHB_CLK>;
 356                         clock-names = "core", "iface";
 357                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 358                         dma-names = "rx", "tx";
 359                         pinctrl-names = "default", "sleep";
 360                         pinctrl-0 = <&spi2_default>;
 361                         pinctrl-1 = <&spi2_sleep>;
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         status = "disabled";
 365                 };
 366
 367                 blsp_spi3: spi@78b7000 {
 368                         compatible = "qcom,spi-qup-v2.2.1";
 369                         reg = <0x078b7000 0x600>;
 370                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 371                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 372                                  <&gcc GCC_BLSP1_AHB_CLK>;
 373                         clock-names = "core", "iface";
 374                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 375                         dma-names = "rx", "tx";
 376                         pinctrl-names = "default", "sleep";
 377                         pinctrl-0 = <&spi3_default>;
 378                         pinctrl-1 = <&spi3_sleep>;
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         status = "disabled";
 382                 };
 383
 384                 blsp_spi4: spi@78b8000 {
 385                         compatible = "qcom,spi-qup-v2.2.1";
 386                         reg = <0x078b8000 0x600>;
 387                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 388                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 389                                  <&gcc GCC_BLSP1_AHB_CLK>;
 390                         clock-names = "core", "iface";
 391                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 392                         dma-names = "rx", "tx";
 393                         pinctrl-names = "default", "sleep";
 394                         pinctrl-0 = <&spi4_default>;
 395                         pinctrl-1 = <&spi4_sleep>;
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                         status = "disabled";
 399                 };
 400
 401                 blsp_spi5: spi@78b9000 {
 402                         compatible = "qcom,spi-qup-v2.2.1";
 403                         reg = <0x078b9000 0x600>;
 404                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 405                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 406                                  <&gcc GCC_BLSP1_AHB_CLK>;
 407                         clock-names = "core", "iface";
 408                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 409                         dma-names = "rx", "tx";
 410                         pinctrl-names = "default", "sleep";
 411                         pinctrl-0 = <&spi5_default>;
 412                         pinctrl-1 = <&spi5_sleep>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         status = "disabled";
 416                 };
 417
 418                 blsp_spi6: spi@78ba000 {
 419                         compatible = "qcom,spi-qup-v2.2.1";
 420                         reg = <0x078ba000 0x600>;
 421                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 422                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 423                                  <&gcc GCC_BLSP1_AHB_CLK>;
 424                         clock-names = "core", "iface";
 425                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 426                         dma-names = "rx", "tx";
 427                         pinctrl-names = "default", "sleep";
 428                         pinctrl-0 = <&spi6_default>;
 429                         pinctrl-1 = <&spi6_sleep>;
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                         status = "disabled";
 433                 };
 434
 435                 blsp_i2c2: i2c@78b6000 {
 436                         compatible = "qcom,i2c-qup-v2.2.1";
 437                         reg = <0x78b6000 0x1000>;
 438                         interrupts = <GIC_SPI 96 0>;
 439                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 440                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 441                         clock-names = "iface", "core";
 442                         pinctrl-names = "default", "sleep";
 443                         pinctrl-0 = <&i2c2_default>;
 444                         pinctrl-1 = <&i2c2_sleep>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         status = "disabled";
 448                 };
 449
 450                 blsp_i2c4: i2c@78b8000 {
 451                         compatible = "qcom,i2c-qup-v2.2.1";
 452                         reg = <0x78b8000 0x1000>;
 453                         interrupts = <GIC_SPI 98 0>;
 454                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 455                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 456                         clock-names = "iface", "core";
 457                         pinctrl-names = "default", "sleep";
 458                         pinctrl-0 = <&i2c4_default>;
 459                         pinctrl-1 = <&i2c4_sleep>;
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         status = "disabled";
 463                 };
 464
 465                 blsp_i2c6: i2c@78ba000 {
 466                         compatible = "qcom,i2c-qup-v2.2.1";
 467                         reg = <0x78ba000 0x1000>;
 468                         interrupts = <GIC_SPI 100 0>;
 469                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 470                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 471                         clock-names = "iface", "core";
 472                         pinctrl-names = "default", "sleep";
 473                         pinctrl-0 = <&i2c6_default>;
 474                         pinctrl-1 = <&i2c6_sleep>;
 475                         #address-cells = <1>;
 476                         #size-cells = <0>;
 477                         status = "disabled";
 478                 };
 479
 480                 sdhc_1: sdhci@07824000 {
 481                         compatible = "qcom,sdhci-msm-v4";
 482                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 483                         reg-names = "hc_mem", "core_mem";
 484
 485                         interrupts = <0 123 0>, <0 138 0>;
 486                         interrupt-names = "hc_irq", "pwr_irq";
 487                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 488                                  <&gcc GCC_SDCC1_AHB_CLK>;
 489                         clock-names = "core", "iface";
 490                         bus-width = <8>;
 491                         non-removable;
 492                         status = "disabled";
 493                 };
 494
 495                 sdhc_2: sdhci@07864000 {
 496                         compatible = "qcom,sdhci-msm-v4";
 497                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 498                         reg-names = "hc_mem", "core_mem";
 499
 500                         interrupts = <0 125 0>, <0 221 0>;
 501                         interrupt-names = "hc_irq", "pwr_irq";
 502                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 503                                  <&gcc GCC_SDCC2_AHB_CLK>;
 504                         clock-names = "core", "iface";
 505                         bus-width = <4>;
 506                         status = "disabled";
 507                 };
 508
 509                 usb_dev: usb@78d9000 {
 510                         compatible = "qcom,ci-hdrc";
 511                         reg = <0x78d9000 0x400>;
 512                         dr_mode = "peripheral";
 513                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 514                         usb-phy = <&usb_otg>;
 515                         status = "disabled";
 516                 };
 517
 518                 usb_host: ehci@78d9000 {
 519                         compatible = "qcom,ehci-host";
 520                         reg = <0x78d9000 0x400>;
 521                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 522                         usb-phy = <&usb_otg>;
 523                         status = "disabled";
 524                 };
 525
 526                 usb_otg: phy@78d9000 {
 527                         compatible = "qcom,usb-otg-snps";
 528                         reg = <0x78d9000 0x400>;
 529                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 530                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 531
 532                         v1p8-supply = <&pm8916_l7>;
 533                         v3p3-supply = <&pm8916_l13>;
 534                         qcom,vdd-levels = <1 5 7>;
 535                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 536                         dr_mode = "peripheral";
 537                         qcom,otg-control = <2>; // PMIC
 538                         qcom,manual-pullup;
 539
 540                         qcom,msm-bus,name = "usb2";
 541                         qcom,msm-bus,num-cases = <3>;
 542                         qcom,msm-bus,num-paths = <1>;
 543                         qcom,msm-bus,vectors-KBps =
 544                                         <87 512 0 0>,
 545                                         <87 512 80000 0>,
 546                                         <87 512 6000  6000>;
 547
 548                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 549                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 550                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 551                         clock-names = "iface", "core", "sleep";
 552
 553                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 554                                  <&gcc GCC_USB_HS_BCR>;
 555                         reset-names = "phy", "link";
 556                         status = "disabled";
 557                 };
 558
 559                 intc: interrupt-controller@b000000 {
 560                         compatible = "qcom,msm-qgic2";
 561                         interrupt-controller;
 562                         #interrupt-cells = <3>;
 563                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 564                 };
 565
 566                 l2ccc_0: clock-controller@b011000 {
 567                         compatible = "qcom,8916-l2ccc";
 568                         reg = <0x0b011000 0x1000>;
 569                 };
 570
 571                 timer@b020000 {
 572                         #address-cells = <1>;
 573                         #size-cells = <1>;
 574                         ranges;
 575                         compatible = "arm,armv7-timer-mem";
 576                         reg = <0xb020000 0x1000>;
 577                         clock-frequency = <19200000>;
 578
 579                         frame@b021000 {
 580                                 frame-number = <0>;
 581                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 582                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 583                                 reg = <0xb021000 0x1000>,
 584                                       <0xb022000 0x1000>;
 585                         };
 586
 587                         frame@b023000 {
 588                                 frame-number = <1>;
 589                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 590                                 reg = <0xb023000 0x1000>;
 591                                 status = "disabled";
 592                         };
 593
 594                         frame@b024000 {
 595                                 frame-number = <2>;
 596                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 597                                 reg = <0xb024000 0x1000>;
 598                                 status = "disabled";
 599                         };
 600
 601                         frame@b025000 {
 602                                 frame-number = <3>;
 603                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 604                                 reg = <0xb025000 0x1000>;
 605                                 status = "disabled";
 606                         };
 607
 608                         frame@b026000 {
 609                                 frame-number = <4>;
 610                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 611                                 reg = <0xb026000 0x1000>;
 612                                 status = "disabled";
 613                         };
 614
 615                         frame@b027000 {
 616                                 frame-number = <5>;
 617                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 618                                 reg = <0xb027000 0x1000>;
 619                                 status = "disabled";
 620                         };
 621
 622                         frame@b028000 {
 623                                 frame-number = <6>;
 624                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 625                                 reg = <0xb028000 0x1000>;
 626                                 status = "disabled";
 627                         };
 628                 };
 629
 630                 spmi_bus: spmi@200f000 {
 631                         compatible = "qcom,spmi-pmic-arb";
 632                         reg = <0x200f000 0x001000>,
 633                               <0x2400000 0x400000>,
 634                               <0x2c00000 0x400000>,
 635                               <0x3800000 0x200000>,
 636                               <0x200a000 0x002100>;
 637                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 638                         interrupt-names = "periph_irq";
 639                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 640                         qcom,ee = <0>;
 641                         qcom,channel = <0>;
 642                         #address-cells = <2>;
 643                         #size-cells = <0>;
 644                         interrupt-controller;
 645                         #interrupt-cells = <4>;
 646                 };
 647
 648                 rng@22000 {
 649                         compatible = "qcom,prng";
 650                         reg = <0x00022000 0x200>;
 651                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 652                         clock-names = "core";
 653                 };
 654                 acc0: clock-controller@b088000 {
 655                         compatible = "qcom,arm-cortex-acc";
 656                         reg = <0x0b088000 0x1000>,
 657                               <0x0b008000 0x1000>;
 658                 };
 659
 660                 acc1: clock-controller@b098000 {
 661                         compatible = "qcom,arm-cortex-acc";
 662                         reg = <0x0b098000 0x1000>,
 663                               <0x0b008000 0x1000>;
 664                 };
 665
 666                 acc2: clock-controller@b0a8000 {
 667                         compatible = "qcom,arm-cortex-acc";
 668                         reg = <0x0b0a8000 0x1000>,
 669                               <0x0b008000 0x1000>;
 670                 };
 671
 672                 acc3: clock-controller@b0b8000 {
 673                         compatible = "qcom,arm-cortex-acc";
 674                         reg = <0x0b0b8000 0x1000>,
 675                               <0x0b008000 0x1000>;
 676                 };
 677
 678                 /* Audio */
 679
 680                 wcd_digital: codec-digital{
 681                         compatible = "syscon", "qcom,apq8016-wcd-digital-codec";
 682                         reg = <0x0771c000 0x400>;
 683                 };
 684
 685                 lpass: lpass-cpu@07700000 {
 686                         status = "disabled";
 687                         compatible = "qcom,lpass-cpu-apq8016";
 688                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 689                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 690                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 691                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 692                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 693                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
 694                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 695
 696                         clock-names = "ahbix-clk",
 697                                         "pcnoc-mport-clk",
 698                                         "pcnoc-sway-clk",
 699                                         "mi2s-bit-clk0",
 700                                         "mi2s-bit-clk1",
 701                                         "mi2s-bit-clk2",
 702                                         "mi2s-bit-clk3";
 703                         #sound-dai-cells = <1>;
 704
 705                         interrupts = <0 160 0>;
 706                         interrupt-names = "lpass-irq-lpaif";
 707                         reg = <0x07708000 0x10000>, <0x07702000 0x4>, <0x07702004 0x4>;
 708                         reg-names = "lpass-lpaif", "mic-iomux", "spkr-iomux";
 709                 };
 710
 711                 sound: sound {
 712                         status = "disabled";
 713                         compatible = "qcom,apq8016-sbc-sndcard";
 714                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
 715                         reg-names = "mic-iomux", "spkr-iomux";
 716                 };
 717
 718                 tcsr: syscon@1937000 {
 719                         compatible = "qcom,tcsr-msm8916", "syscon";
 720                         reg = <0x1937000 0x30000>;
 721                 };
 722
 723                 uqfprom: eeprom@58000 {
 724                         compatible = "qcom,qfprom-msm8916";
 725                         reg = <0x58000 0x7000>;
 726                 };
 727
 728                 cpr@b018000 {
 729                         compatible = "qcom,cpr";
 730                         reg = <0xb018000 0x1000>;
 731                         interrupts = <0 15 1>, <0 16 1>, <0 17 1>;
 732                         vdd-mx-supply = <&pm8916_l3>;
 733                         acc-syscon = <&tcsr>;
 734                         eeprom = <&uqfprom>;
 735
 736                         qcom,cpr-ref-clk = <19200>;
 737                         qcom,cpr-timer-delay-us = <5000>;
 738                         qcom,cpr-timer-cons-up = <0>;
 739                         qcom,cpr-timer-cons-down = <2>;
 740                         qcom,cpr-up-threshold = <0>;
 741                         qcom,cpr-down-threshold = <2>;
 742                         qcom,cpr-idle-clocks = <15>;
 743                         qcom,cpr-gcnt-us = <1>;
 744                         qcom,vdd-apc-step-up-limit = <1>;
 745                         qcom,vdd-apc-step-down-limit = <1>;
 746                         qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
 747                 };
 748
 749                 qfprom: qfprom@5c000 {
 750                         compatible = "qcom,qfprom";
 751                         reg = <0x5c000 0x1000>;
 752                         #address-cells = <1>;
 753                         #size-cells = <1>;
 754                         tsens_caldata: caldata@d0 {
 755                                 reg = <0xd0 0x8>;
 756                         };
 757                         tsens_calsel: calsel@ec {
 758                                 reg = <0xec 0x4>;
 759                         };
 760                 };
 761
 762                 tsens: thermal-sensor@4a8000 {
 763                         compatible = "qcom,msm8916-tsens";
 764                         reg = <0x4a8000 0x2000>;
 765                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 766                         nvmem-cell-names = "calib", "calib_sel";
 767                         qcom,tsens-slopes = <3200 3200 3200 3200 3200>;
 768                         qcom,sensor-id = <0 1 2 4 5>;
 769                         #thermal-sensor-cells = <1>;
 770                 };
 771
 772                 q6-smp2p {
 773                         compatible = "qcom,smp2p";
 774                         qcom,smem = <435>, <428>;
 775                         interrupts = <0 27 1>;
 776                         qcom,ipc = <&apcs 8 14>;
 777
 778                         qcom,local-pid = <0>;
 779                         qcom,remote-pid = <1>;
 780
 781                         q6_smp2p_out: master-kernel {
 782                                 qcom,entry-name = "master-kernel";
 783                                 qcom,outbound;
 784
 785                                 gpio-controller;
 786                                 #gpio-cells = <2>;
 787                         };
 788
 789                         q6_smp2p_in: slave-kernel {
 790                                 qcom,entry-name = "slave-kernel";
 791                                 qcom,inbound;
 792
 793                                 interrupt-controller;
 794                                 #interrupt-cells = <2>;
 795                         };
 796                 };
 797
 798                 wcnss-smp2p {
 799                         compatible = "qcom,smp2p";
 800                         qcom,smem = <451>, <431>;
 801
 802                         interrupts = <0 143 1>;
 803
 804                         qcom,ipc = <&apcs 8 18>;
 805
 806                         qcom,local-pid = <0>;
 807                         qcom,remote-pid = <4>;
 808
 809                         wcnss_smp2p_out: master-kernel {
 810                                 qcom,entry-name = "master-kernel";
 811                                 qcom,outbound;
 812
 813                                 gpio-controller;
 814                                 #gpio-cells = <2>;
 815                         };
 816
 817                         wcnss_smp2p_in: slave-kernel {
 818                                 qcom,entry-name = "slave-kernel";
 819                                 qcom,inbound;
 820
 821                                 interrupt-controller;
 822                                 #interrupt-cells = <2>;
 823                         };
 824                 };
 825
 826                 qcom,mss@4080000 {
 827                         compatible = "qcom,pil-q6v56-mss", "qcom,q6v5-pil";
 828                         reg = <0x04080000 0x100>,
 829                               <0x04020000 0x040>,
 830                               <0x01810000 0x004>,
 831                               <0x01810000 0x004>,
 832                               <0x0194f000 0x010>,
 833                               <0x01950000 0x008>,
 834                               <0x01951000 0x008>;
 835
 836                         reg-names = "qdsp6_base", "rmb_base", "restart_reg_sec",
 837                                         "halt_q6", "halt_modem", "halt_nc";
 838
 839                         interrupts-extended = <&intc 0 24 1>,
 840                                               <&q6_smp2p_in 0 0>,
 841                                               <&q6_smp2p_in 1 0>,
 842                                               <&q6_smp2p_in 2 0>,
 843                                               <&q6_smp2p_in 3 0>;
 844                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 845
 846                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>;
 847
 848                         clock-names = "iface", "bus", "mem";
 849
 850                         qcom,mx-supply = <&pm8916_l3>;
 851                         qcom,mx-uV = <1050000>;
 852                         qcom,pll-supply = <&pm8916_l7>;
 853                         qcom,pll-uV = <1800000>;
 854                         qcom,proxy-clock-names = "xo";
 855                         qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
 856                         qcom,is-loadable;
 857                         qcom,firmware-name = "modem";
 858                         qcom,pil-self-auth;
 859
 860
 861                         /* GPIO inputs from mss */
 862                         qcom,gpio-err-fatal = <&q6_smp2p_in 0 0>;
 863                         qcom,gpio-err-ready = <&q6_smp2p_in 1 0>;
 864                         qcom,gpio-proxy-unvote = <&q6_smp2p_in 2 0>;
 865                         qcom,gpio-stop-ack = <&q6_smp2p_in 3 0>;
 866                         qcom,gpio-ramdump-disable = <&q6_smp2p_in 15 0>;
 867                         /* GPIO output to mss */
 868                         qcom,gpio-force-stop = <&q6_smp2p_out 0 0>;
 869                         qcom,stop-gpio = <&q6_smp2p_out 0 0>;
 870                         memory-region = <&modem_adsp_mem>;
 871                 };
 872
 873                 pronto_rproc:pronto_rproc {
 874                         compatible = "qcom,tz-pil";
 875
 876                         interrupts-extended = <&intc 0 149 1>,
 877                                               <&wcnss_smp2p_in 0 0>,
 878                                               <&wcnss_smp2p_in 1 0>,
 879                                               <&wcnss_smp2p_in 2 0>,
 880                                               <&wcnss_smp2p_in 3 0>;
 881                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 882
 883                         clocks = <&gcc GCC_CRYPTO_CLK>,
 884                                  <&gcc GCC_CRYPTO_AHB_CLK>,
 885                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 886                                  <&gcc CRYPTO_CLK_SRC>;
 887                         clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_src_clk";
 888
 889                         qcom,firmware-name = "wcnss";
 890                         qcom,pas-id = <6>;
 891
 892                         qcom,crash-reason = <422>;
 893                         qcom,smd-edges = <&pronto_smd_edge>;
 894
 895                         qcom,pll-supply = <&pm8916_l7>;
 896                         qcom,pll-uV = <1800000>;
 897                         qcom,pll-uA = <18000>;
 898
 899                         qcom,stop-gpio = <&wcnss_smp2p_out 0 0>;
 900
 901                         pinctrl-names = "default";
 902                         pinctrl-0 = <&wcnss_default>;
 903
 904                         memory-region = <&peripheral_mem>;
 905                 };
 906
 907                 qcom,wcn36xx@0a000000 {
 908                         compatible = "qcom,wcn3620";
 909                         reg = <0x0a000000 0x280000>,
 910                                 <0xb011008 0x04>,
 911                                 <0x0a21b000 0x3000>,
 912                                 <0x03204000 0x00000100>,
 913                                 <0x03200800 0x00000200>,
 914                                 <0x0A100400 0x00000200>,
 915                                 <0x0A205050 0x00000200>,
 916                                 <0x0A219000 0x00000020>,
 917                                 <0x0A080488 0x00000008>,
 918                                 <0x0A080fb0 0x00000008>,
 919                                 <0x0A08040c 0x00000008>,
 920                                 <0x0A0120a8 0x00000008>,
 921                                 <0x0A012448 0x00000008>,
 922                                 <0x0A080c00 0x00000001>;
 923
 924                         reg-names = "wcnss_mmio", "wcnss_fiq",
 925                                     "pronto_phy_base", "riva_phy_base",
 926                                     "riva_ccu_base", "pronto_a2xb_base",
 927                                     "pronto_ccpu_base", "pronto_saw2_base",
 928                                     "wlan_tx_phy_aborts","wlan_brdg_err_source",
 929                                     "wlan_tx_status", "alarms_txctl",
 930                                     "alarms_tactl", "pronto_mcu_base";
 931
 932                         interrupts = <0 145 0 0 146 0>;
 933                         interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
 934
 935                         // qcom,pronto-vddmx-supply = <&pm8916_l3>;
 936                         // qcom,pronto-vddcx-supply = <&pm8916_s1_corner>;
 937                         // qcom,pronto-vddpx-supply = <&pm8916_l7>;
 938                         // qcom,iris-vddxo-supply   = <&pm8916_l7>;
 939                         // qcom,iris-vddrfa-supply  = <&pm8916_s3>;
 940                         // qcom,iris-vddpa-supply   = <&pm8916_l9>;
 941                         // qcom,iris-vdddig-supply  = <&pm8916_l5>;
 942
 943                         pinctrl-names = "wcnss_default";
 944                         // pinctrl-names = "wcnss_default", "wcnss_sleep",
 945                         //                                "wcnss_gpio_default";
 946                         pinctrl-0 = <&wcnss_default>;
 947                         // pinctrl-1 = <&wcnss_sleep>;
 948                         // pinctrl-2 = <&wcnss_gpio_default>;
 949
 950                         // clocks = <&rpmcc RPM_XO_CLK_SRC>,
 951                         //         <&rpmcc RPM_RF_CLK2>;
 952                         //clock-names = "xo", "rf_clk";
 953
 954                         rproc = <&pronto_rproc>;
 955                         qcom,has-autodetect-xo;
 956                         qcom,wlan-rx-buff-count = <512>;
 957                         qcom,is-pronto-vt;
 958                         qcom,has-pronto-hw;
 959                         // qcom,wcnss-adc_tm = <&pm8916_adc_tm>;
 960                 };
 961
 962
 963
 964                 qcom,rpm-log@29dc00 {
 965                         compatible = "qcom,rpm-log";
 966                         reg = <0x29dc00 0x4000>;
 967                         qcom,rpm-addr-phys = <0x200000>;
 968                         qcom,offset-version = <4>;
 969                         qcom,offset-page-buffer-addr = <36>;
 970                         qcom,offset-log-len = <40>;
 971                         qcom,offset-log-len-mask = <44>;
 972                         qcom,offset-page-indices = <56>;
 973                 };
 974
 975                 vidc_rproc: vidc_tzpil@0 {
 976                         compatible = "qcom,tz-pil";
 977                         clocks = <&gcc GCC_CRYPTO_CLK>,
 978                                  <&gcc GCC_CRYPTO_AHB_CLK>,
 979                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 980                                  <&gcc CRYPTO_CLK_SRC>;
 981                         clock-names = "scm_core_clk", "scm_iface_clk",
 982                                       "scm_bus_clk", "scm_src_clk";
 983                         qcom,firmware-name = "venus";
 984                         qcom,pas-id = <9>;
 985                         memory-region = <&vidc_mem>;
 986                         status = "disabled";
 987                 };
 988
 989                 vidc: qcom,vidc@1d00000 {
 990                         compatible = "qcom,msm-vidc";
 991                         reg = <0x01d00000 0xff000>;
 992                         interrupts = <GIC_SPI 44 0>;
 993                         power-domains = <&gcc VENUS_GDSC>;
 994                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
 995                                  <&gcc GCC_VENUS0_AHB_CLK>,
 996                                  <&gcc GCC_VENUS0_AXI_CLK>;
 997                         clock-names = "core_clk", "iface_clk", "bus_clk";
 998                         qcom,hfi = "venus";
 999                         qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */
1000                         qcom,enable-idle-indicator;
1001                         rproc = <&vidc_rproc>;
1002                         qcom,iommu-cb = <&venus_ns>,
1003                                         <&venus_sec_bitstream>,
1004                                         <&venus_sec_pixel>,
1005                                         <&venus_sec_non_pixel>;
1006                         status = "disabled";
1007                 };
1008         };
1009
1010         smem {
1011                 compatible = "qcom,smem";
1012
1013                 memory-region = <&smem_mem>;
1014                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
1015
1016                 hwlocks = <&tcsr_mutex 3>;
1017         };
1018         smd {
1019                 compatible = "qcom,smd";
1020
1021                 rpm {
1022                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1023                         qcom,ipc = <&apcs 8 0>;
1024                         qcom,smd-edge = <15>;
1025                         qcom,remote-pid = <0xffffffff>;
1026
1027                         rpm_requests {
1028                                 compatible = "qcom,rpm-msm8916";
1029                                 qcom,smd-channels = "rpm_requests";
1030                                 rpmcc: qcom,rpmcc {
1031                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
1032                                         #clock-cells = <1>;
1033                                 };
1034
1035                                 msm-bus {
1036                                                 compatible = "qcom,rpm-msm-bus";
1037                                 };
1038                                 pm8916-regulators {
1039                                         compatible = "qcom,rpm-pm8916-regulators";
1040
1041                                         pm8916_s1: s1 {};
1042                                         pm8916_s2: s2 {};
1043                                         pm8916_s3: s3 {};
1044                                         pm8916_s4: s4 {};
1045
1046                                         pm8916_l1: l1 {};
1047                                         pm8916_l2: l2 {};
1048                                         pm8916_l3: l3 {};
1049                                         pm8916_l4: l4 {};
1050                                         pm8916_l5: l5 {};
1051                                         pm8916_l6: l6 {};
1052                                         pm8916_l7: l7 {};
1053                                         pm8916_l8: l8 {};
1054                                         pm8916_l9: l9 {};
1055                                         pm8916_l10: l10 {};
1056                                         pm8916_l11: l11 {};
1057                                         pm8916_l12: l12 {};
1058                                         pm8916_l13: l13 {};
1059                                         pm8916_l14: l14 {};
1060                                         pm8916_l15: l15 {};
1061                                         pm8916_l16: l16 {};
1062                                         pm8916_l17: l17 {};
1063                                         pm8916_l18: l18 {};
1064                                 };
1065                         };
1066                 };
1067
1068                 qcom,smd-modem {
1069                         interrupts = <0 25 1>;
1070                         qcom,smd-edge = <0>;
1071                         qcom,ipc = <&apcs 8 12>;
1072                         qcom,remote-pid = <1>;
1073                         ipcrtr_requests {
1074                                 compatible = "qcom,ipcrtr";
1075                                 qcom,smd-channels = "IPCRTR";
1076                         };
1077                 };
1078
1079                 pronto_smd_edge: pronto {
1080                         interrupts = <0 142 1>;
1081
1082                         qcom,ipc = <&apcs 8 17>;
1083                         qcom,smd-edge = <6>;
1084                         qcom,remote-pid = <4>;
1085
1086                                bt {
1087                                 compatible = "qcom,hci-smd";
1088                                 qcom,smd-channels = "APPS_RIVA_BT_CMD", "APPS_RIVA_BT_ACL";
1089                                 qcom,smd-channel-names = "event", "data";
1090                         };
1091
1092                         ipcrtr {
1093                                 compatible = "qcom,ipcrtr";
1094                                 qcom,smd-channels = "IPCRTR";
1095                         };
1096
1097                         wifi {
1098                                 compatible = "qcom,wlan-ctrl";
1099                                 qcom,smd-channels = "WLAN_CTRL";
1100
1101                                 interrupts = <0 145 0>, <0 146 0>;
1102                                 interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
1103
1104                                 qcom,wcnss_mmio = <0xfb000000 0x21b000>;
1105
1106                                 // qcom,tx-enable-gpios = <&apps_smsm 10 0>;
1107                                 // qcom,tx-rings-empty-gpios = <&apps_smsm 9 0>;
1108                         };
1109
1110                         wcnss_ctrl {
1111                                 compatible = "qcom,wcnss-ctrl";
1112                                 qcom,smd-channels = "WCNSS_CTRL";
1113
1114                                 qcom,wcnss_mmio = <0xfb21b000 0x3000>;
1115                         };
1116                 };
1117         };
1118
1119
1120 };
1121
1122 #include "msm8916-pins.dtsi"
1123 #include "msm8916-iommu.dtsi"
1124 #include "msm8916-coresight.dtsi"
1125 #include "msm8916-bus.dtsi"