2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
17 #include <dt-bindings/clock/qcom,rpmcc.h>
18 #include <dt-bindings/thermal/thermal.h>
19 #include <dt-bindings/arm/qcom-ids.h>
22 model = "Qualcomm Technologies, Inc. MSM8916";
23 compatible = "qcom,msm8916";
24 qcom,msm-id = <QCOM_ID_MSM8916 0>,
31 interrupt-parent = <&intc>;
37 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
38 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
44 device_type = "memory";
45 /* We expect the bootloader to fill in the reg */
54 reserve_aligned@86000000 {
55 reg = <0x0 0x86000000 0x0 0x0300000>;
59 smem_mem: smem_region@86300000 {
60 reg = <0x0 0x86300000 0x0 0x0100000>;
64 hypervisor_mem: hypervisor_region@86400000 {
66 reg = <0x0 0x86400000 0x0 0x0400000>;
69 modem_adsp_mem: modem_adsp_region@86800000 {
71 reg = <0x0 0x86800000 0x0 0x04800000>;
74 peripheral_mem: peripheral_region@8b600000 {
76 reg = <0x0 0x8b600000 0x0 0x0600000>;
79 vidc_mem: vidc_region@8f800000 {
81 reg = <0 0x8f800000 0 0x800000>;
91 compatible = "arm,cortex-a53", "arm,armv8";
93 enable-method = "qcom,arm-cortex-acc";
95 next-level-cache = <&L2_0>;
97 clock-latency = <200000>;
98 cpu-supply = <&pm8916_spmi_s2>;
100 cooling-min-level = <0>;
101 cooling-max-level = <7>;
102 #cooling-cells = <2>;
104 compatible = "arm,arch-cache";
106 power-domain = <&l2ccc_0>;
112 compatible = "arm,cortex-a53", "arm,armv8";
114 enable-method = "qcom,arm-cortex-acc";
116 next-level-cache = <&L2_0>;
118 clock-latency = <200000>;
119 cpu-supply = <&pm8916_spmi_s2>;
120 /* cooling options */
121 cooling-min-level = <0>;
122 cooling-max-level = <7>;
123 #cooling-cells = <2>;
128 compatible = "arm,cortex-a53", "arm,armv8";
130 enable-method = "qcom,arm-cortex-acc";
132 next-level-cache = <&L2_0>;
134 clock-latency = <200000>;
135 cpu-supply = <&pm8916_spmi_s2>;
136 /* cooling options */
137 cooling-min-level = <0>;
138 cooling-max-level = <7>;
139 #cooling-cells = <2>;
144 compatible = "arm,cortex-a53", "arm,armv8";
146 enable-method = "qcom,arm-cortex-acc";
148 next-level-cache = <&L2_0>;
150 clock-latency = <200000>;
151 cpu-supply = <&pm8916_spmi_s2>;
152 /* cooling options */
153 cooling-min-level = <0>;
154 cooling-max-level = <7>;
155 #cooling-cells = <2>;
160 compatible = "arm,armv8-pmuv3";
161 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
166 polling-delay-passive = <250>;
167 polling-delay = <1000>;
169 thermal-sensors = <&tsens 4>;
173 temperature = <75000>;
178 temperature = <100000>;
186 trip = <&cpu_alert0>;
187 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
193 polling-delay-passive = <250>;
194 polling-delay = <1000>;
196 thermal-sensors = <&tsens 3>;
200 temperature = <75000>;
205 temperature = <100000>;
213 trip = <&cpu_alert1>;
214 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
221 compatible = "arm,armv8-timer";
222 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
223 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
224 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
225 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
230 compatible = "fixed-clock";
232 clock-frequency = <19200000>;
233 clock-output-names = "xo_board";
236 sleep_clk: sleep_clk {
237 compatible = "fixed-clock";
239 clock-frequency = <32768>;
244 compatible = "simple-bus";
247 compatible = "qcom,scm";
248 clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
249 clock-names = "core", "bus", "iface";
254 #address-cells = <1>;
256 ranges = <0 0 0 0xffffffff>;
257 compatible = "simple-bus";
260 compatible = "qcom,pshold";
261 reg = <0x4ab000 0x4>;
264 msmgpio: pinctrl@1000000 {
265 compatible = "qcom,msm8916-pinctrl";
266 reg = <0x1000000 0x300000>;
267 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
274 gcc: qcom,gcc@1800000 {
275 compatible = "qcom,gcc-msm8916";
278 #power-domain-cells = <1>;
279 reg = <0x1800000 0x80000>;
282 tcsr_mutex_regs: syscon@1905000 {
283 compatible = "syscon";
284 reg = <0x1905000 0x20000>;
288 compatible = "qcom,tcsr-mutex";
289 syscon = <&tcsr_mutex_regs 0 0x1000>;
293 rpm_msg_ram: memory@60000 {
294 compatible = "qcom,rpm-msg-ram";
295 reg = <0x60000 0x8000>;
298 blsp1_uart1: serial@78af000 {
299 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
300 reg = <0x78af000 0x200>;
301 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
303 clock-names = "core", "iface";
304 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
305 dma-names = "rx", "tx";
309 apcs: syscon@b011000 {
310 compatible = "syscon";
311 reg = <0x0b011000 0x1000>;
314 a53cc: qcom,a53cc@0b016000 {
315 compatible = "qcom,clock-a53-msm8916";
316 reg = <0x0b016000 0x40>;
321 blsp1_uart2: serial@78b0000 {
322 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
323 reg = <0x78b0000 0x200>;
324 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
326 clock-names = "core", "iface";
327 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
328 dma-names = "rx", "tx";
332 blsp_dma: dma@7884000 {
333 compatible = "qcom,bam-v1.7.0";
334 reg = <0x07884000 0x23000>;
335 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
337 clock-names = "bam_clk";
343 blsp_spi1: spi@78b5000 {
344 compatible = "qcom,spi-qup-v2.2.1";
345 reg = <0x078b5000 0x600>;
346 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
348 <&gcc GCC_BLSP1_AHB_CLK>;
349 clock-names = "core", "iface";
350 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
351 dma-names = "rx", "tx";
352 pinctrl-names = "default", "sleep";
353 pinctrl-0 = <&spi1_default>;
354 pinctrl-1 = <&spi1_sleep>;
355 #address-cells = <1>;
360 blsp_spi2: spi@78b6000 {
361 compatible = "qcom,spi-qup-v2.2.1";
362 reg = <0x078b6000 0x600>;
363 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
365 <&gcc GCC_BLSP1_AHB_CLK>;
366 clock-names = "core", "iface";
367 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
368 dma-names = "rx", "tx";
369 pinctrl-names = "default", "sleep";
370 pinctrl-0 = <&spi2_default>;
371 pinctrl-1 = <&spi2_sleep>;
372 #address-cells = <1>;
377 blsp_spi3: spi@78b7000 {
378 compatible = "qcom,spi-qup-v2.2.1";
379 reg = <0x078b7000 0x600>;
380 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
382 <&gcc GCC_BLSP1_AHB_CLK>;
383 clock-names = "core", "iface";
384 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
385 dma-names = "rx", "tx";
386 pinctrl-names = "default", "sleep";
387 pinctrl-0 = <&spi3_default>;
388 pinctrl-1 = <&spi3_sleep>;
389 #address-cells = <1>;
394 blsp_spi4: spi@78b8000 {
395 compatible = "qcom,spi-qup-v2.2.1";
396 reg = <0x078b8000 0x600>;
397 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
399 <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", "iface";
401 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
402 dma-names = "rx", "tx";
403 pinctrl-names = "default", "sleep";
404 pinctrl-0 = <&spi4_default>;
405 pinctrl-1 = <&spi4_sleep>;
406 #address-cells = <1>;
411 blsp_spi5: spi@78b9000 {
412 compatible = "qcom,spi-qup-v2.2.1";
413 reg = <0x078b9000 0x600>;
414 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
416 <&gcc GCC_BLSP1_AHB_CLK>;
417 clock-names = "core", "iface";
418 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
419 dma-names = "rx", "tx";
420 pinctrl-names = "default", "sleep";
421 pinctrl-0 = <&spi5_default>;
422 pinctrl-1 = <&spi5_sleep>;
423 #address-cells = <1>;
428 blsp_spi6: spi@78ba000 {
429 compatible = "qcom,spi-qup-v2.2.1";
430 reg = <0x078ba000 0x600>;
431 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
433 <&gcc GCC_BLSP1_AHB_CLK>;
434 clock-names = "core", "iface";
435 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
436 dma-names = "rx", "tx";
437 pinctrl-names = "default", "sleep";
438 pinctrl-0 = <&spi6_default>;
439 pinctrl-1 = <&spi6_sleep>;
440 #address-cells = <1>;
445 blsp_i2c2: i2c@78b6000 {
446 compatible = "qcom,i2c-qup-v2.2.1";
447 reg = <0x78b6000 0x1000>;
448 interrupts = <GIC_SPI 96 0>;
449 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
450 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
451 clock-names = "iface", "core";
452 pinctrl-names = "default", "sleep";
453 pinctrl-0 = <&i2c2_default>;
454 pinctrl-1 = <&i2c2_sleep>;
455 #address-cells = <1>;
460 blsp_i2c4: i2c@78b8000 {
461 compatible = "qcom,i2c-qup-v2.2.1";
462 reg = <0x78b8000 0x1000>;
463 interrupts = <GIC_SPI 98 0>;
464 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
465 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
466 clock-names = "iface", "core";
467 pinctrl-names = "default", "sleep";
468 pinctrl-0 = <&i2c4_default>;
469 pinctrl-1 = <&i2c4_sleep>;
470 #address-cells = <1>;
475 blsp_i2c6: i2c@78ba000 {
476 compatible = "qcom,i2c-qup-v2.2.1";
477 reg = <0x78ba000 0x1000>;
478 interrupts = <GIC_SPI 100 0>;
479 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
480 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
481 clock-names = "iface", "core";
482 pinctrl-names = "default", "sleep";
483 pinctrl-0 = <&i2c6_default>;
484 pinctrl-1 = <&i2c6_sleep>;
485 #address-cells = <1>;
490 sdhc_1: sdhci@07824000 {
491 compatible = "qcom,sdhci-msm-v4";
492 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
493 reg-names = "hc_mem", "core_mem";
495 interrupts = <0 123 0>, <0 138 0>;
496 interrupt-names = "hc_irq", "pwr_irq";
497 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
498 <&gcc GCC_SDCC1_AHB_CLK>;
499 clock-names = "core", "iface";
505 sdhc_2: sdhci@07864000 {
506 compatible = "qcom,sdhci-msm-v4";
507 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
508 reg-names = "hc_mem", "core_mem";
510 interrupts = <0 125 0>, <0 221 0>;
511 interrupt-names = "hc_irq", "pwr_irq";
512 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
513 <&gcc GCC_SDCC2_AHB_CLK>;
514 clock-names = "core", "iface";
519 usb_dev: usb@78d9000 {
520 compatible = "qcom,ci-hdrc";
521 reg = <0x78d9000 0x400>;
522 dr_mode = "peripheral";
523 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
524 usb-phy = <&usb_otg>;
528 usb_host: ehci@78d9000 {
529 compatible = "qcom,ehci-host";
530 reg = <0x78d9000 0x400>;
531 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
532 usb-phy = <&usb_otg>;
536 usb_otg: phy@78d9000 {
537 compatible = "qcom,usb-otg-snps";
538 reg = <0x78d9000 0x400>;
539 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
540 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
542 v1p8-supply = <&pm8916_l7>;
543 v3p3-supply = <&pm8916_l13>;
544 qcom,vdd-levels = <1 5 7>;
545 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
546 dr_mode = "peripheral";
547 qcom,otg-control = <2>; // PMIC
550 qcom,msm-bus,name = "usb2";
551 qcom,msm-bus,num-cases = <3>;
552 qcom,msm-bus,num-paths = <1>;
553 qcom,msm-bus,vectors-KBps =
558 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
559 <&gcc GCC_USB_HS_SYSTEM_CLK>,
560 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
561 clock-names = "iface", "core", "sleep";
563 resets = <&gcc GCC_USB2A_PHY_BCR>,
564 <&gcc GCC_USB_HS_BCR>;
565 reset-names = "phy", "link";
569 intc: interrupt-controller@b000000 {
570 compatible = "qcom,msm-qgic2";
571 interrupt-controller;
572 #interrupt-cells = <3>;
573 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
576 l2ccc_0: clock-controller@b011000 {
577 compatible = "qcom,8916-l2ccc";
578 reg = <0x0b011000 0x1000>;
582 #address-cells = <1>;
585 compatible = "arm,armv7-timer-mem";
586 reg = <0xb020000 0x1000>;
587 clock-frequency = <19200000>;
591 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
593 reg = <0xb021000 0x1000>,
599 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
600 reg = <0xb023000 0x1000>;
606 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
607 reg = <0xb024000 0x1000>;
613 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
614 reg = <0xb025000 0x1000>;
620 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
621 reg = <0xb026000 0x1000>;
627 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
628 reg = <0xb027000 0x1000>;
634 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
635 reg = <0xb028000 0x1000>;
640 spmi_bus: spmi@200f000 {
641 compatible = "qcom,spmi-pmic-arb";
642 reg = <0x200f000 0x001000>,
643 <0x2400000 0x400000>,
644 <0x2c00000 0x400000>,
645 <0x3800000 0x200000>,
646 <0x200a000 0x002100>;
647 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
648 interrupt-names = "periph_irq";
649 interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
652 #address-cells = <2>;
654 interrupt-controller;
655 #interrupt-cells = <4>;
659 compatible = "qcom,prng";
660 reg = <0x00022000 0x200>;
661 clocks = <&gcc GCC_PRNG_AHB_CLK>;
662 clock-names = "core";
664 acc0: clock-controller@b088000 {
665 compatible = "qcom,arm-cortex-acc";
666 reg = <0x0b088000 0x1000>,
670 acc1: clock-controller@b098000 {
671 compatible = "qcom,arm-cortex-acc";
672 reg = <0x0b098000 0x1000>,
676 acc2: clock-controller@b0a8000 {
677 compatible = "qcom,arm-cortex-acc";
678 reg = <0x0b0a8000 0x1000>,
682 acc3: clock-controller@b0b8000 {
683 compatible = "qcom,arm-cortex-acc";
684 reg = <0x0b0b8000 0x1000>,
690 wcd_digital: codec-digital{
691 compatible = "syscon", "qcom,apq8016-wcd-digital-codec";
692 reg = <0x0771c000 0x400>;
695 lpass: lpass-cpu@07700000 {
697 compatible = "qcom,lpass-cpu-apq8016";
698 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
699 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
700 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
701 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
702 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
703 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
704 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
706 clock-names = "ahbix-clk",
713 #sound-dai-cells = <1>;
715 interrupts = <0 160 0>;
716 interrupt-names = "lpass-irq-lpaif";
717 reg = <0x07708000 0x10000>, <0x07702000 0x4>, <0x07702004 0x4>;
718 reg-names = "lpass-lpaif", "mic-iomux", "spkr-iomux";
723 compatible = "qcom,apq8016-sbc-sndcard";
724 reg = <0x07702000 0x4>, <0x07702004 0x4>;
725 reg-names = "mic-iomux", "spkr-iomux";
728 tcsr: syscon@1937000 {
729 compatible = "qcom,tcsr-msm8916", "syscon";
730 reg = <0x1937000 0x30000>;
733 uqfprom: eeprom@58000 {
734 compatible = "qcom,qfprom-msm8916";
735 reg = <0x58000 0x7000>;
739 compatible = "qcom,cpr";
740 reg = <0xb018000 0x1000>;
741 interrupts = <0 15 1>, <0 16 1>, <0 17 1>;
742 vdd-mx-supply = <&pm8916_l3>;
743 acc-syscon = <&tcsr>;
746 qcom,cpr-ref-clk = <19200>;
747 qcom,cpr-timer-delay-us = <5000>;
748 qcom,cpr-timer-cons-up = <0>;
749 qcom,cpr-timer-cons-down = <2>;
750 qcom,cpr-up-threshold = <0>;
751 qcom,cpr-down-threshold = <2>;
752 qcom,cpr-idle-clocks = <15>;
753 qcom,cpr-gcnt-us = <1>;
754 qcom,vdd-apc-step-up-limit = <1>;
755 qcom,vdd-apc-step-down-limit = <1>;
756 qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
759 qfprom: qfprom@5c000 {
760 compatible = "qcom,qfprom";
761 reg = <0x5c000 0x1000>;
762 #address-cells = <1>;
764 tsens_caldata: caldata@d0 {
767 tsens_calsel: calsel@ec {
772 tsens: thermal-sensor@4a8000 {
773 compatible = "qcom,msm8916-tsens";
774 reg = <0x4a8000 0x2000>;
775 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
776 nvmem-cell-names = "calib", "calib_sel";
777 qcom,tsens-slopes = <3200 3200 3200 3200 3200>;
778 qcom,sensor-id = <0 1 2 4 5>;
779 #thermal-sensor-cells = <1>;
783 compatible = "qcom,smp2p";
784 qcom,smem = <435>, <428>;
785 interrupts = <0 27 1>;
786 qcom,ipc = <&apcs 8 14>;
788 qcom,local-pid = <0>;
789 qcom,remote-pid = <1>;
791 q6_smp2p_out: master-kernel {
792 qcom,entry-name = "master-kernel";
799 q6_smp2p_in: slave-kernel {
800 qcom,entry-name = "slave-kernel";
803 interrupt-controller;
804 #interrupt-cells = <2>;
809 compatible = "qcom,smp2p";
810 qcom,smem = <451>, <431>;
812 interrupts = <0 143 1>;
814 qcom,ipc = <&apcs 8 18>;
816 qcom,local-pid = <0>;
817 qcom,remote-pid = <4>;
819 wcnss_smp2p_out: master-kernel {
820 qcom,entry-name = "master-kernel";
827 wcnss_smp2p_in: slave-kernel {
828 qcom,entry-name = "slave-kernel";
831 interrupt-controller;
832 #interrupt-cells = <2>;
837 compatible = "qcom,pil-q6v56-mss", "qcom,q6v5-pil";
838 reg = <0x04080000 0x100>,
846 reg-names = "qdsp6_base", "rmb_base", "restart_reg_sec",
847 "halt_q6", "halt_modem", "halt_nc";
849 interrupts-extended = <&intc 0 24 1>,
854 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
856 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>;
858 clock-names = "iface", "bus", "mem";
860 qcom,mx-supply = <&pm8916_l3>;
861 qcom,mx-uV = <1050000>;
862 qcom,pll-supply = <&pm8916_l7>;
863 qcom,pll-uV = <1800000>;
864 qcom,proxy-clock-names = "xo";
865 qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
867 qcom,firmware-name = "modem";
871 /* GPIO inputs from mss */
872 qcom,gpio-err-fatal = <&q6_smp2p_in 0 0>;
873 qcom,gpio-err-ready = <&q6_smp2p_in 1 0>;
874 qcom,gpio-proxy-unvote = <&q6_smp2p_in 2 0>;
875 qcom,gpio-stop-ack = <&q6_smp2p_in 3 0>;
876 qcom,gpio-ramdump-disable = <&q6_smp2p_in 15 0>;
877 /* GPIO output to mss */
878 qcom,gpio-force-stop = <&q6_smp2p_out 0 0>;
879 qcom,stop-gpio = <&q6_smp2p_out 0 0>;
880 memory-region = <&modem_adsp_mem>;
883 pronto_rproc:pronto_rproc {
884 compatible = "qcom,tz-pil";
886 interrupts-extended = <&intc 0 149 1>,
887 <&wcnss_smp2p_in 0 0>,
888 <&wcnss_smp2p_in 1 0>,
889 <&wcnss_smp2p_in 2 0>,
890 <&wcnss_smp2p_in 3 0>;
891 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
893 clocks = <&gcc GCC_CRYPTO_CLK>,
894 <&gcc GCC_CRYPTO_AHB_CLK>,
895 <&gcc GCC_CRYPTO_AXI_CLK>,
896 <&gcc CRYPTO_CLK_SRC>;
897 clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_src_clk";
899 qcom,firmware-name = "wcnss";
902 qcom,crash-reason = <422>;
903 qcom,smd-edges = <&pronto_smd_edge>;
905 qcom,pll-supply = <&pm8916_l7>;
906 qcom,pll-uV = <1800000>;
907 qcom,pll-uA = <18000>;
909 qcom,stop-gpio = <&wcnss_smp2p_out 0 0>;
911 pinctrl-names = "default";
912 pinctrl-0 = <&wcnss_default>;
914 memory-region = <&peripheral_mem>;
917 qcom,wcn36xx@0a000000 {
918 compatible = "qcom,wcn3620";
919 reg = <0x0a000000 0x280000>,
922 <0x03204000 0x00000100>,
923 <0x03200800 0x00000200>,
924 <0x0A100400 0x00000200>,
925 <0x0A205050 0x00000200>,
926 <0x0A219000 0x00000020>,
927 <0x0A080488 0x00000008>,
928 <0x0A080fb0 0x00000008>,
929 <0x0A08040c 0x00000008>,
930 <0x0A0120a8 0x00000008>,
931 <0x0A012448 0x00000008>,
932 <0x0A080c00 0x00000001>;
934 reg-names = "wcnss_mmio", "wcnss_fiq",
935 "pronto_phy_base", "riva_phy_base",
936 "riva_ccu_base", "pronto_a2xb_base",
937 "pronto_ccpu_base", "pronto_saw2_base",
938 "wlan_tx_phy_aborts","wlan_brdg_err_source",
939 "wlan_tx_status", "alarms_txctl",
940 "alarms_tactl", "pronto_mcu_base";
942 interrupts = <0 145 0 0 146 0>;
943 interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
945 // qcom,pronto-vddmx-supply = <&pm8916_l3>;
946 // qcom,pronto-vddcx-supply = <&pm8916_s1_corner>;
947 // qcom,pronto-vddpx-supply = <&pm8916_l7>;
948 // qcom,iris-vddxo-supply = <&pm8916_l7>;
949 // qcom,iris-vddrfa-supply = <&pm8916_s3>;
950 // qcom,iris-vddpa-supply = <&pm8916_l9>;
951 // qcom,iris-vdddig-supply = <&pm8916_l5>;
953 pinctrl-names = "wcnss_default";
954 // pinctrl-names = "wcnss_default", "wcnss_sleep",
955 // "wcnss_gpio_default";
956 pinctrl-0 = <&wcnss_default>;
957 // pinctrl-1 = <&wcnss_sleep>;
958 // pinctrl-2 = <&wcnss_gpio_default>;
960 // clocks = <&rpmcc RPM_XO_CLK_SRC>,
961 // <&rpmcc RPM_RF_CLK2>;
962 //clock-names = "xo", "rf_clk";
964 rproc = <&pronto_rproc>;
965 qcom,has-autodetect-xo;
966 qcom,wlan-rx-buff-count = <512>;
969 // qcom,wcnss-adc_tm = <&pm8916_adc_tm>;
974 qcom,rpm-log@29dc00 {
975 compatible = "qcom,rpm-log";
976 reg = <0x29dc00 0x4000>;
977 qcom,rpm-addr-phys = <0x200000>;
978 qcom,offset-version = <4>;
979 qcom,offset-page-buffer-addr = <36>;
980 qcom,offset-log-len = <40>;
981 qcom,offset-log-len-mask = <44>;
982 qcom,offset-page-indices = <56>;
985 vidc_rproc: vidc_tzpil@0 {
986 compatible = "qcom,tz-pil";
987 clocks = <&gcc GCC_CRYPTO_CLK>,
988 <&gcc GCC_CRYPTO_AHB_CLK>,
989 <&gcc GCC_CRYPTO_AXI_CLK>,
990 <&gcc CRYPTO_CLK_SRC>;
991 clock-names = "scm_core_clk", "scm_iface_clk",
992 "scm_bus_clk", "scm_src_clk";
993 qcom,firmware-name = "venus";
995 memory-region = <&vidc_mem>;
999 vidc: qcom,vidc@1d00000 {
1000 compatible = "qcom,msm-vidc";
1001 reg = <0x01d00000 0xff000>;
1002 interrupts = <GIC_SPI 44 0>;
1003 power-domains = <&gcc VENUS_GDSC>;
1004 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1005 <&gcc GCC_VENUS0_AHB_CLK>,
1006 <&gcc GCC_VENUS0_AXI_CLK>;
1007 clock-names = "core_clk", "iface_clk", "bus_clk";
1009 qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */
1010 qcom,enable-idle-indicator;
1011 rproc = <&vidc_rproc>;
1012 qcom,iommu-cb = <&venus_ns>,
1013 <&venus_sec_bitstream>,
1015 <&venus_sec_non_pixel>;
1016 status = "disabled";
1021 compatible = "qcom,smem";
1023 memory-region = <&smem_mem>;
1024 qcom,rpm-msg-ram = <&rpm_msg_ram>;
1026 hwlocks = <&tcsr_mutex 3>;
1029 compatible = "qcom,smd";
1032 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1033 qcom,ipc = <&apcs 8 0>;
1034 qcom,smd-edge = <15>;
1035 qcom,remote-pid = <0xffffffff>;
1038 compatible = "qcom,rpm-msm8916";
1039 qcom,smd-channels = "rpm_requests";
1041 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
1046 compatible = "qcom,rpm-msm-bus";
1049 compatible = "qcom,rpm-pm8916-regulators";
1079 interrupts = <0 25 1>;
1080 qcom,smd-edge = <0>;
1081 qcom,ipc = <&apcs 8 12>;
1082 qcom,remote-pid = <1>;
1084 compatible = "qcom,ipcrtr";
1085 qcom,smd-channels = "IPCRTR";
1089 pronto_smd_edge: pronto {
1090 interrupts = <0 142 1>;
1092 qcom,ipc = <&apcs 8 17>;
1093 qcom,smd-edge = <6>;
1094 qcom,remote-pid = <4>;
1097 compatible = "qcom,hci-smd";
1098 qcom,smd-channels = "APPS_RIVA_BT_CMD", "APPS_RIVA_BT_ACL";
1099 qcom,smd-channel-names = "event", "data";
1103 compatible = "qcom,ipcrtr";
1104 qcom,smd-channels = "IPCRTR";
1108 compatible = "qcom,wlan-ctrl";
1109 qcom,smd-channels = "WLAN_CTRL";
1111 interrupts = <0 145 0>, <0 146 0>;
1112 interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
1114 qcom,wcnss_mmio = <0xfb000000 0x21b000>;
1116 // qcom,tx-enable-gpios = <&apps_smsm 10 0>;
1117 // qcom,tx-rings-empty-gpios = <&apps_smsm 9 0>;
1121 compatible = "qcom,wcnss-ctrl";
1122 qcom,smd-channels = "WCNSS_CTRL";
1124 qcom,wcnss_mmio = <0xfb21b000 0x3000>;
1132 #include "msm8916-pins.dtsi"
1133 #include "msm8916-iommu.dtsi"
1134 #include "msm8916-coresight.dtsi"
1135 #include "msm8916-bus.dtsi"