arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17 #include <dt-bindings/arm/qcom-ids.h>
  18
  19 / {
  20         model = "Qualcomm Technologies, Inc. MSM8916";
  21         compatible = "qcom,msm8916";
  22         qcom,msm-id =   <QCOM_ID_MSM8916 0>,
  23                         <QCOM_ID_MSM8216 0>,
  24                         <QCOM_ID_MSM8116 0>,
  25                         <QCOM_ID_MSM8616 0>,
  26                         <QCOM_ID_APQ8016 0>;
  27
  28
  29         interrupt-parent = <&intc>;
  30
  31         #address-cells = <2>;
  32         #size-cells = <2>;
  33
  34         aliases {
  35                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  36                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  37         };
  38
  39         chosen { };
  40
  41         memory {
  42                 device_type = "memory";
  43                 /* We expect the bootloader to fill in the reg */
  44                 reg = <0 0 0 0>;
  45         };
  46
  47         reserved-memory {
  48                 #address-cells = <2>;
  49                 #size-cells = <2>;
  50                 ranges;
  51
  52                 reserve_aligned@86000000 {
  53                         reg = <0x0 0x86000000 0x0 0x0300000>;
  54                         no-map;
  55                 };
  56
  57                 smem_mem: smem_region@86300000 {
  58                         reg = <0x0 0x86300000 0x0 0x0100000>;
  59                         no-map;
  60                 };
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 CPU0: cpu@0 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a53", "arm,armv8";
  70                         reg = <0x0>;
  71                         enable-method = "qcom,arm-cortex-acc";
  72                         qcom,acc = <&acc0>;
  73                         next-level-cache = <&L2_0>;
  74                         L2_0: l2-cache {
  75                               compatible = "arm,arch-cache";
  76                               cache-level = <2>;
  77                               power-domain = <&l2ccc_0>;
  78                         };
  79                 };
  80
  81                 CPU1: cpu@1 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53", "arm,armv8";
  84                         reg = <0x1>;
  85                         enable-method = "qcom,arm-cortex-acc";
  86                         qcom,acc = <&acc1>;
  87                         next-level-cache = <&L2_0>;
  88                 };
  89
  90                 CPU2: cpu@2 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53", "arm,armv8";
  93                         reg = <0x2>;
  94                         enable-method = "qcom,arm-cortex-acc";
  95                         qcom,acc = <&acc2>;
  96                         next-level-cache = <&L2_0>;
  97                 };
  98
  99                 CPU3: cpu@3 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53", "arm,armv8";
 102                         reg = <0x3>;
 103                         enable-method = "qcom,arm-cortex-acc";
 104                         qcom,acc = <&acc3>;
 105                         next-level-cache = <&L2_0>;
 106                 };
 107         };
 108
 109         cpu-pmu {
 110                 compatible = "arm,armv8-pmuv3";
 111                 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
 112         };
 113
 114         timer {
 115                 compatible = "arm,armv8-timer";
 116                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 117                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 118                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 119                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 120         };
 121
 122         clocks {
 123                 xo_board: xo_board {
 124                         compatible = "fixed-clock";
 125                         #clock-cells = <0>;
 126                         clock-frequency = <19200000>;
 127                 };
 128
 129                 sleep_clk: sleep_clk {
 130                         compatible = "fixed-clock";
 131                         #clock-cells = <0>;
 132                         clock-frequency = <32768>;
 133                 };
 134         };
 135
 136         smem {
 137                 compatible = "qcom,smem";
 138
 139                 memory-region = <&smem_mem>;
 140                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 141
 142                 hwlocks = <&tcsr_mutex 3>;
 143         };
 144
 145         soc: soc {
 146                 #address-cells = <1>;
 147                 #size-cells = <1>;
 148                 ranges = <0 0 0 0xffffffff>;
 149                 compatible = "simple-bus";
 150
 151                 restart@4ab000 {
 152                         compatible = "qcom,pshold";
 153                         reg = <0x4ab000 0x4>;
 154                 };
 155
 156                 msmgpio: pinctrl@1000000 {
 157                         compatible = "qcom,msm8916-pinctrl";
 158                         reg = <0x1000000 0x300000>;
 159                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 160                         gpio-controller;
 161                         #gpio-cells = <2>;
 162                         interrupt-controller;
 163                         #interrupt-cells = <2>;
 164                 };
 165
 166                 gcc: qcom,gcc@1800000 {
 167                         compatible = "qcom,gcc-msm8916";
 168                         #clock-cells = <1>;
 169                         #reset-cells = <1>;
 170                         #power-domain-cells = <1>;
 171                         reg = <0x1800000 0x80000>;
 172                 };
 173
 174                 tcsr_mutex_regs: syscon@1905000 {
 175                         compatible = "syscon";
 176                         reg = <0x1905000 0x20000>;
 177                 };
 178
 179                 tcsr_mutex: hwlock {
 180                         compatible = "qcom,tcsr-mutex";
 181                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 182                         #hwlock-cells = <1>;
 183                 };
 184
 185                 rpm_msg_ram: memory@60000 {
 186                         compatible = "qcom,rpm-msg-ram";
 187                         reg = <0x60000 0x8000>;
 188                 };
 189
 190                 blsp1_uart1: serial@78af000 {
 191                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 192                         reg = <0x78af000 0x200>;
 193                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 194                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 195                         clock-names = "core", "iface";
 196                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 197                         dma-names = "rx", "tx";
 198                         status = "disabled";
 199                 };
 200
 201                 apcs: syscon@b011000 {
 202                         compatible = "syscon";
 203                         reg = <0x0b011000 0x1000>;
 204                 };
 205
 206                 blsp1_uart2: serial@78b0000 {
 207                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 208                         reg = <0x78b0000 0x200>;
 209                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 210                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 211                         clock-names = "core", "iface";
 212                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 213                         dma-names = "rx", "tx";
 214                         status = "disabled";
 215                 };
 216
 217                 blsp_dma: dma@7884000 {
 218                         compatible = "qcom,bam-v1.7.0";
 219                         reg = <0x07884000 0x23000>;
 220                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 222                         clock-names = "bam_clk";
 223                         #dma-cells = <1>;
 224                         qcom,ee = <0>;
 225                         status = "disabled";
 226                 };
 227
 228                 blsp_spi1: spi@78b5000 {
 229                         compatible = "qcom,spi-qup-v2.2.1";
 230                         reg = <0x078b5000 0x600>;
 231                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 233                                  <&gcc GCC_BLSP1_AHB_CLK>;
 234                         clock-names = "core", "iface";
 235                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 236                         dma-names = "rx", "tx";
 237                         pinctrl-names = "default", "sleep";
 238                         pinctrl-0 = <&spi1_default>;
 239                         pinctrl-1 = <&spi1_sleep>;
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         status = "disabled";
 243                 };
 244
 245                 blsp_spi2: spi@78b6000 {
 246                         compatible = "qcom,spi-qup-v2.2.1";
 247                         reg = <0x078b6000 0x600>;
 248                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 249                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 250                                  <&gcc GCC_BLSP1_AHB_CLK>;
 251                         clock-names = "core", "iface";
 252                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 253                         dma-names = "rx", "tx";
 254                         pinctrl-names = "default", "sleep";
 255                         pinctrl-0 = <&spi2_default>;
 256                         pinctrl-1 = <&spi2_sleep>;
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         status = "disabled";
 260                 };
 261
 262                 blsp_spi3: spi@78b7000 {
 263                         compatible = "qcom,spi-qup-v2.2.1";
 264                         reg = <0x078b7000 0x600>;
 265                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 266                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 267                                  <&gcc GCC_BLSP1_AHB_CLK>;
 268                         clock-names = "core", "iface";
 269                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 270                         dma-names = "rx", "tx";
 271                         pinctrl-names = "default", "sleep";
 272                         pinctrl-0 = <&spi3_default>;
 273                         pinctrl-1 = <&spi3_sleep>;
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         status = "disabled";
 277                 };
 278
 279                 blsp_spi4: spi@78b8000 {
 280                         compatible = "qcom,spi-qup-v2.2.1";
 281                         reg = <0x078b8000 0x600>;
 282                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 284                                  <&gcc GCC_BLSP1_AHB_CLK>;
 285                         clock-names = "core", "iface";
 286                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 287                         dma-names = "rx", "tx";
 288                         pinctrl-names = "default", "sleep";
 289                         pinctrl-0 = <&spi4_default>;
 290                         pinctrl-1 = <&spi4_sleep>;
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293                         status = "disabled";
 294                 };
 295
 296                 blsp_spi5: spi@78b9000 {
 297                         compatible = "qcom,spi-qup-v2.2.1";
 298                         reg = <0x078b9000 0x600>;
 299                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 300                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 301                                  <&gcc GCC_BLSP1_AHB_CLK>;
 302                         clock-names = "core", "iface";
 303                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 304                         dma-names = "rx", "tx";
 305                         pinctrl-names = "default", "sleep";
 306                         pinctrl-0 = <&spi5_default>;
 307                         pinctrl-1 = <&spi5_sleep>;
 308                         #address-cells = <1>;
 309                         #size-cells = <0>;
 310                         status = "disabled";
 311                 };
 312
 313                 blsp_spi6: spi@78ba000 {
 314                         compatible = "qcom,spi-qup-v2.2.1";
 315                         reg = <0x078ba000 0x600>;
 316                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 318                                  <&gcc GCC_BLSP1_AHB_CLK>;
 319                         clock-names = "core", "iface";
 320                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 321                         dma-names = "rx", "tx";
 322                         pinctrl-names = "default", "sleep";
 323                         pinctrl-0 = <&spi6_default>;
 324                         pinctrl-1 = <&spi6_sleep>;
 325                         #address-cells = <1>;
 326                         #size-cells = <0>;
 327                         status = "disabled";
 328                 };
 329
 330                 blsp_i2c2: i2c@78b6000 {
 331                         compatible = "qcom,i2c-qup-v2.2.1";
 332                         reg = <0x78b6000 0x1000>;
 333                         interrupts = <GIC_SPI 96 0>;
 334                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 335                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 336                         clock-names = "iface", "core";
 337                         pinctrl-names = "default", "sleep";
 338                         pinctrl-0 = <&i2c2_default>;
 339                         pinctrl-1 = <&i2c2_sleep>;
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                         status = "disabled";
 343                 };
 344
 345                 blsp_i2c4: i2c@78b8000 {
 346                         compatible = "qcom,i2c-qup-v2.2.1";
 347                         reg = <0x78b8000 0x1000>;
 348                         interrupts = <GIC_SPI 98 0>;
 349                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 350                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 351                         clock-names = "iface", "core";
 352                         pinctrl-names = "default", "sleep";
 353                         pinctrl-0 = <&i2c4_default>;
 354                         pinctrl-1 = <&i2c4_sleep>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         status = "disabled";
 358                 };
 359
 360                 blsp_i2c6: i2c@78ba000 {
 361                         compatible = "qcom,i2c-qup-v2.2.1";
 362                         reg = <0x78ba000 0x1000>;
 363                         interrupts = <GIC_SPI 100 0>;
 364                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 365                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 366                         clock-names = "iface", "core";
 367                         pinctrl-names = "default", "sleep";
 368                         pinctrl-0 = <&i2c6_default>;
 369                         pinctrl-1 = <&i2c6_sleep>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         status = "disabled";
 373                 };
 374
 375                 sdhc_1: sdhci@07824000 {
 376                         compatible = "qcom,sdhci-msm-v4";
 377                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 378                         reg-names = "hc_mem", "core_mem";
 379
 380                         interrupts = <0 123 0>, <0 138 0>;
 381                         interrupt-names = "hc_irq", "pwr_irq";
 382                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 383                                  <&gcc GCC_SDCC1_AHB_CLK>;
 384                         clock-names = "core", "iface";
 385                         bus-width = <8>;
 386                         non-removable;
 387                         status = "disabled";
 388                 };
 389
 390                 sdhc_2: sdhci@07864000 {
 391                         compatible = "qcom,sdhci-msm-v4";
 392                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 393                         reg-names = "hc_mem", "core_mem";
 394
 395                         interrupts = <0 125 0>, <0 221 0>;
 396                         interrupt-names = "hc_irq", "pwr_irq";
 397                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 398                                  <&gcc GCC_SDCC2_AHB_CLK>;
 399                         clock-names = "core", "iface";
 400                         bus-width = <4>;
 401                         status = "disabled";
 402                 };
 403
 404                 usb_dev: usb@78d9000 {
 405                         compatible = "qcom,ci-hdrc";
 406                         reg = <0x78d9000 0x400>;
 407                         dr_mode = "peripheral";
 408                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 409                         usb-phy = <&usb_otg>;
 410                         status = "disabled";
 411                 };
 412
 413                 usb_host: ehci@78d9000 {
 414                         compatible = "qcom,ehci-host";
 415                         reg = <0x78d9000 0x400>;
 416                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 417                         usb-phy = <&usb_otg>;
 418                         status = "disabled";
 419                 };
 420
 421                 usb_otg: phy@78d9000 {
 422                         compatible = "qcom,usb-otg-snps";
 423                         reg = <0x78d9000 0x400>;
 424                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 425                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 426
 427                         qcom,vdd-levels = <1 5 7>;
 428                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 429                         dr_mode = "peripheral";
 430                         qcom,otg-control = <2>; // PMIC
 431
 432                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 433                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 434                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 435                         clock-names = "iface", "core", "sleep";
 436
 437                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 438                                  <&gcc GCC_USB_HS_BCR>;
 439                         reset-names = "phy", "link";
 440                         status = "disabled";
 441                 };
 442
 443                 intc: interrupt-controller@b000000 {
 444                         compatible = "qcom,msm-qgic2";
 445                         interrupt-controller;
 446                         #interrupt-cells = <3>;
 447                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 448                 };
 449
 450                 l2ccc_0: clock-controller@b011000 {
 451                         compatible = "qcom,8916-l2ccc";
 452                         reg = <0x0b011000 0x1000>;
 453                 };
 454
 455                 timer@b020000 {
 456                         #address-cells = <1>;
 457                         #size-cells = <1>;
 458                         ranges;
 459                         compatible = "arm,armv7-timer-mem";
 460                         reg = <0xb020000 0x1000>;
 461                         clock-frequency = <19200000>;
 462
 463                         frame@b021000 {
 464                                 frame-number = <0>;
 465                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 466                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 467                                 reg = <0xb021000 0x1000>,
 468                                       <0xb022000 0x1000>;
 469                         };
 470
 471                         frame@b023000 {
 472                                 frame-number = <1>;
 473                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 474                                 reg = <0xb023000 0x1000>;
 475                                 status = "disabled";
 476                         };
 477
 478                         frame@b024000 {
 479                                 frame-number = <2>;
 480                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 481                                 reg = <0xb024000 0x1000>;
 482                                 status = "disabled";
 483                         };
 484
 485                         frame@b025000 {
 486                                 frame-number = <3>;
 487                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 488                                 reg = <0xb025000 0x1000>;
 489                                 status = "disabled";
 490                         };
 491
 492                         frame@b026000 {
 493                                 frame-number = <4>;
 494                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 495                                 reg = <0xb026000 0x1000>;
 496                                 status = "disabled";
 497                         };
 498
 499                         frame@b027000 {
 500                                 frame-number = <5>;
 501                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 502                                 reg = <0xb027000 0x1000>;
 503                                 status = "disabled";
 504                         };
 505
 506                         frame@b028000 {
 507                                 frame-number = <6>;
 508                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 509                                 reg = <0xb028000 0x1000>;
 510                                 status = "disabled";
 511                         };
 512                 };
 513
 514                 spmi_bus: spmi@200f000 {
 515                         compatible = "qcom,spmi-pmic-arb";
 516                         reg = <0x200f000 0x001000>,
 517                               <0x2400000 0x400000>,
 518                               <0x2c00000 0x400000>,
 519                               <0x3800000 0x200000>,
 520                               <0x200a000 0x002100>;
 521                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 522                         interrupt-names = "periph_irq";
 523                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 524                         qcom,ee = <0>;
 525                         qcom,channel = <0>;
 526                         #address-cells = <2>;
 527                         #size-cells = <0>;
 528                         interrupt-controller;
 529                         #interrupt-cells = <4>;
 530                 };
 531
 532                 rng@22000 {
 533                         compatible = "qcom,prng";
 534                         reg = <0x00022000 0x200>;
 535                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 536                         clock-names = "core";
 537                 };
 538                 acc0: clock-controller@b088000 {
 539                         compatible = "qcom,arm-cortex-acc";
 540                         reg = <0x0b088000 0x1000>,
 541                               <0x0b008000 0x1000>;
 542                 };
 543
 544                 acc1: clock-controller@b098000 {
 545                         compatible = "qcom,arm-cortex-acc";
 546                         reg = <0x0b098000 0x1000>,
 547                               <0x0b008000 0x1000>;
 548                 };
 549
 550                 acc2: clock-controller@b0a8000 {
 551                         compatible = "qcom,arm-cortex-acc";
 552                         reg = <0x0b0a8000 0x1000>,
 553                               <0x0b008000 0x1000>;
 554                 };
 555
 556                 acc3: clock-controller@b0b8000 {
 557                         compatible = "qcom,arm-cortex-acc";
 558                         reg = <0x0b0b8000 0x1000>,
 559                               <0x0b008000 0x1000>;
 560                 };
 561         };
 562
 563         smd {
 564                 compatible = "qcom,smd";
 565
 566                 rpm {
 567                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 568                         qcom,ipc = <&apcs 8 0>;
 569                         qcom,smd-edge = <15>;
 570
 571                         rpm_requests {
 572                                 compatible = "qcom,rpm-msm8916";
 573                                 qcom,smd-channels = "rpm_requests";
 574
 575                                 pm8916-regulators {
 576                                         compatible = "qcom,rpm-pm8916-regulators";
 577
 578                                         pm8916_s1: s1 {};
 579                                         pm8916_s2: s2 {};
 580                                         pm8916_s3: s3 {};
 581                                         pm8916_s4: s4 {};
 582
 583                                         pm8916_l1: l1 {};
 584                                         pm8916_l2: l2 {};
 585                                         pm8916_l3: l3 {};
 586                                         pm8916_l4: l4 {};
 587                                         pm8916_l5: l5 {};
 588                                         pm8916_l6: l6 {};
 589                                         pm8916_l7: l7 {};
 590                                         pm8916_l8: l8 {};
 591                                         pm8916_l9: l9 {};
 592                                         pm8916_l10: l10 {};
 593                                         pm8916_l11: l11 {};
 594                                         pm8916_l12: l12 {};
 595                                         pm8916_l13: l13 {};
 596                                         pm8916_l14: l14 {};
 597                                         pm8916_l15: l15 {};
 598                                         pm8916_l16: l16 {};
 599                                         pm8916_l17: l17 {};
 600                                         pm8916_l18: l18 {};
 601                                 };
 602                         };
 603                 };
 604         };
 605 };
 606
 607 #include "msm8916-pins.dtsi"