arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8916";
  20         compatible = "qcom,msm8916";
  21
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  29                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  30         };
  31
  32         chosen { };
  33
  34         memory {
  35                 device_type = "memory";
  36                 /* We expect the bootloader to fill in the reg */
  37                 reg = <0 0 0 0>;
  38         };
  39
  40         cpus {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 CPU0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53", "arm,armv8";
  47                         reg = <0x0>;
  48                 };
  49
  50                 CPU1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         reg = <0x1>;
  54                 };
  55
  56                 CPU2: cpu@2 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a53", "arm,armv8";
  59                         reg = <0x2>;
  60                 };
  61
  62                 CPU3: cpu@3 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x3>;
  66                 };
  67         };
  68
  69         timer {
  70                 compatible = "arm,armv8-timer";
  71                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  72                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  75         };
  76
  77         clocks {
  78                 xo_board: xo_board {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <19200000>;
  82                 };
  83
  84                 sleep_clk: sleep_clk {
  85                         compatible = "fixed-clock";
  86                         #clock-cells = <0>;
  87                         clock-frequency = <32768>;
  88                 };
  89         };
  90
  91         soc: soc {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges = <0 0 0 0xffffffff>;
  95                 compatible = "simple-bus";
  96
  97                 restart@4ab000 {
  98                         compatible = "qcom,pshold";
  99                         reg = <0x4ab000 0x4>;
 100                 };
 101
 102                 msmgpio: pinctrl@1000000 {
 103                         compatible = "qcom,msm8916-pinctrl";
 104                         reg = <0x1000000 0x300000>;
 105                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 106                         gpio-controller;
 107                         #gpio-cells = <2>;
 108                         interrupt-controller;
 109                         #interrupt-cells = <2>;
 110                 };
 111
 112                 gcc: qcom,gcc@1800000 {
 113                         compatible = "qcom,gcc-msm8916";
 114                         #clock-cells = <1>;
 115                         #reset-cells = <1>;
 116                         #power-domain-cells = <1>;
 117                         reg = <0x1800000 0x80000>;
 118                 };
 119
 120                 blsp1_uart1: serial@78af000 {
 121                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 122                         reg = <0x78af000 0x200>;
 123                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 124                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 125                         clock-names = "core", "iface";
 126                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 127                         dma-names = "rx", "tx";
 128                         status = "disabled";
 129                 };
 130
 131                 blsp1_uart2: serial@78b0000 {
 132                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 133                         reg = <0x78b0000 0x200>;
 134                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 135                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 136                         clock-names = "core", "iface";
 137                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 138                         dma-names = "rx", "tx";
 139                         status = "disabled";
 140                 };
 141
 142                 blsp_dma: dma@7884000 {
 143                         compatible = "qcom,bam-v1.7.0";
 144                         reg = <0x07884000 0x23000>;
 145                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 146                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 147                         clock-names = "bam_clk";
 148                         #dma-cells = <1>;
 149                         qcom,ee = <0>;
 150                         status = "disabled";
 151                 };
 152
 153                 blsp_spi1: spi@78b5000 {
 154                         compatible = "qcom,spi-qup-v2.2.1";
 155                         reg = <0x078b5000 0x600>;
 156                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 157                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 158                                  <&gcc GCC_BLSP1_AHB_CLK>;
 159                         clock-names = "core", "iface";
 160                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 161                         dma-names = "rx", "tx";
 162                         pinctrl-names = "default", "sleep";
 163                         pinctrl-0 = <&spi1_default>;
 164                         pinctrl-1 = <&spi1_sleep>;
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         status = "disabled";
 168                 };
 169
 170                 blsp_spi2: spi@78b6000 {
 171                         compatible = "qcom,spi-qup-v2.2.1";
 172                         reg = <0x078b6000 0x600>;
 173                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 174                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 175                                  <&gcc GCC_BLSP1_AHB_CLK>;
 176                         clock-names = "core", "iface";
 177                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 178                         dma-names = "rx", "tx";
 179                         pinctrl-names = "default", "sleep";
 180                         pinctrl-0 = <&spi2_default>;
 181                         pinctrl-1 = <&spi2_sleep>;
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         status = "disabled";
 185                 };
 186
 187                 blsp_spi3: spi@78b7000 {
 188                         compatible = "qcom,spi-qup-v2.2.1";
 189                         reg = <0x078b7000 0x600>;
 190                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 192                                  <&gcc GCC_BLSP1_AHB_CLK>;
 193                         clock-names = "core", "iface";
 194                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 195                         dma-names = "rx", "tx";
 196                         pinctrl-names = "default", "sleep";
 197                         pinctrl-0 = <&spi3_default>;
 198                         pinctrl-1 = <&spi3_sleep>;
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201                         status = "disabled";
 202                 };
 203
 204                 blsp_spi4: spi@78b8000 {
 205                         compatible = "qcom,spi-qup-v2.2.1";
 206                         reg = <0x078b8000 0x600>;
 207                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 208                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 209                                  <&gcc GCC_BLSP1_AHB_CLK>;
 210                         clock-names = "core", "iface";
 211                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 212                         dma-names = "rx", "tx";
 213                         pinctrl-names = "default", "sleep";
 214                         pinctrl-0 = <&spi4_default>;
 215                         pinctrl-1 = <&spi4_sleep>;
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                         status = "disabled";
 219                 };
 220
 221                 blsp_spi5: spi@78b9000 {
 222                         compatible = "qcom,spi-qup-v2.2.1";
 223                         reg = <0x078b9000 0x600>;
 224                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 225                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 226                                  <&gcc GCC_BLSP1_AHB_CLK>;
 227                         clock-names = "core", "iface";
 228                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 229                         dma-names = "rx", "tx";
 230                         pinctrl-names = "default", "sleep";
 231                         pinctrl-0 = <&spi5_default>;
 232                         pinctrl-1 = <&spi5_sleep>;
 233                         #address-cells = <1>;
 234                         #size-cells = <0>;
 235                         status = "disabled";
 236                 };
 237
 238                 blsp_spi6: spi@78ba000 {
 239                         compatible = "qcom,spi-qup-v2.2.1";
 240                         reg = <0x078ba000 0x600>;
 241                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 242                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 243                                  <&gcc GCC_BLSP1_AHB_CLK>;
 244                         clock-names = "core", "iface";
 245                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 246                         dma-names = "rx", "tx";
 247                         pinctrl-names = "default", "sleep";
 248                         pinctrl-0 = <&spi6_default>;
 249                         pinctrl-1 = <&spi6_sleep>;
 250                         #address-cells = <1>;
 251                         #size-cells = <0>;
 252                         status = "disabled";
 253                 };
 254
 255                 blsp_i2c2: i2c@78b6000 {
 256                         compatible = "qcom,i2c-qup-v2.2.1";
 257                         reg = <0x78b6000 0x1000>;
 258                         interrupts = <GIC_SPI 96 0>;
 259                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 260                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 261                         clock-names = "iface", "core";
 262                         pinctrl-names = "default", "sleep";
 263                         pinctrl-0 = <&i2c2_default>;
 264                         pinctrl-1 = <&i2c2_sleep>;
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         status = "disabled";
 268                 };
 269
 270                 blsp_i2c4: i2c@78b8000 {
 271                         compatible = "qcom,i2c-qup-v2.2.1";
 272                         reg = <0x78b8000 0x1000>;
 273                         interrupts = <GIC_SPI 98 0>;
 274                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 275                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 276                         clock-names = "iface", "core";
 277                         pinctrl-names = "default", "sleep";
 278                         pinctrl-0 = <&i2c4_default>;
 279                         pinctrl-1 = <&i2c4_sleep>;
 280                         #address-cells = <1>;
 281                         #size-cells = <0>;
 282                         status = "disabled";
 283                 };
 284
 285                 blsp_i2c6: i2c@78ba000 {
 286                         compatible = "qcom,i2c-qup-v2.2.1";
 287                         reg = <0x78ba000 0x1000>;
 288                         interrupts = <GIC_SPI 100 0>;
 289                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 290                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 291                         clock-names = "iface", "core";
 292                         pinctrl-names = "default", "sleep";
 293                         pinctrl-0 = <&i2c6_default>;
 294                         pinctrl-1 = <&i2c6_sleep>;
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         status = "disabled";
 298                 };
 299
 300                 sdhc_1: sdhci@07824000 {
 301                         compatible = "qcom,sdhci-msm-v4";
 302                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 303                         reg-names = "hc_mem", "core_mem";
 304
 305                         interrupts = <0 123 0>, <0 138 0>;
 306                         interrupt-names = "hc_irq", "pwr_irq";
 307                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 308                                  <&gcc GCC_SDCC1_AHB_CLK>;
 309                         clock-names = "core", "iface";
 310                         bus-width = <8>;
 311                         non-removable;
 312                         status = "disabled";
 313                 };
 314
 315                 sdhc_2: sdhci@07864000 {
 316                         compatible = "qcom,sdhci-msm-v4";
 317                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 318                         reg-names = "hc_mem", "core_mem";
 319
 320                         interrupts = <0 125 0>, <0 221 0>;
 321                         interrupt-names = "hc_irq", "pwr_irq";
 322                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 323                                  <&gcc GCC_SDCC2_AHB_CLK>;
 324                         clock-names = "core", "iface";
 325                         bus-width = <4>;
 326                         status = "disabled";
 327                 };
 328
 329                 usb_dev: usb@78d9000 {
 330                         compatible = "qcom,ci-hdrc";
 331                         reg = <0x78d9000 0x400>;
 332                         dr_mode = "peripheral";
 333                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 334                         usb-phy = <&usb_otg>;
 335                         status = "disabled";
 336                 };
 337
 338                 usb_host: ehci@78d9000 {
 339                         compatible = "qcom,ehci-host";
 340                         reg = <0x78d9000 0x400>;
 341                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 342                         usb-phy = <&usb_otg>;
 343                         status = "disabled";
 344                 };
 345
 346                 usb_otg: phy@78d9000 {
 347                         compatible = "qcom,usb-otg-snps";
 348                         reg = <0x78d9000 0x400>;
 349                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 350                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 351
 352                         qcom,vdd-levels = <1 5 7>;
 353                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 354                         dr_mode = "peripheral";
 355                         qcom,otg-control = <2>; // PMIC
 356
 357                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 358                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 359                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 360                         clock-names = "iface", "core", "sleep";
 361
 362                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 363                                  <&gcc GCC_USB_HS_BCR>;
 364                         reset-names = "phy", "link";
 365                         status = "disabled";
 366                 };
 367
 368                 intc: interrupt-controller@b000000 {
 369                         compatible = "qcom,msm-qgic2";
 370                         interrupt-controller;
 371                         #interrupt-cells = <3>;
 372                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 373                 };
 374
 375                 timer@b020000 {
 376                         #address-cells = <1>;
 377                         #size-cells = <1>;
 378                         ranges;
 379                         compatible = "arm,armv7-timer-mem";
 380                         reg = <0xb020000 0x1000>;
 381                         clock-frequency = <19200000>;
 382
 383                         frame@b021000 {
 384                                 frame-number = <0>;
 385                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 386                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 387                                 reg = <0xb021000 0x1000>,
 388                                       <0xb022000 0x1000>;
 389                         };
 390
 391                         frame@b023000 {
 392                                 frame-number = <1>;
 393                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 394                                 reg = <0xb023000 0x1000>;
 395                                 status = "disabled";
 396                         };
 397
 398                         frame@b024000 {
 399                                 frame-number = <2>;
 400                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 401                                 reg = <0xb024000 0x1000>;
 402                                 status = "disabled";
 403                         };
 404
 405                         frame@b025000 {
 406                                 frame-number = <3>;
 407                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 408                                 reg = <0xb025000 0x1000>;
 409                                 status = "disabled";
 410                         };
 411
 412                         frame@b026000 {
 413                                 frame-number = <4>;
 414                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 415                                 reg = <0xb026000 0x1000>;
 416                                 status = "disabled";
 417                         };
 418
 419                         frame@b027000 {
 420                                 frame-number = <5>;
 421                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 422                                 reg = <0xb027000 0x1000>;
 423                                 status = "disabled";
 424                         };
 425
 426                         frame@b028000 {
 427                                 frame-number = <6>;
 428                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 429                                 reg = <0xb028000 0x1000>;
 430                                 status = "disabled";
 431                         };
 432                 };
 433
 434                 spmi_bus: spmi@200f000 {
 435                         compatible = "qcom,spmi-pmic-arb";
 436                         reg = <0x200f000 0x001000>,
 437                               <0x2400000 0x400000>,
 438                               <0x2c00000 0x400000>,
 439                               <0x3800000 0x200000>,
 440                               <0x200a000 0x002100>;
 441                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 442                         interrupt-names = "periph_irq";
 443                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 444                         qcom,ee = <0>;
 445                         qcom,channel = <0>;
 446                         #address-cells = <2>;
 447                         #size-cells = <0>;
 448                         interrupt-controller;
 449                         #interrupt-cells = <4>;
 450                 };
 451
 452                 rng@22000 {
 453                         compatible = "qcom,prng";
 454                         reg = <0x00022000 0x200>;
 455                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 456                         clock-names = "core";
 457                 };
 458         };
 459 };
 460
 461 #include "msm8916-pins.dtsi"