1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
18 model = "Qualcomm Technologies, Inc. MSM8996";
20 interrupt-parent = <&intc>;
28 device_type = "memory";
29 /* We expect the bootloader to fill in the reg */
39 compatible = "qcom,kryo";
41 enable-method = "psci";
42 next-level-cache = <&L2_0>;
51 compatible = "qcom,kryo";
53 enable-method = "psci";
54 next-level-cache = <&L2_0>;
59 compatible = "qcom,kryo";
61 enable-method = "psci";
62 next-level-cache = <&L2_1>;
71 compatible = "qcom,kryo";
73 enable-method = "psci";
74 next-level-cache = <&L2_1>;
101 compatible = "arm,armv8-timer";
102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
104 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
105 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
110 compatible = "fixed-clock";
112 clock-frequency = <19200000>;
113 clock-output-names = "xo_board";
117 compatible = "fixed-clock";
119 clock-frequency = <32764>;
120 clock-output-names = "sleep_clk";
125 compatible = "arm,psci-1.0";
130 #address-cells = <1>;
132 ranges = <0 0 0 0xffffffff>;
133 compatible = "simple-bus";
135 intc: interrupt-controller@9bc0000 {
136 compatible = "arm,gic-v3";
137 #interrupt-cells = <3>;
138 interrupt-controller;
139 #redistributor-regions = <1>;
140 redistributor-stride = <0x0 0x40000>;
141 reg = <0x09bc0000 0x10000>,
142 <0x09c00000 0x100000>;
143 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
146 gcc: clock-controller@300000 {
147 compatible = "qcom,gcc-msm8996";
150 reg = <0x300000 0x90000>;
153 blsp2_uart1: serial@75b0000 {
154 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
155 reg = <0x75b0000 0x1000>;
156 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
158 <&gcc GCC_BLSP2_AHB_CLK>;
159 clock-names = "core", "iface";
164 compatible = "qcom,msm8996-pinctrl";
165 reg = <0x01010000 0x300000>;
166 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
169 interrupt-controller;
170 #interrupt-cells = <2>;
174 #address-cells = <1>;
177 compatible = "arm,armv7-timer-mem";
178 reg = <0x09840000 0x1000>;
179 clock-frequency = <19200000>;
183 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
185 reg = <0x09850000 0x1000>,
191 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
192 reg = <0x09870000 0x1000>;
198 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
199 reg = <0x09880000 0x1000>;
205 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
206 reg = <0x09890000 0x1000>;
212 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
213 reg = <0x098a0000 0x1000>;
219 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
220 reg = <0x098b0000 0x1000>;
226 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
227 reg = <0x098c0000 0x1000>;
232 spmi_bus: qcom,spmi@400f000 {
233 compatible = "qcom,spmi-pmic-arb";
234 reg = <0x400f000 0x1000>,
235 <0x4400000 0x800000>,
236 <0x4c00000 0x800000>,
237 <0x5800000 0x200000>,
238 <0x400a000 0x002100>;
239 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
240 interrupt-names = "periph_irq";
241 interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
244 #address-cells = <2>;
246 interrupt-controller;
247 #interrupt-cells = <4>;
250 mmcc: clock-controller@8c0000 {
251 compatible = "qcom,mmcc-msm8996";
254 reg = <0x8c0000 0x40000>;
255 assigned-clocks = <&mmcc MMPLL9_PLL>,
260 assigned-clock-rates = <624000000>,