2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
51 compatible = "rockchip,rk3368";
52 interrupt-parent = <&gic>;
75 #address-cells = <0x2>;
111 entry-method = "psci";
113 cpu_sleep: cpu-sleep-0 {
114 compatible = "arm,idle-state";
115 arm,psci-suspend-param = <0x1010000>;
116 entry-latency-us = <0x3fffffff>;
117 exit-latency-us = <0x40000000>;
118 min-residency-us = <0xffffffff>;
124 compatible = "arm,cortex-a53", "arm,armv8";
126 cpu-idle-states = <&cpu_sleep>;
127 enable-method = "psci";
129 #cooling-cells = <2>; /* min followed by max */
134 compatible = "arm,cortex-a53", "arm,armv8";
136 cpu-idle-states = <&cpu_sleep>;
137 enable-method = "psci";
142 compatible = "arm,cortex-a53", "arm,armv8";
144 cpu-idle-states = <&cpu_sleep>;
145 enable-method = "psci";
150 compatible = "arm,cortex-a53", "arm,armv8";
152 cpu-idle-states = <&cpu_sleep>;
153 enable-method = "psci";
158 compatible = "arm,cortex-a53", "arm,armv8";
160 cpu-idle-states = <&cpu_sleep>;
161 enable-method = "psci";
163 #cooling-cells = <2>; /* min followed by max */
168 compatible = "arm,cortex-a53", "arm,armv8";
170 cpu-idle-states = <&cpu_sleep>;
171 enable-method = "psci";
176 compatible = "arm,cortex-a53", "arm,armv8";
178 cpu-idle-states = <&cpu_sleep>;
179 enable-method = "psci";
184 compatible = "arm,cortex-a53", "arm,armv8";
186 cpu-idle-states = <&cpu_sleep>;
187 enable-method = "psci";
192 compatible = "arm,armv8-pmuv3";
193 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
202 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
203 <&cpu_b2>, <&cpu_b3>;
207 compatible = "arm,psci-0.2";
212 compatible = "arm,armv8-timer";
213 interrupts = <GIC_PPI 13
214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
216 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
218 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
220 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
224 compatible = "fixed-clock";
225 clock-frequency = <24000000>;
226 clock-output-names = "xin24m";
230 sdmmc: dwmmc@ff0c0000 {
231 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
232 reg = <0x0 0xff0c0000 0x0 0x4000>;
233 clock-freq-min-max = <400000 150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
235 clock-names = "biu", "ciu";
236 fifo-depth = <0x100>;
237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
241 sdio0: dwmmc@ff0d0000 {
242 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
243 reg = <0x0 0xff0d0000 0x0 0x4000>;
244 clock-freq-min-max = <400000 150000000>;
245 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
246 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
253 emmc: dwmmc@ff0f0000 {
254 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
255 reg = <0x0 0xff0f0000 0x0 0x4000>;
256 clock-freq-min-max = <400000 150000000>;
257 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
258 clock-names = "biu", "ciu";
259 fifo-depth = <0x100>;
260 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
264 saradc: saradc@ff100000 {
265 compatible = "rockchip,saradc";
266 reg = <0x0 0xff100000 0x0 0x100>;
267 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
268 #io-channel-cells = <1>;
269 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
270 clock-names = "saradc", "apb_pclk";
275 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
276 reg = <0x0 0xff110000 0x0 0x1000>;
277 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
278 clock-names = "spiclk", "apb_pclk";
279 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
282 #address-cells = <1>;
288 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
289 reg = <0x0 0xff120000 0x0 0x1000>;
290 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
291 clock-names = "spiclk", "apb_pclk";
292 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
295 #address-cells = <1>;
301 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
302 reg = <0x0 0xff130000 0x0 0x1000>;
303 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
304 clock-names = "spiclk", "apb_pclk";
305 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
308 #address-cells = <1>;
314 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
315 reg = <0x0 0xff140000 0x0 0x1000>;
316 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
317 #address-cells = <1>;
320 clocks = <&cru PCLK_I2C1>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&i2c1_xfer>;
327 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
328 reg = <0x0 0xff150000 0x0 0x1000>;
329 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
330 #address-cells = <1>;
333 clocks = <&cru PCLK_I2C3>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&i2c3_xfer>;
340 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
341 reg = <0x0 0xff160000 0x0 0x1000>;
342 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
346 clocks = <&cru PCLK_I2C4>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&i2c4_xfer>;
353 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
354 reg = <0x0 0xff170000 0x0 0x1000>;
355 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
356 #address-cells = <1>;
359 clocks = <&cru PCLK_I2C5>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c5_xfer>;
365 uart0: serial@ff180000 {
366 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
367 reg = <0x0 0xff180000 0x0 0x100>;
368 clock-frequency = <24000000>;
369 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
370 clock-names = "baudclk", "apb_pclk";
371 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
377 uart1: serial@ff190000 {
378 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
379 reg = <0x0 0xff190000 0x0 0x100>;
380 clock-frequency = <24000000>;
381 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
382 clock-names = "baudclk", "apb_pclk";
383 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
389 uart3: serial@ff1b0000 {
390 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
391 reg = <0x0 0xff1b0000 0x0 0x100>;
392 clock-frequency = <24000000>;
393 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
394 clock-names = "baudclk", "apb_pclk";
395 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
401 uart4: serial@ff1c0000 {
402 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
403 reg = <0x0 0xff1c0000 0x0 0x100>;
404 clock-frequency = <24000000>;
405 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
406 clock-names = "baudclk", "apb_pclk";
407 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
414 #include "rk3368-thermal.dtsi"
417 tsadc: tsadc@ff280000 {
418 compatible = "rockchip,rk3368-tsadc";
419 reg = <0x0 0xff280000 0x0 0x100>;
420 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
422 clock-names = "tsadc", "apb_pclk";
423 resets = <&cru SRST_TSADC>;
424 reset-names = "tsadc-apb";
425 pinctrl-names = "init", "default", "sleep";
426 pinctrl-0 = <&otp_gpio>;
427 pinctrl-1 = <&otp_out>;
428 pinctrl-2 = <&otp_gpio>;
429 #thermal-sensor-cells = <1>;
430 rockchip,hw-tshut-temp = <95000>;
434 gmac: ethernet@ff290000 {
435 compatible = "rockchip,rk3368-gmac";
436 reg = <0x0 0xff290000 0x0 0x10000>;
437 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
438 interrupt-names = "macirq";
439 rockchip,grf = <&grf>;
440 clocks = <&cru SCLK_MAC>,
441 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
442 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
443 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
444 clock-names = "stmmaceth",
445 "mac_clk_rx", "mac_clk_tx",
446 "clk_mac_ref", "clk_mac_refout",
447 "aclk_mac", "pclk_mac";
451 usb_host0_ehci: usb@ff500000 {
452 compatible = "generic-ehci";
453 reg = <0x0 0xff500000 0x0 0x100>;
454 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru HCLK_HOST0>;
456 clock-names = "usbhost";
460 usb_otg: usb@ff580000 {
461 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
463 reg = <0x0 0xff580000 0x0 0x40000>;
464 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cru HCLK_OTG0>;
468 g-np-tx-fifo-size = <16>;
469 g-rx-fifo-size = <275>;
470 g-tx-fifo-size = <256 128 128 64 64 32>;
476 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
477 reg = <0x0 0xff650000 0x0 0x1000>;
478 clocks = <&cru PCLK_I2C0>;
480 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&i2c0_xfer>;
483 #address-cells = <1>;
489 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
490 reg = <0x0 0xff660000 0x0 0x1000>;
491 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
492 #address-cells = <1>;
495 clocks = <&cru PCLK_I2C2>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&i2c2_xfer>;
502 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
503 reg = <0x0 0xff680000 0x0 0x10>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&pwm0_pin>;
507 clocks = <&cru PCLK_PWM1>;
513 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
514 reg = <0x0 0xff680010 0x0 0x10>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&pwm1_pin>;
518 clocks = <&cru PCLK_PWM1>;
524 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
525 reg = <0x0 0xff680020 0x0 0x10>;
527 clocks = <&cru PCLK_PWM1>;
533 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
534 reg = <0x0 0xff680030 0x0 0x10>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&pwm3_pin>;
538 clocks = <&cru PCLK_PWM1>;
543 uart2: serial@ff690000 {
544 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
545 reg = <0x0 0xff690000 0x0 0x100>;
546 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
547 clock-names = "baudclk", "apb_pclk";
548 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&uart2_xfer>;
556 pmugrf: syscon@ff738000 {
557 compatible = "rockchip,rk3368-pmugrf", "syscon";
558 reg = <0x0 0xff738000 0x0 0x1000>;
561 cru: clock-controller@ff760000 {
562 compatible = "rockchip,rk3368-cru";
563 reg = <0x0 0xff760000 0x0 0x1000>;
564 rockchip,grf = <&grf>;
569 grf: syscon@ff770000 {
570 compatible = "rockchip,rk3368-grf", "syscon";
571 reg = <0x0 0xff770000 0x0 0x1000>;
574 wdt: watchdog@ff800000 {
575 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
576 reg = <0x0 0xff800000 0x0 0x100>;
577 clocks = <&cru PCLK_WDT>;
578 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
583 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
584 reg = <0x0 0xff810000 0x0 0x20>;
585 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
588 gic: interrupt-controller@ffb71000 {
589 compatible = "arm,gic-400";
590 interrupt-controller;
591 #interrupt-cells = <3>;
592 #address-cells = <0>;
594 reg = <0x0 0xffb71000 0x0 0x1000>,
595 <0x0 0xffb72000 0x0 0x1000>,
596 <0x0 0xffb74000 0x0 0x2000>,
597 <0x0 0xffb76000 0x0 0x2000>;
598 interrupts = <GIC_PPI 9
599 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
603 compatible = "rockchip,rk3368-pinctrl";
604 rockchip,grf = <&grf>;
605 rockchip,pmu = <&pmugrf>;
606 #address-cells = <0x2>;
610 gpio0: gpio0@ff750000 {
611 compatible = "rockchip,gpio-bank";
612 reg = <0x0 0xff750000 0x0 0x100>;
613 clocks = <&cru PCLK_GPIO0>;
614 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
619 interrupt-controller;
620 #interrupt-cells = <0x2>;
623 gpio1: gpio1@ff780000 {
624 compatible = "rockchip,gpio-bank";
625 reg = <0x0 0xff780000 0x0 0x100>;
626 clocks = <&cru PCLK_GPIO1>;
627 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
632 interrupt-controller;
633 #interrupt-cells = <0x2>;
636 gpio2: gpio2@ff790000 {
637 compatible = "rockchip,gpio-bank";
638 reg = <0x0 0xff790000 0x0 0x100>;
639 clocks = <&cru PCLK_GPIO2>;
640 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
645 interrupt-controller;
646 #interrupt-cells = <0x2>;
649 gpio3: gpio3@ff7a0000 {
650 compatible = "rockchip,gpio-bank";
651 reg = <0x0 0xff7a0000 0x0 0x100>;
652 clocks = <&cru PCLK_GPIO3>;
653 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
658 interrupt-controller;
659 #interrupt-cells = <0x2>;
662 pcfg_pull_up: pcfg-pull-up {
666 pcfg_pull_down: pcfg-pull-down {
670 pcfg_pull_none: pcfg-pull-none {
674 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
676 drive-strength = <12>;
681 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
685 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
689 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
692 emmc_bus1: emmc-bus1 {
693 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
696 emmc_bus4: emmc-bus4 {
697 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
698 <1 19 RK_FUNC_2 &pcfg_pull_up>,
699 <1 20 RK_FUNC_2 &pcfg_pull_up>,
700 <1 21 RK_FUNC_2 &pcfg_pull_up>;
703 emmc_bus8: emmc-bus8 {
704 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
705 <1 19 RK_FUNC_2 &pcfg_pull_up>,
706 <1 20 RK_FUNC_2 &pcfg_pull_up>,
707 <1 21 RK_FUNC_2 &pcfg_pull_up>,
708 <1 22 RK_FUNC_2 &pcfg_pull_up>,
709 <1 23 RK_FUNC_2 &pcfg_pull_up>,
710 <1 24 RK_FUNC_2 &pcfg_pull_up>,
711 <1 25 RK_FUNC_2 &pcfg_pull_up>;
716 rgmii_pins: rgmii-pins {
717 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
718 <3 24 RK_FUNC_1 &pcfg_pull_none>,
719 <3 19 RK_FUNC_1 &pcfg_pull_none>,
720 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
721 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
722 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
723 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
724 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
725 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
726 <3 15 RK_FUNC_1 &pcfg_pull_none>,
727 <3 16 RK_FUNC_1 &pcfg_pull_none>,
728 <3 17 RK_FUNC_1 &pcfg_pull_none>,
729 <3 18 RK_FUNC_1 &pcfg_pull_none>,
730 <3 25 RK_FUNC_1 &pcfg_pull_none>,
731 <3 20 RK_FUNC_1 &pcfg_pull_none>;
734 rmii_pins: rmii-pins {
735 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
736 <3 24 RK_FUNC_1 &pcfg_pull_none>,
737 <3 19 RK_FUNC_1 &pcfg_pull_none>,
738 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
739 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
740 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
741 <3 15 RK_FUNC_1 &pcfg_pull_none>,
742 <3 16 RK_FUNC_1 &pcfg_pull_none>,
743 <3 20 RK_FUNC_1 &pcfg_pull_none>,
744 <3 21 RK_FUNC_1 &pcfg_pull_none>;
749 i2c0_xfer: i2c0-xfer {
750 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
751 <0 7 RK_FUNC_1 &pcfg_pull_none>;
756 i2c1_xfer: i2c1-xfer {
757 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
758 <2 22 RK_FUNC_1 &pcfg_pull_none>;
763 i2c2_xfer: i2c2-xfer {
764 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
765 <3 31 RK_FUNC_2 &pcfg_pull_none>;
770 i2c3_xfer: i2c3-xfer {
771 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
772 <1 17 RK_FUNC_1 &pcfg_pull_none>;
777 i2c4_xfer: i2c4-xfer {
778 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
779 <3 25 RK_FUNC_2 &pcfg_pull_none>;
784 i2c5_xfer: i2c5-xfer {
785 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
786 <3 27 RK_FUNC_2 &pcfg_pull_none>;
792 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
798 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
804 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
809 sdio0_bus1: sdio0-bus1 {
810 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
813 sdio0_bus4: sdio0-bus4 {
814 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
815 <2 29 RK_FUNC_1 &pcfg_pull_up>,
816 <2 30 RK_FUNC_1 &pcfg_pull_up>,
817 <2 31 RK_FUNC_1 &pcfg_pull_up>;
820 sdio0_cmd: sdio0-cmd {
821 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
824 sdio0_clk: sdio0-clk {
825 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
829 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
833 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
836 sdio0_pwr: sdio0-pwr {
837 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
840 sdio0_bkpwr: sdio0-bkpwr {
841 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
844 sdio0_int: sdio0-int {
845 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
850 sdmmc_clk: sdmmc-clk {
851 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
854 sdmmc_cmd: sdmmc-cmd {
855 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
859 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
862 sdmmc_bus1: sdmmc-bus1 {
863 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
866 sdmmc_bus4: sdmmc-bus4 {
867 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
868 <2 6 RK_FUNC_1 &pcfg_pull_up>,
869 <2 7 RK_FUNC_1 &pcfg_pull_up>,
870 <2 8 RK_FUNC_1 &pcfg_pull_up>;
876 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
879 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
882 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
885 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
888 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
894 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
897 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
900 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
903 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
906 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
912 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
915 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
918 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
921 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
927 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
931 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
936 uart0_xfer: uart0-xfer {
937 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
938 <2 25 RK_FUNC_1 &pcfg_pull_none>;
941 uart0_cts: uart0-cts {
942 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
945 uart0_rts: uart0-rts {
946 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
951 uart1_xfer: uart1-xfer {
952 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
953 <0 21 RK_FUNC_3 &pcfg_pull_none>;
956 uart1_cts: uart1-cts {
957 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
960 uart1_rts: uart1-rts {
961 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
966 uart2_xfer: uart2-xfer {
967 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
968 <2 5 RK_FUNC_2 &pcfg_pull_none>;
970 /* no rts / cts for uart2 */
974 uart3_xfer: uart3-xfer {
975 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
976 <3 30 RK_FUNC_3 &pcfg_pull_none>;
979 uart3_cts: uart3-cts {
980 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
983 uart3_rts: uart3-rts {
984 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
989 uart4_xfer: uart4-xfer {
990 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
991 <0 26 RK_FUNC_3 &pcfg_pull_none>;
994 uart4_cts: uart4-cts {
995 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
998 uart4_rts: uart4-rts {
999 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;