2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
54 interrupt-parent = <&gic>;
107 compatible = "arm,cortex-a53", "arm,armv8";
109 enable-method = "psci";
110 #cooling-cells = <2>; /* min followed by max */
111 clocks = <&cru ARMCLKL>;
116 compatible = "arm,cortex-a53", "arm,armv8";
118 enable-method = "psci";
119 clocks = <&cru ARMCLKL>;
124 compatible = "arm,cortex-a53", "arm,armv8";
126 enable-method = "psci";
127 clocks = <&cru ARMCLKL>;
132 compatible = "arm,cortex-a53", "arm,armv8";
134 enable-method = "psci";
135 clocks = <&cru ARMCLKL>;
140 compatible = "arm,cortex-a72", "arm,armv8";
142 enable-method = "psci";
143 #cooling-cells = <2>; /* min followed by max */
144 clocks = <&cru ARMCLKB>;
149 compatible = "arm,cortex-a72", "arm,armv8";
151 enable-method = "psci";
152 clocks = <&cru ARMCLKB>;
157 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
162 compatible = "arm,cortex-a72-pmu";
163 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
167 compatible = "arm,psci-1.0";
172 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
174 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
175 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
176 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
177 arm,no-tick-in-suspend;
181 compatible = "fixed-clock";
182 clock-frequency = <24000000>;
183 clock-output-names = "xin24m";
188 compatible = "simple-bus";
189 #address-cells = <2>;
193 dmac_bus: dma-controller@ff6d0000 {
194 compatible = "arm,pl330", "arm,primecell";
195 reg = <0x0 0xff6d0000 0x0 0x4000>;
196 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
197 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
199 clocks = <&cru ACLK_DMAC0_PERILP>;
200 clock-names = "apb_pclk";
203 dmac_peri: dma-controller@ff6e0000 {
204 compatible = "arm,pl330", "arm,primecell";
205 reg = <0x0 0xff6e0000 0x0 0x4000>;
206 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
207 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
209 clocks = <&cru ACLK_DMAC1_PERILP>;
210 clock-names = "apb_pclk";
214 pcie0: pcie@f8000000 {
215 compatible = "rockchip,rk3399-pcie";
216 reg = <0x0 0xf8000000 0x0 0x2000000>,
217 <0x0 0xfd000000 0x0 0x1000000>;
218 reg-names = "axi-base", "apb-base";
219 #address-cells = <3>;
221 #interrupt-cells = <1>;
223 bus-range = <0x0 0x1f>;
224 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
225 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
226 clock-names = "aclk", "aclk-perf",
228 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
229 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
230 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
231 interrupt-names = "sys", "legacy", "client";
232 interrupt-map-mask = <0 0 0 7>;
233 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
234 <0 0 0 2 &pcie0_intc 1>,
235 <0 0 0 3 &pcie0_intc 2>,
236 <0 0 0 4 &pcie0_intc 3>;
237 linux,pci-domain = <0>;
238 max-link-speed = <1>;
239 msi-map = <0x0 &its 0x0 0x1000>;
241 phy-names = "pcie-phy";
242 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
243 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
244 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
245 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
246 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
248 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
249 "pm", "pclk", "aclk";
252 pcie0_intc: interrupt-controller {
253 interrupt-controller;
254 #address-cells = <0>;
255 #interrupt-cells = <1>;
259 gmac: ethernet@fe300000 {
260 compatible = "rockchip,rk3399-gmac";
261 reg = <0x0 0xfe300000 0x0 0x10000>;
262 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
263 interrupt-names = "macirq";
264 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
265 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
266 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
268 clock-names = "stmmaceth", "mac_clk_rx",
269 "mac_clk_tx", "clk_mac_ref",
270 "clk_mac_refout", "aclk_mac",
272 power-domains = <&power RK3399_PD_GMAC>;
273 resets = <&cru SRST_A_GMAC>;
274 reset-names = "stmmaceth";
275 rockchip,grf = <&grf>;
279 sdio0: dwmmc@fe310000 {
280 compatible = "rockchip,rk3399-dw-mshc",
281 "rockchip,rk3288-dw-mshc";
282 reg = <0x0 0xfe310000 0x0 0x4000>;
283 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
284 max-frequency = <150000000>;
285 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
286 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
287 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
288 fifo-depth = <0x100>;
289 resets = <&cru SRST_SDIO0>;
290 reset-names = "reset";
294 sdmmc: dwmmc@fe320000 {
295 compatible = "rockchip,rk3399-dw-mshc",
296 "rockchip,rk3288-dw-mshc";
297 reg = <0x0 0xfe320000 0x0 0x4000>;
298 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
299 max-frequency = <150000000>;
300 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
301 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
303 fifo-depth = <0x100>;
304 power-domains = <&power RK3399_PD_SD>;
305 resets = <&cru SRST_SDMMC>;
306 reset-names = "reset";
310 sdhci: sdhci@fe330000 {
311 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
312 reg = <0x0 0xfe330000 0x0 0x10000>;
313 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
314 arasan,soc-ctl-syscon = <&grf>;
315 assigned-clocks = <&cru SCLK_EMMC>;
316 assigned-clock-rates = <200000000>;
317 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
318 clock-names = "clk_xin", "clk_ahb";
319 clock-output-names = "emmc_cardclock";
322 phy-names = "phy_arasan";
323 power-domains = <&power RK3399_PD_EMMC>;
327 usb_host0_ehci: usb@fe380000 {
328 compatible = "generic-ehci";
329 reg = <0x0 0xfe380000 0x0 0x20000>;
330 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
331 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
333 clock-names = "usbhost", "arbiter",
335 phys = <&u2phy0_host>;
340 usb_host0_ohci: usb@fe3a0000 {
341 compatible = "generic-ohci";
342 reg = <0x0 0xfe3a0000 0x0 0x20000>;
343 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
344 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
346 clock-names = "usbhost", "arbiter",
348 phys = <&u2phy0_host>;
353 usb_host1_ehci: usb@fe3c0000 {
354 compatible = "generic-ehci";
355 reg = <0x0 0xfe3c0000 0x0 0x20000>;
356 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
357 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
359 clock-names = "usbhost", "arbiter",
361 phys = <&u2phy1_host>;
366 usb_host1_ohci: usb@fe3e0000 {
367 compatible = "generic-ohci";
368 reg = <0x0 0xfe3e0000 0x0 0x20000>;
369 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
370 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
372 clock-names = "usbhost", "arbiter",
374 phys = <&u2phy1_host>;
379 usbdrd3_0: usb@fe800000 {
380 compatible = "rockchip,rk3399-dwc3";
381 #address-cells = <2>;
384 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
385 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
386 clock-names = "ref_clk", "suspend_clk",
387 "bus_clk", "grf_clk";
390 usbdrd_dwc3_0: dwc3 {
391 compatible = "snps,dwc3";
392 reg = <0x0 0xfe800000 0x0 0x100000>;
393 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
395 phys = <&u2phy0_otg>;
396 phy-names = "usb2-phy";
397 phy_type = "utmi_wide";
398 snps,dis_enblslpm_quirk;
399 snps,dis-u2-freeclk-exists-quirk;
400 snps,dis_u2_susphy_quirk;
401 snps,dis-del-phy-power-chg-quirk;
406 usbdrd3_1: usb@fe900000 {
407 compatible = "rockchip,rk3399-dwc3";
408 #address-cells = <2>;
411 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
412 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
413 clock-names = "ref_clk", "suspend_clk",
414 "bus_clk", "grf_clk";
417 usbdrd_dwc3_1: dwc3 {
418 compatible = "snps,dwc3";
419 reg = <0x0 0xfe900000 0x0 0x100000>;
420 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
422 phys = <&u2phy1_otg>;
423 phy-names = "usb2-phy";
424 phy_type = "utmi_wide";
425 snps,dis_enblslpm_quirk;
426 snps,dis-u2-freeclk-exists-quirk;
427 snps,dis_u2_susphy_quirk;
428 snps,dis-del-phy-power-chg-quirk;
433 gic: interrupt-controller@fee00000 {
434 compatible = "arm,gic-v3";
435 #interrupt-cells = <4>;
436 #address-cells = <2>;
439 interrupt-controller;
441 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
442 <0x0 0xfef00000 0 0xc0000>, /* GICR */
443 <0x0 0xfff00000 0 0x10000>, /* GICC */
444 <0x0 0xfff10000 0 0x10000>, /* GICH */
445 <0x0 0xfff20000 0 0x10000>; /* GICV */
446 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
447 its: interrupt-controller@fee20000 {
448 compatible = "arm,gic-v3-its";
450 reg = <0x0 0xfee20000 0x0 0x20000>;
454 ppi_cluster0: interrupt-partition-0 {
455 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
458 ppi_cluster1: interrupt-partition-1 {
459 affinity = <&cpu_b0 &cpu_b1>;
464 saradc: saradc@ff100000 {
465 compatible = "rockchip,rk3399-saradc";
466 reg = <0x0 0xff100000 0x0 0x100>;
467 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
468 #io-channel-cells = <1>;
469 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
470 clock-names = "saradc", "apb_pclk";
471 resets = <&cru SRST_P_SARADC>;
472 reset-names = "saradc-apb";
477 compatible = "rockchip,rk3399-i2c";
478 reg = <0x0 0xff110000 0x0 0x1000>;
479 assigned-clocks = <&cru SCLK_I2C1>;
480 assigned-clock-rates = <200000000>;
481 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
482 clock-names = "i2c", "pclk";
483 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
484 pinctrl-names = "default";
485 pinctrl-0 = <&i2c1_xfer>;
486 #address-cells = <1>;
492 compatible = "rockchip,rk3399-i2c";
493 reg = <0x0 0xff120000 0x0 0x1000>;
494 assigned-clocks = <&cru SCLK_I2C2>;
495 assigned-clock-rates = <200000000>;
496 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
497 clock-names = "i2c", "pclk";
498 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&i2c2_xfer>;
501 #address-cells = <1>;
507 compatible = "rockchip,rk3399-i2c";
508 reg = <0x0 0xff130000 0x0 0x1000>;
509 assigned-clocks = <&cru SCLK_I2C3>;
510 assigned-clock-rates = <200000000>;
511 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
512 clock-names = "i2c", "pclk";
513 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c3_xfer>;
516 #address-cells = <1>;
522 compatible = "rockchip,rk3399-i2c";
523 reg = <0x0 0xff140000 0x0 0x1000>;
524 assigned-clocks = <&cru SCLK_I2C5>;
525 assigned-clock-rates = <200000000>;
526 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
527 clock-names = "i2c", "pclk";
528 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2c5_xfer>;
531 #address-cells = <1>;
537 compatible = "rockchip,rk3399-i2c";
538 reg = <0x0 0xff150000 0x0 0x1000>;
539 assigned-clocks = <&cru SCLK_I2C6>;
540 assigned-clock-rates = <200000000>;
541 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
542 clock-names = "i2c", "pclk";
543 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&i2c6_xfer>;
546 #address-cells = <1>;
552 compatible = "rockchip,rk3399-i2c";
553 reg = <0x0 0xff160000 0x0 0x1000>;
554 assigned-clocks = <&cru SCLK_I2C7>;
555 assigned-clock-rates = <200000000>;
556 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
557 clock-names = "i2c", "pclk";
558 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c7_xfer>;
561 #address-cells = <1>;
566 uart0: serial@ff180000 {
567 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
568 reg = <0x0 0xff180000 0x0 0x100>;
569 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
570 clock-names = "baudclk", "apb_pclk";
571 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&uart0_xfer>;
579 uart1: serial@ff190000 {
580 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
581 reg = <0x0 0xff190000 0x0 0x100>;
582 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
583 clock-names = "baudclk", "apb_pclk";
584 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&uart1_xfer>;
592 uart2: serial@ff1a0000 {
593 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
594 reg = <0x0 0xff1a0000 0x0 0x100>;
595 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
596 clock-names = "baudclk", "apb_pclk";
597 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
600 pinctrl-names = "default";
601 pinctrl-0 = <&uart2c_xfer>;
605 uart3: serial@ff1b0000 {
606 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
607 reg = <0x0 0xff1b0000 0x0 0x100>;
608 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
609 clock-names = "baudclk", "apb_pclk";
610 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&uart3_xfer>;
619 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
620 reg = <0x0 0xff1c0000 0x0 0x1000>;
621 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
622 clock-names = "spiclk", "apb_pclk";
623 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
626 #address-cells = <1>;
632 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
633 reg = <0x0 0xff1d0000 0x0 0x1000>;
634 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
635 clock-names = "spiclk", "apb_pclk";
636 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
639 #address-cells = <1>;
645 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
646 reg = <0x0 0xff1e0000 0x0 0x1000>;
647 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
648 clock-names = "spiclk", "apb_pclk";
649 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
652 #address-cells = <1>;
658 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
659 reg = <0x0 0xff1f0000 0x0 0x1000>;
660 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
661 clock-names = "spiclk", "apb_pclk";
662 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
665 #address-cells = <1>;
671 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
672 reg = <0x0 0xff200000 0x0 0x1000>;
673 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
674 clock-names = "spiclk", "apb_pclk";
675 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
678 #address-cells = <1>;
683 thermal_zones: thermal-zones {
685 polling-delay-passive = <100>;
686 polling-delay = <1000>;
688 thermal-sensors = <&tsadc 0>;
691 cpu_alert0: cpu_alert0 {
692 temperature = <70000>;
696 cpu_alert1: cpu_alert1 {
697 temperature = <75000>;
702 temperature = <95000>;
710 trip = <&cpu_alert0>;
712 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
715 trip = <&cpu_alert1>;
717 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
718 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
724 polling-delay-passive = <100>;
725 polling-delay = <1000>;
727 thermal-sensors = <&tsadc 1>;
730 gpu_alert0: gpu_alert0 {
731 temperature = <75000>;
736 temperature = <95000>;
744 trip = <&gpu_alert0>;
746 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
752 tsadc: tsadc@ff260000 {
753 compatible = "rockchip,rk3399-tsadc";
754 reg = <0x0 0xff260000 0x0 0x100>;
755 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
756 assigned-clocks = <&cru SCLK_TSADC>;
757 assigned-clock-rates = <750000>;
758 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
759 clock-names = "tsadc", "apb_pclk";
760 resets = <&cru SRST_TSADC>;
761 reset-names = "tsadc-apb";
762 rockchip,grf = <&grf>;
763 rockchip,hw-tshut-temp = <95000>;
764 pinctrl-names = "init", "default", "sleep";
765 pinctrl-0 = <&otp_gpio>;
766 pinctrl-1 = <&otp_out>;
767 pinctrl-2 = <&otp_gpio>;
768 #thermal-sensor-cells = <1>;
772 qos_emmc: qos@ffa58000 {
773 compatible = "syscon";
774 reg = <0x0 0xffa58000 0x0 0x20>;
777 qos_gmac: qos@ffa5c000 {
778 compatible = "syscon";
779 reg = <0x0 0xffa5c000 0x0 0x20>;
782 qos_pcie: qos@ffa60080 {
783 compatible = "syscon";
784 reg = <0x0 0xffa60080 0x0 0x20>;
787 qos_usb_host0: qos@ffa60100 {
788 compatible = "syscon";
789 reg = <0x0 0xffa60100 0x0 0x20>;
792 qos_usb_host1: qos@ffa60180 {
793 compatible = "syscon";
794 reg = <0x0 0xffa60180 0x0 0x20>;
797 qos_usb_otg0: qos@ffa70000 {
798 compatible = "syscon";
799 reg = <0x0 0xffa70000 0x0 0x20>;
802 qos_usb_otg1: qos@ffa70080 {
803 compatible = "syscon";
804 reg = <0x0 0xffa70080 0x0 0x20>;
807 qos_sd: qos@ffa74000 {
808 compatible = "syscon";
809 reg = <0x0 0xffa74000 0x0 0x20>;
812 qos_sdioaudio: qos@ffa76000 {
813 compatible = "syscon";
814 reg = <0x0 0xffa76000 0x0 0x20>;
817 qos_hdcp: qos@ffa90000 {
818 compatible = "syscon";
819 reg = <0x0 0xffa90000 0x0 0x20>;
822 qos_iep: qos@ffa98000 {
823 compatible = "syscon";
824 reg = <0x0 0xffa98000 0x0 0x20>;
827 qos_isp0_m0: qos@ffaa0000 {
828 compatible = "syscon";
829 reg = <0x0 0xffaa0000 0x0 0x20>;
832 qos_isp0_m1: qos@ffaa0080 {
833 compatible = "syscon";
834 reg = <0x0 0xffaa0080 0x0 0x20>;
837 qos_isp1_m0: qos@ffaa8000 {
838 compatible = "syscon";
839 reg = <0x0 0xffaa8000 0x0 0x20>;
842 qos_isp1_m1: qos@ffaa8080 {
843 compatible = "syscon";
844 reg = <0x0 0xffaa8080 0x0 0x20>;
847 qos_rga_r: qos@ffab0000 {
848 compatible = "syscon";
849 reg = <0x0 0xffab0000 0x0 0x20>;
852 qos_rga_w: qos@ffab0080 {
853 compatible = "syscon";
854 reg = <0x0 0xffab0080 0x0 0x20>;
857 qos_video_m0: qos@ffab8000 {
858 compatible = "syscon";
859 reg = <0x0 0xffab8000 0x0 0x20>;
862 qos_video_m1_r: qos@ffac0000 {
863 compatible = "syscon";
864 reg = <0x0 0xffac0000 0x0 0x20>;
867 qos_video_m1_w: qos@ffac0080 {
868 compatible = "syscon";
869 reg = <0x0 0xffac0080 0x0 0x20>;
872 qos_vop_big_r: qos@ffac8000 {
873 compatible = "syscon";
874 reg = <0x0 0xffac8000 0x0 0x20>;
877 qos_vop_big_w: qos@ffac8080 {
878 compatible = "syscon";
879 reg = <0x0 0xffac8080 0x0 0x20>;
882 qos_vop_little: qos@ffad0000 {
883 compatible = "syscon";
884 reg = <0x0 0xffad0000 0x0 0x20>;
887 qos_perihp: qos@ffad8080 {
888 compatible = "syscon";
889 reg = <0x0 0xffad8080 0x0 0x20>;
892 qos_gpu: qos@ffae0000 {
893 compatible = "syscon";
894 reg = <0x0 0xffae0000 0x0 0x20>;
897 pmu: power-management@ff310000 {
898 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
899 reg = <0x0 0xff310000 0x0 0x1000>;
902 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
903 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
904 * Some of the power domains are grouped together for every
906 * The detail contents as below.
908 power: power-controller {
909 compatible = "rockchip,rk3399-power-controller";
910 #power-domain-cells = <1>;
911 #address-cells = <1>;
914 /* These power domains are grouped by VD_CENTER */
915 pd_iep@RK3399_PD_IEP {
916 reg = <RK3399_PD_IEP>;
917 clocks = <&cru ACLK_IEP>,
921 pd_rga@RK3399_PD_RGA {
922 reg = <RK3399_PD_RGA>;
923 clocks = <&cru ACLK_RGA>,
925 pm_qos = <&qos_rga_r>,
928 pd_vcodec@RK3399_PD_VCODEC {
929 reg = <RK3399_PD_VCODEC>;
930 clocks = <&cru ACLK_VCODEC>,
932 pm_qos = <&qos_video_m0>;
934 pd_vdu@RK3399_PD_VDU {
935 reg = <RK3399_PD_VDU>;
936 clocks = <&cru ACLK_VDU>,
938 pm_qos = <&qos_video_m1_r>,
942 /* These power domains are grouped by VD_GPU */
943 pd_gpu@RK3399_PD_GPU {
944 reg = <RK3399_PD_GPU>;
945 clocks = <&cru ACLK_GPU>;
949 /* These power domains are grouped by VD_LOGIC */
950 pd_emmc@RK3399_PD_EMMC {
951 reg = <RK3399_PD_EMMC>;
952 clocks = <&cru ACLK_EMMC>;
953 pm_qos = <&qos_emmc>;
955 pd_gmac@RK3399_PD_GMAC {
956 reg = <RK3399_PD_GMAC>;
957 clocks = <&cru ACLK_GMAC>,
959 pm_qos = <&qos_gmac>;
962 reg = <RK3399_PD_SD>;
963 clocks = <&cru HCLK_SDMMC>,
967 pd_vio@RK3399_PD_VIO {
968 reg = <RK3399_PD_VIO>;
969 #address-cells = <1>;
972 pd_hdcp@RK3399_PD_HDCP {
973 reg = <RK3399_PD_HDCP>;
974 clocks = <&cru ACLK_HDCP>,
977 pm_qos = <&qos_hdcp>;
979 pd_isp0@RK3399_PD_ISP0 {
980 reg = <RK3399_PD_ISP0>;
981 clocks = <&cru ACLK_ISP0>,
983 pm_qos = <&qos_isp0_m0>,
986 pd_isp1@RK3399_PD_ISP1 {
987 reg = <RK3399_PD_ISP1>;
988 clocks = <&cru ACLK_ISP1>,
990 pm_qos = <&qos_isp1_m0>,
993 pd_tcpc0@RK3399_PD_TCPC0 {
994 reg = <RK3399_PD_TCPD0>;
995 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
996 <&cru SCLK_UPHY0_TCPDPHY_REF>;
998 pd_tcpc1@RK3399_PD_TCPC1 {
999 reg = <RK3399_PD_TCPD1>;
1000 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1001 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1003 pd_vo@RK3399_PD_VO {
1004 reg = <RK3399_PD_VO>;
1005 #address-cells = <1>;
1008 pd_vopb@RK3399_PD_VOPB {
1009 reg = <RK3399_PD_VOPB>;
1010 clocks = <&cru ACLK_VOP0>,
1012 pm_qos = <&qos_vop_big_r>,
1015 pd_vopl@RK3399_PD_VOPL {
1016 reg = <RK3399_PD_VOPL>;
1017 clocks = <&cru ACLK_VOP1>,
1019 pm_qos = <&qos_vop_little>;
1026 pmugrf: syscon@ff320000 {
1027 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1028 reg = <0x0 0xff320000 0x0 0x1000>;
1029 #address-cells = <1>;
1032 pmu_io_domains: io-domains {
1033 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1034 status = "disabled";
1038 spi3: spi@ff350000 {
1039 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1040 reg = <0x0 0xff350000 0x0 0x1000>;
1041 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1042 clock-names = "spiclk", "apb_pclk";
1043 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1044 pinctrl-names = "default";
1045 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1046 #address-cells = <1>;
1048 status = "disabled";
1051 uart4: serial@ff370000 {
1052 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1053 reg = <0x0 0xff370000 0x0 0x100>;
1054 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1055 clock-names = "baudclk", "apb_pclk";
1056 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1059 pinctrl-names = "default";
1060 pinctrl-0 = <&uart4_xfer>;
1061 status = "disabled";
1064 i2c0: i2c@ff3c0000 {
1065 compatible = "rockchip,rk3399-i2c";
1066 reg = <0x0 0xff3c0000 0x0 0x1000>;
1067 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1068 assigned-clock-rates = <200000000>;
1069 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1070 clock-names = "i2c", "pclk";
1071 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&i2c0_xfer>;
1074 #address-cells = <1>;
1076 status = "disabled";
1079 i2c4: i2c@ff3d0000 {
1080 compatible = "rockchip,rk3399-i2c";
1081 reg = <0x0 0xff3d0000 0x0 0x1000>;
1082 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1083 assigned-clock-rates = <200000000>;
1084 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1085 clock-names = "i2c", "pclk";
1086 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1087 pinctrl-names = "default";
1088 pinctrl-0 = <&i2c4_xfer>;
1089 #address-cells = <1>;
1091 status = "disabled";
1094 i2c8: i2c@ff3e0000 {
1095 compatible = "rockchip,rk3399-i2c";
1096 reg = <0x0 0xff3e0000 0x0 0x1000>;
1097 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1098 assigned-clock-rates = <200000000>;
1099 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1100 clock-names = "i2c", "pclk";
1101 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&i2c8_xfer>;
1104 #address-cells = <1>;
1106 status = "disabled";
1109 pwm0: pwm@ff420000 {
1110 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1111 reg = <0x0 0xff420000 0x0 0x10>;
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&pwm0_pin>;
1115 clocks = <&pmucru PCLK_RKPWM_PMU>;
1116 clock-names = "pwm";
1117 status = "disabled";
1120 pwm1: pwm@ff420010 {
1121 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1122 reg = <0x0 0xff420010 0x0 0x10>;
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&pwm1_pin>;
1126 clocks = <&pmucru PCLK_RKPWM_PMU>;
1127 clock-names = "pwm";
1128 status = "disabled";
1131 pwm2: pwm@ff420020 {
1132 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1133 reg = <0x0 0xff420020 0x0 0x10>;
1135 pinctrl-names = "default";
1136 pinctrl-0 = <&pwm2_pin>;
1137 clocks = <&pmucru PCLK_RKPWM_PMU>;
1138 clock-names = "pwm";
1139 status = "disabled";
1142 pwm3: pwm@ff420030 {
1143 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1144 reg = <0x0 0xff420030 0x0 0x10>;
1146 pinctrl-names = "default";
1147 pinctrl-0 = <&pwm3a_pin>;
1148 clocks = <&pmucru PCLK_RKPWM_PMU>;
1149 clock-names = "pwm";
1150 status = "disabled";
1153 efuse0: efuse@ff690000 {
1154 compatible = "rockchip,rk3399-efuse";
1155 reg = <0x0 0xff690000 0x0 0x80>;
1156 #address-cells = <1>;
1158 clocks = <&cru PCLK_EFUSE1024NS>;
1159 clock-names = "pclk_efuse";
1165 cpub_leakage: cpu-leakage@17 {
1168 gpu_leakage: gpu-leakage@18 {
1171 center_leakage: center-leakage@19 {
1174 cpul_leakage: cpu-leakage@1a {
1177 logic_leakage: logic-leakage@1b {
1180 wafer_info: wafer-info@1c {
1185 pmucru: pmu-clock-controller@ff750000 {
1186 compatible = "rockchip,rk3399-pmucru";
1187 reg = <0x0 0xff750000 0x0 0x1000>;
1188 rockchip,grf = <&pmugrf>;
1191 assigned-clocks = <&pmucru PLL_PPLL>;
1192 assigned-clock-rates = <676000000>;
1195 cru: clock-controller@ff760000 {
1196 compatible = "rockchip,rk3399-cru";
1197 reg = <0x0 0xff760000 0x0 0x1000>;
1198 rockchip,grf = <&grf>;
1202 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1204 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1206 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1207 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1208 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1209 assigned-clock-rates =
1210 <594000000>, <800000000>,
1212 <150000000>, <75000000>,
1214 <100000000>, <100000000>,
1215 <50000000>, <600000000>,
1216 <100000000>, <50000000>;
1219 grf: syscon@ff770000 {
1220 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1221 reg = <0x0 0xff770000 0x0 0x10000>;
1222 #address-cells = <1>;
1225 io_domains: io-domains {
1226 compatible = "rockchip,rk3399-io-voltage-domain";
1227 status = "disabled";
1230 u2phy0: usb2-phy@e450 {
1231 compatible = "rockchip,rk3399-usb2phy";
1232 reg = <0xe450 0x10>;
1233 clocks = <&cru SCLK_USB2PHY0_REF>;
1234 clock-names = "phyclk";
1236 clock-output-names = "clk_usbphy0_480m";
1237 status = "disabled";
1239 u2phy0_host: host-port {
1241 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1242 interrupt-names = "linestate";
1243 status = "disabled";
1246 u2phy0_otg: otg-port {
1248 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1249 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1250 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1251 interrupt-names = "otg-bvalid", "otg-id",
1253 status = "disabled";
1257 u2phy1: usb2-phy@e460 {
1258 compatible = "rockchip,rk3399-usb2phy";
1259 reg = <0xe460 0x10>;
1260 clocks = <&cru SCLK_USB2PHY1_REF>;
1261 clock-names = "phyclk";
1263 clock-output-names = "clk_usbphy1_480m";
1264 status = "disabled";
1266 u2phy1_host: host-port {
1268 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1269 interrupt-names = "linestate";
1270 status = "disabled";
1273 u2phy1_otg: otg-port {
1275 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1276 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1278 interrupt-names = "otg-bvalid", "otg-id",
1280 status = "disabled";
1284 emmc_phy: phy@f780 {
1285 compatible = "rockchip,rk3399-emmc-phy";
1286 reg = <0xf780 0x24>;
1288 clock-names = "emmcclk";
1290 status = "disabled";
1293 pcie_phy: pcie-phy {
1294 compatible = "rockchip,rk3399-pcie-phy";
1295 clocks = <&cru SCLK_PCIEPHY_REF>;
1296 clock-names = "refclk";
1298 resets = <&cru SRST_PCIEPHY>;
1299 reset-names = "phy";
1300 status = "disabled";
1304 tcphy0: phy@ff7c0000 {
1305 compatible = "rockchip,rk3399-typec-phy";
1306 reg = <0x0 0xff7c0000 0x0 0x40000>;
1307 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1308 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1309 clock-names = "tcpdcore", "tcpdphy-ref";
1310 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1311 assigned-clock-rates = <50000000>;
1312 power-domains = <&power RK3399_PD_TCPD0>;
1313 resets = <&cru SRST_UPHY0>,
1314 <&cru SRST_UPHY0_PIPE_L00>,
1315 <&cru SRST_P_UPHY0_TCPHY>;
1316 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1317 rockchip,grf = <&grf>;
1318 rockchip,typec-conn-dir = <0xe580 0 16>;
1319 rockchip,usb3tousb2-en = <0xe580 3 19>;
1320 rockchip,external-psm = <0xe588 14 30>;
1321 rockchip,pipe-status = <0xe5c0 0 0>;
1322 status = "disabled";
1324 tcphy0_dp: dp-port {
1328 tcphy0_usb3: usb3-port {
1333 tcphy1: phy@ff800000 {
1334 compatible = "rockchip,rk3399-typec-phy";
1335 reg = <0x0 0xff800000 0x0 0x40000>;
1336 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1337 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1338 clock-names = "tcpdcore", "tcpdphy-ref";
1339 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1340 assigned-clock-rates = <50000000>;
1341 power-domains = <&power RK3399_PD_TCPD1>;
1342 resets = <&cru SRST_UPHY1>,
1343 <&cru SRST_UPHY1_PIPE_L00>,
1344 <&cru SRST_P_UPHY1_TCPHY>;
1345 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1346 rockchip,grf = <&grf>;
1347 rockchip,typec-conn-dir = <0xe58c 0 16>;
1348 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1349 rockchip,external-psm = <0xe594 14 30>;
1350 rockchip,pipe-status = <0xe5c0 16 16>;
1351 status = "disabled";
1353 tcphy1_dp: dp-port {
1357 tcphy1_usb3: usb3-port {
1363 compatible = "snps,dw-wdt";
1364 reg = <0x0 0xff848000 0x0 0x100>;
1365 clocks = <&cru PCLK_WDT>;
1366 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1369 rktimer: rktimer@ff850000 {
1370 compatible = "rockchip,rk3399-timer";
1371 reg = <0x0 0xff850000 0x0 0x1000>;
1372 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1373 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1374 clock-names = "pclk", "timer";
1377 spdif: spdif@ff870000 {
1378 compatible = "rockchip,rk3399-spdif";
1379 reg = <0x0 0xff870000 0x0 0x1000>;
1380 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1381 dmas = <&dmac_bus 7>;
1383 clock-names = "mclk", "hclk";
1384 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1385 pinctrl-names = "default";
1386 pinctrl-0 = <&spdif_bus>;
1387 status = "disabled";
1390 i2s0: i2s@ff880000 {
1391 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1392 reg = <0x0 0xff880000 0x0 0x1000>;
1393 rockchip,grf = <&grf>;
1394 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1395 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1396 dma-names = "tx", "rx";
1397 clock-names = "i2s_clk", "i2s_hclk";
1398 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1399 pinctrl-names = "default";
1400 pinctrl-0 = <&i2s0_8ch_bus>;
1401 status = "disabled";
1404 i2s1: i2s@ff890000 {
1405 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1406 reg = <0x0 0xff890000 0x0 0x1000>;
1407 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1408 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1409 dma-names = "tx", "rx";
1410 clock-names = "i2s_clk", "i2s_hclk";
1411 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1412 pinctrl-names = "default";
1413 pinctrl-0 = <&i2s1_2ch_bus>;
1414 status = "disabled";
1417 i2s2: i2s@ff8a0000 {
1418 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1419 reg = <0x0 0xff8a0000 0x0 0x1000>;
1420 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1421 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1422 dma-names = "tx", "rx";
1423 clock-names = "i2s_clk", "i2s_hclk";
1424 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1425 status = "disabled";
1429 compatible = "rockchip,rk3399-pinctrl";
1430 rockchip,grf = <&grf>;
1431 rockchip,pmu = <&pmugrf>;
1432 #address-cells = <2>;
1436 gpio0: gpio0@ff720000 {
1437 compatible = "rockchip,gpio-bank";
1438 reg = <0x0 0xff720000 0x0 0x100>;
1439 clocks = <&pmucru PCLK_GPIO0_PMU>;
1440 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1443 #gpio-cells = <0x2>;
1445 interrupt-controller;
1446 #interrupt-cells = <0x2>;
1449 gpio1: gpio1@ff730000 {
1450 compatible = "rockchip,gpio-bank";
1451 reg = <0x0 0xff730000 0x0 0x100>;
1452 clocks = <&pmucru PCLK_GPIO1_PMU>;
1453 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1456 #gpio-cells = <0x2>;
1458 interrupt-controller;
1459 #interrupt-cells = <0x2>;
1462 gpio2: gpio2@ff780000 {
1463 compatible = "rockchip,gpio-bank";
1464 reg = <0x0 0xff780000 0x0 0x100>;
1465 clocks = <&cru PCLK_GPIO2>;
1466 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1469 #gpio-cells = <0x2>;
1471 interrupt-controller;
1472 #interrupt-cells = <0x2>;
1475 gpio3: gpio3@ff788000 {
1476 compatible = "rockchip,gpio-bank";
1477 reg = <0x0 0xff788000 0x0 0x100>;
1478 clocks = <&cru PCLK_GPIO3>;
1479 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1482 #gpio-cells = <0x2>;
1484 interrupt-controller;
1485 #interrupt-cells = <0x2>;
1488 gpio4: gpio4@ff790000 {
1489 compatible = "rockchip,gpio-bank";
1490 reg = <0x0 0xff790000 0x0 0x100>;
1491 clocks = <&cru PCLK_GPIO4>;
1492 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1495 #gpio-cells = <0x2>;
1497 interrupt-controller;
1498 #interrupt-cells = <0x2>;
1501 pcfg_pull_up: pcfg-pull-up {
1505 pcfg_pull_down: pcfg-pull-down {
1509 pcfg_pull_none: pcfg-pull-none {
1513 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1515 drive-strength = <12>;
1518 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1520 drive-strength = <8>;
1523 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1525 drive-strength = <4>;
1528 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1530 drive-strength = <2>;
1533 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1535 drive-strength = <12>;
1538 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1540 drive-strength = <13>;
1545 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1552 <4 23 RK_FUNC_2 &pcfg_pull_none>;
1557 rgmii_pins: rgmii-pins {
1560 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1562 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1564 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1566 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1568 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1570 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1572 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1574 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1576 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1578 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1580 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1582 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1584 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1586 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1588 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1591 rmii_pins: rmii-pins {
1594 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1596 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1598 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1600 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1602 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1604 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1606 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1608 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1610 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1612 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1617 i2c0_xfer: i2c0-xfer {
1619 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1620 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1625 i2c1_xfer: i2c1-xfer {
1627 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1628 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1633 i2c2_xfer: i2c2-xfer {
1635 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1636 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1641 i2c3_xfer: i2c3-xfer {
1643 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1644 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1649 i2c4_xfer: i2c4-xfer {
1651 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1652 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1657 i2c5_xfer: i2c5-xfer {
1659 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1660 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1665 i2c6_xfer: i2c6-xfer {
1667 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1668 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1673 i2c7_xfer: i2c7-xfer {
1675 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1676 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1681 i2c8_xfer: i2c8-xfer {
1683 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1684 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1689 i2s0_8ch_bus: i2s0-8ch-bus {
1691 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1692 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1693 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1694 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1695 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1696 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1697 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1698 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1699 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1704 i2s1_2ch_bus: i2s1-2ch-bus {
1706 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1707 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1708 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1709 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1710 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1715 sdio0_bus1: sdio0-bus1 {
1717 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
1720 sdio0_bus4: sdio0-bus4 {
1722 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
1723 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
1724 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
1725 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
1728 sdio0_cmd: sdio0-cmd {
1730 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
1733 sdio0_clk: sdio0-clk {
1735 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1738 sdio0_cd: sdio0-cd {
1740 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
1743 sdio0_pwr: sdio0-pwr {
1745 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
1748 sdio0_bkpwr: sdio0-bkpwr {
1750 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
1753 sdio0_wp: sdio0-wp {
1755 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
1758 sdio0_int: sdio0-int {
1760 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
1765 sdmmc_bus1: sdmmc-bus1 {
1767 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1770 sdmmc_bus4: sdmmc-bus4 {
1772 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
1773 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
1774 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
1775 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1778 sdmmc_clk: sdmmc-clk {
1780 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
1783 sdmmc_cmd: sdmmc-cmd {
1785 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
1788 sdmmc_cd: sdmcc-cd {
1790 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
1793 sdmmc_wp: sdmmc-wp {
1795 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1800 ap_pwroff: ap-pwroff {
1801 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1804 ddrio_pwroff: ddrio-pwroff {
1805 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1810 spdif_bus: spdif-bus {
1812 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1815 spdif_bus_1: spdif-bus-1 {
1817 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
1822 spi0_clk: spi0-clk {
1824 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1826 spi0_cs0: spi0-cs0 {
1828 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1830 spi0_cs1: spi0-cs1 {
1832 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1836 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1840 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1845 spi1_clk: spi1-clk {
1847 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1849 spi1_cs0: spi1-cs0 {
1851 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1855 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1859 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1864 spi2_clk: spi2-clk {
1866 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1868 spi2_cs0: spi2-cs0 {
1870 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1874 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1878 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1883 spi3_clk: spi3-clk {
1885 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1887 spi3_cs0: spi3-cs0 {
1889 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1893 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1897 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1902 spi4_clk: spi4-clk {
1904 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1906 spi4_cs0: spi4-cs0 {
1908 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1912 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1916 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1921 spi5_clk: spi5-clk {
1923 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1925 spi5_cs0: spi5-cs0 {
1927 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1931 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1935 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1940 otp_gpio: otp-gpio {
1941 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1945 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1950 uart0_xfer: uart0-xfer {
1952 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1953 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1956 uart0_cts: uart0-cts {
1958 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1961 uart0_rts: uart0-rts {
1963 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1968 uart1_xfer: uart1-xfer {
1970 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1971 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1976 uart2a_xfer: uart2a-xfer {
1978 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1979 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1984 uart2b_xfer: uart2b-xfer {
1986 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1987 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1992 uart2c_xfer: uart2c-xfer {
1994 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1995 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2000 uart3_xfer: uart3-xfer {
2002 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2003 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2006 uart3_cts: uart3-cts {
2008 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2011 uart3_rts: uart3-rts {
2013 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2018 uart4_xfer: uart4-xfer {
2020 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2021 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2026 uarthdcp_xfer: uarthdcp-xfer {
2028 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2029 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2034 pwm0_pin: pwm0-pin {
2036 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2039 vop0_pwm_pin: vop0-pwm-pin {
2041 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2046 pwm1_pin: pwm1-pin {
2048 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2051 vop1_pwm_pin: vop1-pwm-pin {
2053 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2058 pwm2_pin: pwm2-pin {
2060 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2065 pwm3a_pin: pwm3a-pin {
2067 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2072 pwm3b_pin: pwm3b-pin {
2074 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2079 hdmi_i2c_xfer: hdmi-i2c-xfer {
2081 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2082 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2085 hdmi_cec: hdmi-cec {
2087 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2092 pcie_clkreqn: pci-clkreqn {
2094 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2097 pcie_clkreqnb: pci-clkreqnb {
2099 <4 24 RK_FUNC_1 &pcfg_pull_none>;
2102 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2104 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2107 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2109 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;