2 * Device Tree Source for UniPhier LD20 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /memreserve/ 0x80000000 0x00080000;
49 compatible = "socionext,uniphier-ld20";
52 interrupt-parent = <&gic>;
80 compatible = "arm,cortex-a72", "arm,armv8";
82 clocks = <&sys_clk 32>;
83 enable-method = "psci";
84 operating-points-v2 = <&cluster0_opp>;
89 compatible = "arm,cortex-a72", "arm,armv8";
91 clocks = <&sys_clk 32>;
92 enable-method = "psci";
93 operating-points-v2 = <&cluster0_opp>;
98 compatible = "arm,cortex-a53", "arm,armv8";
100 clocks = <&sys_clk 33>;
101 enable-method = "psci";
102 operating-points-v2 = <&cluster1_opp>;
107 compatible = "arm,cortex-a53", "arm,armv8";
109 clocks = <&sys_clk 33>;
110 enable-method = "psci";
111 operating-points-v2 = <&cluster1_opp>;
115 cluster0_opp: opp_table0 {
116 compatible = "operating-points-v2";
120 opp-hz = /bits/ 64 <250000000>;
121 clock-latency-ns = <300>;
124 opp-hz = /bits/ 64 <275000000>;
125 clock-latency-ns = <300>;
128 opp-hz = /bits/ 64 <500000000>;
129 clock-latency-ns = <300>;
132 opp-hz = /bits/ 64 <550000000>;
133 clock-latency-ns = <300>;
136 opp-hz = /bits/ 64 <666667000>;
137 clock-latency-ns = <300>;
140 opp-hz = /bits/ 64 <733334000>;
141 clock-latency-ns = <300>;
144 opp-hz = /bits/ 64 <1000000000>;
145 clock-latency-ns = <300>;
148 opp-hz = /bits/ 64 <1100000000>;
149 clock-latency-ns = <300>;
153 cluster1_opp: opp_table1 {
154 compatible = "operating-points-v2";
158 opp-hz = /bits/ 64 <250000000>;
159 clock-latency-ns = <300>;
162 opp-hz = /bits/ 64 <275000000>;
163 clock-latency-ns = <300>;
166 opp-hz = /bits/ 64 <500000000>;
167 clock-latency-ns = <300>;
170 opp-hz = /bits/ 64 <550000000>;
171 clock-latency-ns = <300>;
174 opp-hz = /bits/ 64 <666667000>;
175 clock-latency-ns = <300>;
178 opp-hz = /bits/ 64 <733334000>;
179 clock-latency-ns = <300>;
182 opp-hz = /bits/ 64 <1000000000>;
183 clock-latency-ns = <300>;
186 opp-hz = /bits/ 64 <1100000000>;
187 clock-latency-ns = <300>;
192 compatible = "arm,psci-1.0";
198 compatible = "fixed-clock";
200 clock-frequency = <25000000>;
205 compatible = "arm,armv8-timer";
206 interrupts = <1 13 4>,
213 compatible = "simple-bus";
214 #address-cells = <1>;
216 ranges = <0 0 0 0xffffffff>;
218 serial0: serial@54006800 {
219 compatible = "socionext,uniphier-uart";
221 reg = <0x54006800 0x40>;
222 interrupts = <0 33 4>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_uart0>;
225 clocks = <&peri_clk 0>;
228 serial1: serial@54006900 {
229 compatible = "socionext,uniphier-uart";
231 reg = <0x54006900 0x40>;
232 interrupts = <0 35 4>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_uart1>;
235 clocks = <&peri_clk 1>;
238 serial2: serial@54006a00 {
239 compatible = "socionext,uniphier-uart";
241 reg = <0x54006a00 0x40>;
242 interrupts = <0 37 4>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart2>;
245 clocks = <&peri_clk 2>;
248 serial3: serial@54006b00 {
249 compatible = "socionext,uniphier-uart";
251 reg = <0x54006b00 0x40>;
252 interrupts = <0 177 4>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_uart3>;
255 clocks = <&peri_clk 3>;
259 compatible = "socionext,uniphier-fi2c";
261 reg = <0x58780000 0x80>;
262 #address-cells = <1>;
264 interrupts = <0 41 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_i2c0>;
267 clocks = <&peri_clk 4>;
268 clock-frequency = <100000>;
272 compatible = "socionext,uniphier-fi2c";
274 reg = <0x58781000 0x80>;
275 #address-cells = <1>;
277 interrupts = <0 42 4>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_i2c1>;
280 clocks = <&peri_clk 5>;
281 clock-frequency = <100000>;
285 compatible = "socionext,uniphier-fi2c";
286 reg = <0x58782000 0x80>;
287 #address-cells = <1>;
289 interrupts = <0 43 4>;
290 clocks = <&peri_clk 6>;
291 clock-frequency = <400000>;
295 compatible = "socionext,uniphier-fi2c";
297 reg = <0x58783000 0x80>;
298 #address-cells = <1>;
300 interrupts = <0 44 4>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_i2c3>;
303 clocks = <&peri_clk 7>;
304 clock-frequency = <100000>;
308 compatible = "socionext,uniphier-fi2c";
310 reg = <0x58784000 0x80>;
311 #address-cells = <1>;
313 interrupts = <0 45 4>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_i2c4>;
316 clocks = <&peri_clk 8>;
317 clock-frequency = <100000>;
321 compatible = "socionext,uniphier-fi2c";
322 reg = <0x58785000 0x80>;
323 #address-cells = <1>;
325 interrupts = <0 25 4>;
326 clocks = <&peri_clk 9>;
327 clock-frequency = <400000>;
330 system_bus: system-bus@58c00000 {
331 compatible = "socionext,uniphier-system-bus";
333 reg = <0x58c00000 0x400>;
334 #address-cells = <2>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_system_bus>;
341 compatible = "socionext,uniphier-smpctrl";
342 reg = <0x59801000 0x400>;
346 compatible = "socionext,uniphier-ld20-sdctrl",
347 "simple-mfd", "syscon";
348 reg = <0x59810000 0x800>;
351 compatible = "socionext,uniphier-ld20-sd-clock";
356 compatible = "socionext,uniphier-ld20-sd-reset";
362 compatible = "socionext,uniphier-ld20-perictrl",
363 "simple-mfd", "syscon";
364 reg = <0x59820000 0x200>;
367 compatible = "socionext,uniphier-ld20-peri-clock";
372 compatible = "socionext,uniphier-ld20-peri-reset";
378 compatible = "socionext,uniphier-ld20-soc-glue",
379 "simple-mfd", "syscon";
380 reg = <0x5f800000 0x2000>;
383 compatible = "socionext,uniphier-ld20-pinctrl";
387 gic: interrupt-controller@5fe00000 {
388 compatible = "arm,gic-v3";
389 reg = <0x5fe00000 0x10000>, /* GICD */
390 <0x5fe80000 0x80000>; /* GICR */
391 interrupt-controller;
392 #interrupt-cells = <3>;
393 interrupts = <1 9 4>;
397 compatible = "socionext,uniphier-ld20-sysctrl",
398 "simple-mfd", "syscon";
399 reg = <0x61840000 0x10000>;
402 compatible = "socionext,uniphier-ld20-clock";
407 compatible = "socionext,uniphier-ld20-reset";
414 /include/ "uniphier-pinctrl.dtsi"