2 * Spreadtrum SC9860 SoC
4 * Copyright (C) 2016, Spreadtrum Communications Inc.
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include "whale2.dtsi"
51 compatible = "arm,cortex-a53", "arm,armv8";
53 enable-method = "psci";
54 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
59 compatible = "arm,cortex-a53", "arm,armv8";
61 enable-method = "psci";
62 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
70 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
75 compatible = "arm,cortex-a53", "arm,armv8";
77 enable-method = "psci";
78 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
83 compatible = "arm,cortex-a53", "arm,armv8";
85 enable-method = "psci";
86 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
91 compatible = "arm,cortex-a53", "arm,armv8";
93 enable-method = "psci";
94 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
99 compatible = "arm,cortex-a53", "arm,armv8";
100 reg = <0x0 0x530102>;
101 enable-method = "psci";
102 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
107 compatible = "arm,cortex-a53", "arm,armv8";
108 reg = <0x0 0x530103>;
109 enable-method = "psci";
110 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
115 entry-method = "arm,psci";
118 compatible = "arm,idle-state";
119 entry-latency-us = <1000>;
120 exit-latency-us = <700>;
121 min-residency-us = <2500>;
123 arm,psci-suspend-param = <0x00010002>;
126 CLUSTER_PD: cluster_pd {
127 compatible = "arm,idle-state";
128 entry-latency-us = <1000>;
129 exit-latency-us = <1000>;
130 min-residency-us = <3000>;
132 arm,psci-suspend-param = <0x01010003>;
136 gic: interrupt-controller@12001000 {
137 compatible = "arm,gic-400";
138 reg = <0 0x12001000 0 0x1000>,
139 <0 0x12002000 0 0x2000>,
140 <0 0x12004000 0 0x2000>,
141 <0 0x12006000 0 0x2000>;
142 #interrupt-cells = <3>;
143 interrupt-controller;
144 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
145 | IRQ_TYPE_LEVEL_HIGH)>;
149 compatible = "arm,psci-0.2";
154 compatible = "arm,armv8-timer";
155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
156 | IRQ_TYPE_LEVEL_LOW)>,
157 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
158 | IRQ_TYPE_LEVEL_LOW)>,
159 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
160 | IRQ_TYPE_LEVEL_LOW)>,
161 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
162 | IRQ_TYPE_LEVEL_LOW)>;
166 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
167 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
175 interrupt-affinity = <&CPU0>,
186 funnel@10001000 { /* SoC Funnel */
187 compatible = "arm,coresight-funnel", "arm,primecell";
188 reg = <0 0x10001000 0 0x1000>;
190 clock-names = "apb_pclk";
192 #address-cells = <1>;
197 soc_funnel_out_port: endpoint {
198 remote-endpoint = <&etb_in>;
204 soc_funnel_in_port0: endpoint {
207 <&main_funnel_out_port>;
213 soc_funnel_in_port1: endpoint {
223 compatible = "arm,coresight-tmc", "arm,primecell";
224 reg = <0 0x10003000 0 0x1000>;
226 clock-names = "apb_pclk";
231 <&soc_funnel_out_port>;
237 compatible = "arm,coresight-stm", "arm,primecell";
238 reg = <0 0x10006000 0 0x1000>,
239 <0 0x01000000 0 0x180000>;
240 reg-names = "stm-base", "stm-stimulus-base";
242 clock-names = "apb_pclk";
244 stm_out_port: endpoint {
246 <&soc_funnel_in_port1>;
251 funnel@11001000 { /* Cluster0 Funnel */
252 compatible = "arm,coresight-funnel", "arm,primecell";
253 reg = <0 0x11001000 0 0x1000>;
255 clock-names = "apb_pclk";
257 #address-cells = <1>;
262 cluster0_funnel_out_port: endpoint {
270 cluster0_funnel_in_port0: endpoint {
272 remote-endpoint = <&etm0_out>;
278 cluster0_funnel_in_port1: endpoint {
280 remote-endpoint = <&etm1_out>;
286 cluster0_funnel_in_port2: endpoint {
288 remote-endpoint = <&etm2_out>;
294 cluster0_funnel_in_port3: endpoint {
296 remote-endpoint = <&etm3_out>;
302 funnel@11002000 { /* Cluster1 Funnel */
303 compatible = "arm,coresight-funnel", "arm,primecell";
304 reg = <0 0x11002000 0 0x1000>;
306 clock-names = "apb_pclk";
308 #address-cells = <1>;
313 cluster1_funnel_out_port: endpoint {
321 cluster1_funnel_in_port0: endpoint {
323 remote-endpoint = <&etm4_out>;
329 cluster1_funnel_in_port1: endpoint {
331 remote-endpoint = <&etm5_out>;
337 cluster1_funnel_in_port2: endpoint {
339 remote-endpoint = <&etm6_out>;
345 cluster1_funnel_in_port3: endpoint {
347 remote-endpoint = <&etm7_out>;
353 etf@11003000 { /* ETF on Cluster0 */
354 compatible = "arm,coresight-tmc", "arm,primecell";
355 reg = <0 0x11003000 0 0x1000>;
357 clock-names = "apb_pclk";
360 #address-cells = <1>;
365 cluster0_etf_out: endpoint {
367 <&main_funnel_in_port0>;
373 cluster0_etf_in: endpoint {
376 <&cluster0_funnel_out_port>;
382 etf@11004000 { /* ETF on Cluster1 */
383 compatible = "arm,coresight-tmc", "arm,primecell";
384 reg = <0 0x11004000 0 0x1000>;
386 clock-names = "apb_pclk";
389 #address-cells = <1>;
394 cluster1_etf_out: endpoint {
396 <&main_funnel_in_port1>;
402 cluster1_etf_in: endpoint {
405 <&cluster1_funnel_out_port>;
411 funnel@11005000 { /* Main Funnel */
412 compatible = "arm,coresight-funnel", "arm,primecell";
413 reg = <0 0x11005000 0 0x1000>;
415 clock-names = "apb_pclk";
418 #address-cells = <1>;
423 main_funnel_out_port: endpoint {
425 <&soc_funnel_in_port0>;
431 main_funnel_in_port0: endpoint {
440 main_funnel_in_port1: endpoint {
450 compatible = "arm,coresight-etm4x", "arm,primecell";
451 reg = <0 0x11440000 0 0x1000>;
454 clock-names = "apb_pclk";
459 <&cluster0_funnel_in_port0>;
465 compatible = "arm,coresight-etm4x", "arm,primecell";
466 reg = <0 0x11540000 0 0x1000>;
469 clock-names = "apb_pclk";
474 <&cluster0_funnel_in_port1>;
480 compatible = "arm,coresight-etm4x", "arm,primecell";
481 reg = <0 0x11640000 0 0x1000>;
484 clock-names = "apb_pclk";
489 <&cluster0_funnel_in_port2>;
495 compatible = "arm,coresight-etm4x", "arm,primecell";
496 reg = <0 0x11740000 0 0x1000>;
499 clock-names = "apb_pclk";
504 <&cluster0_funnel_in_port3>;
510 compatible = "arm,coresight-etm4x", "arm,primecell";
511 reg = <0 0x11840000 0 0x1000>;
514 clock-names = "apb_pclk";
519 <&cluster1_funnel_in_port0>;
525 compatible = "arm,coresight-etm4x", "arm,primecell";
526 reg = <0 0x11940000 0 0x1000>;
529 clock-names = "apb_pclk";
534 <&cluster1_funnel_in_port1>;
540 compatible = "arm,coresight-etm4x", "arm,primecell";
541 reg = <0 0x11a40000 0 0x1000>;
544 clock-names = "apb_pclk";
549 <&cluster1_funnel_in_port2>;
555 compatible = "arm,coresight-etm4x", "arm,primecell";
556 reg = <0 0x11b40000 0 0x1000>;
559 clock-names = "apb_pclk";
564 <&cluster1_funnel_in_port3>;