2 * arch/arm64/include/asm/arch_gicv3.h
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __ASM_ARCH_GICV3_H
19 #define __ASM_ARCH_GICV3_H
21 #include <asm/sysreg.h>
25 #include <linux/stringify.h>
26 #include <asm/barrier.h>
27 #include <asm/cacheflush.h>
29 #define read_gicreg(r) read_sysreg_s(SYS_ ## r)
30 #define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
35 * These system registers are 32 bits, but we make sure that the compiler
36 * sets the GP register's most significant bits to 0 with an explicit cast.
39 static inline void gic_write_eoir(u32 irq)
41 write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
45 static inline void gic_write_dir(u32 irq)
47 write_sysreg_s(irq, SYS_ICC_DIR_EL1);
51 static inline u64 gic_read_iar_common(void)
55 irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
61 * Cavium ThunderX erratum 23154
63 * The gicv3 of ThunderX requires a modified version for reading the
64 * IAR status to ensure data synchronization (access to icc_iar1_el1
65 * is not sync'ed before and after).
67 static inline u64 gic_read_iar_cavium_thunderx(void)
72 irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
79 static inline void gic_write_pmr(u32 val)
81 write_sysreg_s(val, SYS_ICC_PMR_EL1);
84 static inline void gic_write_ctlr(u32 val)
86 write_sysreg_s(val, SYS_ICC_CTLR_EL1);
90 static inline void gic_write_grpen1(u32 val)
92 write_sysreg_s(val, SYS_ICC_GRPEN1_EL1);
96 static inline void gic_write_sgi1r(u64 val)
98 write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
101 static inline u32 gic_read_sre(void)
103 return read_sysreg_s(SYS_ICC_SRE_EL1);
106 static inline void gic_write_sre(u32 val)
108 write_sysreg_s(val, SYS_ICC_SRE_EL1);
112 static inline void gic_write_bpr1(u32 val)
114 write_sysreg_s(val, SYS_ICC_BPR1_EL1);
117 #define gic_read_typer(c) readq_relaxed(c)
118 #define gic_write_irouter(v, c) writeq_relaxed(v, c)
120 #define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
122 #define gits_read_baser(c) readq_relaxed(c)
123 #define gits_write_baser(v, c) writeq_relaxed(v, c)
125 #define gits_read_cbaser(c) readq_relaxed(c)
126 #define gits_write_cbaser(v, c) writeq_relaxed(v, c)
128 #define gits_write_cwriter(v, c) writeq_relaxed(v, c)
130 #define gicr_read_propbaser(c) readq_relaxed(c)
131 #define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
133 #define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
134 #define gicr_read_pendbaser(c) readq_relaxed(c)
136 #endif /* __ASSEMBLY__ */
137 #endif /* __ASM_ARCH_GICV3_H */