2 * Based on arch/arm/include/asm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #ifndef __ASM_ATOMIC_LL_SC_H
22 #define __ASM_ATOMIC_LL_SC_H
24 #ifndef __ARM64_IN_ATOMIC_IMPL
25 #error "please don't include this file directly"
29 * AArch64 UP and SMP safe atomic ops. We use load exclusive and
30 * store exclusive to ensure that these are atomic. We may loop
31 * to ensure that the update happens.
33 * NOTE: these functions do *not* follow the PCS and must explicitly
34 * save any clobbered registers other than x0 (regardless of return
35 * value). This is achieved through -fcall-saved-* compiler flags for
36 * this file, which unfortunately don't work on a per-function basis
37 * (the optimize attribute silently ignores these options).
40 #define ATOMIC_OP(op, asm_op) \
42 __LL_SC_PREFIX(atomic_##op(int i, atomic_t *v)) \
47 asm volatile("// atomic_" #op "\n" \
49 " " #asm_op " %w0, %w0, %w3\n" \
50 " stxr %w1, %w0, %2\n" \
52 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
55 __LL_SC_EXPORT(atomic_##op);
57 #define ATOMIC_OP_RETURN(op, asm_op) \
59 __LL_SC_PREFIX(atomic_##op##_return(int i, atomic_t *v)) \
64 asm volatile("// atomic_" #op "_return\n" \
66 " " #asm_op " %w0, %w0, %w3\n" \
67 " stlxr %w1, %w0, %2\n" \
69 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
76 __LL_SC_EXPORT(atomic_##op##_return);
78 #define ATOMIC_OPS(op, asm_op) \
79 ATOMIC_OP(op, asm_op) \
80 ATOMIC_OP_RETURN(op, asm_op)
86 ATOMIC_OP(andnot, bic)
91 #undef ATOMIC_OP_RETURN
95 __LL_SC_PREFIX(atomic_cmpxchg(atomic_t *ptr, int old, int new))
102 asm volatile("// atomic_cmpxchg\n"
104 " eor %w0, %w1, %w3\n"
106 " stxr %w0, %w4, %2\n"
109 : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
110 : "Lr" (old), "r" (new));
115 __LL_SC_EXPORT(atomic_cmpxchg);
117 #define ATOMIC64_OP(op, asm_op) \
118 __LL_SC_INLINE void \
119 __LL_SC_PREFIX(atomic64_##op(long i, atomic64_t *v)) \
124 asm volatile("// atomic64_" #op "\n" \
126 " " #asm_op " %0, %0, %3\n" \
127 " stxr %w1, %0, %2\n" \
129 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
132 __LL_SC_EXPORT(atomic64_##op);
134 #define ATOMIC64_OP_RETURN(op, asm_op) \
135 __LL_SC_INLINE long \
136 __LL_SC_PREFIX(atomic64_##op##_return(long i, atomic64_t *v)) \
141 asm volatile("// atomic64_" #op "_return\n" \
143 " " #asm_op " %0, %0, %3\n" \
144 " stlxr %w1, %0, %2\n" \
146 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
153 __LL_SC_EXPORT(atomic64_##op##_return);
155 #define ATOMIC64_OPS(op, asm_op) \
156 ATOMIC64_OP(op, asm_op) \
157 ATOMIC64_OP_RETURN(op, asm_op)
159 ATOMIC64_OPS(add, add)
160 ATOMIC64_OPS(sub, sub)
162 ATOMIC64_OP(and, and)
163 ATOMIC64_OP(andnot, bic)
165 ATOMIC64_OP(xor, eor)
168 #undef ATOMIC64_OP_RETURN
172 __LL_SC_PREFIX(atomic64_cmpxchg(atomic64_t *ptr, long old, long new))
179 asm volatile("// atomic64_cmpxchg\n"
183 " stxr %w0, %4, %2\n"
186 : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
187 : "Lr" (old), "r" (new));
192 __LL_SC_EXPORT(atomic64_cmpxchg);
195 __LL_SC_PREFIX(atomic64_dec_if_positive(atomic64_t *v))
200 asm volatile("// atomic64_dec_if_positive\n"
204 " stlxr %w1, %0, %2\n"
208 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
214 __LL_SC_EXPORT(atomic64_dec_if_positive);
216 #define __CMPXCHG_CASE(w, sz, name, mb, cl) \
217 __LL_SC_INLINE unsigned long \
218 __LL_SC_PREFIX(__cmpxchg_case_##name(volatile void *ptr, \
220 unsigned long new)) \
222 unsigned long tmp, oldval; \
226 "1: ldxr" #sz "\t%" #w "[oldval], %[v]\n" \
227 " eor %" #w "[tmp], %" #w "[oldval], %" #w "[old]\n" \
228 " cbnz %" #w "[tmp], 2f\n" \
229 " stxr" #sz "\t%w[tmp], %" #w "[new], %[v]\n" \
230 " cbnz %w[tmp], 1b\n" \
232 " mov %" #w "[oldval], %" #w "[old]\n" \
234 : [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \
235 [v] "+Q" (*(unsigned long *)ptr) \
236 : [old] "Lr" (old), [new] "r" (new) \
241 __LL_SC_EXPORT(__cmpxchg_case_##name);
243 __CMPXCHG_CASE(w, b, 1, , )
244 __CMPXCHG_CASE(w, h, 2, , )
245 __CMPXCHG_CASE(w, , 4, , )
246 __CMPXCHG_CASE( , , 8, , )
247 __CMPXCHG_CASE(w, b, mb_1, dmb ish, "memory")
248 __CMPXCHG_CASE(w, h, mb_2, dmb ish, "memory")
249 __CMPXCHG_CASE(w, , mb_4, dmb ish, "memory")
250 __CMPXCHG_CASE( , , mb_8, dmb ish, "memory")
252 #undef __CMPXCHG_CASE
254 #define __CMPXCHG_DBL(name, mb, cl) \
256 __LL_SC_PREFIX(__cmpxchg_double##name(unsigned long old1, \
257 unsigned long old2, \
258 unsigned long new1, \
259 unsigned long new2, \
260 volatile void *ptr)) \
262 unsigned long tmp, ret; \
264 asm volatile("// __cmpxchg_double" #name "\n" \
266 "1: ldxp %0, %1, %2\n" \
267 " eor %0, %0, %3\n" \
268 " eor %1, %1, %4\n" \
269 " orr %1, %0, %1\n" \
271 " stxp %w0, %5, %6, %2\n" \
275 : "=&r" (tmp), "=&r" (ret), "+Q" (*(unsigned long *)ptr) \
276 : "r" (old1), "r" (old2), "r" (new1), "r" (new2) \
281 __LL_SC_EXPORT(__cmpxchg_double##name);
284 __CMPXCHG_DBL(_mb, dmb ish, "memory")
288 #endif /* __ASM_ATOMIC_LL_SC_H */