2 * Based on arch/arm/include/asm/ptrace.h
4 * Copyright (C) 1996-2003 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef __ASM_PTRACE_H
20 #define __ASM_PTRACE_H
22 #include <uapi/asm/ptrace.h>
24 /* AArch32-specific ptrace requests */
25 #define COMPAT_PTRACE_GETREGS 12
26 #define COMPAT_PTRACE_SETREGS 13
27 #define COMPAT_PTRACE_GET_THREAD_AREA 22
28 #define COMPAT_PTRACE_SET_SYSCALL 23
29 #define COMPAT_PTRACE_GETVFPREGS 27
30 #define COMPAT_PTRACE_SETVFPREGS 28
31 #define COMPAT_PTRACE_GETHBPREGS 29
32 #define COMPAT_PTRACE_SETHBPREGS 30
34 /* AArch32 CPSR bits */
35 #define COMPAT_PSR_MODE_MASK 0x0000001f
36 #define COMPAT_PSR_MODE_USR 0x00000010
37 #define COMPAT_PSR_MODE_FIQ 0x00000011
38 #define COMPAT_PSR_MODE_IRQ 0x00000012
39 #define COMPAT_PSR_MODE_SVC 0x00000013
40 #define COMPAT_PSR_MODE_ABT 0x00000017
41 #define COMPAT_PSR_MODE_HYP 0x0000001a
42 #define COMPAT_PSR_MODE_UND 0x0000001b
43 #define COMPAT_PSR_MODE_SYS 0x0000001f
44 #define COMPAT_PSR_T_BIT 0x00000020
45 #define COMPAT_PSR_F_BIT 0x00000040
46 #define COMPAT_PSR_I_BIT 0x00000080
47 #define COMPAT_PSR_A_BIT 0x00000100
48 #define COMPAT_PSR_E_BIT 0x00000200
49 #define COMPAT_PSR_J_BIT 0x01000000
50 #define COMPAT_PSR_Q_BIT 0x08000000
51 #define COMPAT_PSR_V_BIT 0x10000000
52 #define COMPAT_PSR_C_BIT 0x20000000
53 #define COMPAT_PSR_Z_BIT 0x40000000
54 #define COMPAT_PSR_N_BIT 0x80000000
55 #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
57 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
58 * process is located in memory.
60 #define COMPAT_PT_TEXT_ADDR 0x10000
61 #define COMPAT_PT_DATA_ADDR 0x10004
62 #define COMPAT_PT_TEXT_END_ADDR 0x10008
65 /* sizeof(struct user) for AArch32 */
66 #define COMPAT_USER_SZ 296
68 /* Architecturally defined mapping between AArch32 and AArch64 registers */
69 #define compat_usr(x) regs[(x)]
70 #define compat_sp regs[13]
71 #define compat_lr regs[14]
72 #define compat_sp_hyp regs[15]
73 #define compat_sp_irq regs[16]
74 #define compat_lr_irq regs[17]
75 #define compat_sp_svc regs[18]
76 #define compat_lr_svc regs[19]
77 #define compat_sp_abt regs[20]
78 #define compat_lr_abt regs[21]
79 #define compat_sp_und regs[22]
80 #define compat_lr_und regs[23]
81 #define compat_r8_fiq regs[24]
82 #define compat_r9_fiq regs[25]
83 #define compat_r10_fiq regs[26]
84 #define compat_r11_fiq regs[27]
85 #define compat_r12_fiq regs[28]
86 #define compat_sp_fiq regs[29]
87 #define compat_lr_fiq regs[30]
90 * This struct defines the way the registers are stored on the stack during an
91 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
92 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
96 struct user_pt_regs user_regs;
108 #define arch_has_single_step() (1)
111 #define compat_thumb_mode(regs) \
112 (((regs)->pstate & COMPAT_PSR_T_BIT))
114 #define compat_thumb_mode(regs) (0)
117 #define user_mode(regs) \
118 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
120 #define compat_user_mode(regs) \
121 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
122 (PSR_MODE32_BIT | PSR_MODE_EL0t))
124 #define processor_mode(regs) \
125 ((regs)->pstate & PSR_MODE_MASK)
127 #define interrupts_enabled(regs) \
128 (!((regs)->pstate & PSR_I_BIT))
130 #define fast_interrupts_enabled(regs) \
131 (!((regs)->pstate & PSR_F_BIT))
133 #define user_stack_pointer(regs) \
137 * Are the current registers suitable for user mode? (used to maintain
138 * security in signal handlers)
140 static inline int valid_user_regs(struct user_pt_regs *regs)
142 if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
143 regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT);
145 /* The T bit is reserved for AArch64 */
146 if (!(regs->pstate & PSR_MODE32_BIT))
147 regs->pstate &= ~COMPAT_PSR_T_BIT;
153 * Force PSR to something logical...
155 regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \
156 COMPAT_PSR_T_BIT | PSR_MODE32_BIT;
158 if (!(regs->pstate & PSR_MODE32_BIT)) {
159 regs->pstate &= ~COMPAT_PSR_T_BIT;
160 regs->pstate |= PSR_MODE_EL0t;
166 #define instruction_pointer(regs) (regs)->pc
169 extern unsigned long profile_pc(struct pt_regs *regs);
171 #define profile_pc(regs) instruction_pointer(regs)
174 extern int aarch32_break_trap(struct pt_regs *regs);
176 #endif /* __ASSEMBLY__ */