2 * Macros for accessing system registers with older binutils.
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ASM_SYSREG_H
21 #define __ASM_SYSREG_H
23 #include <linux/stringify.h>
26 * ARMv8 ARM reserves the following encoding for system registers:
27 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
28 * C5.2, version:ARM DDI 0487A.f)
46 #define sys_reg(op0, op1, crn, crm, op2) \
47 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
48 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
51 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
52 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
53 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
54 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
55 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
57 #ifndef CONFIG_BROKEN_GAS_INST
60 #define __emit_inst(x) .inst (x)
62 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
65 #else /* CONFIG_BROKEN_GAS_INST */
67 #ifndef CONFIG_CPU_BIG_ENDIAN
68 #define __INSTR_BSWAP(x) (x)
69 #else /* CONFIG_CPU_BIG_ENDIAN */
70 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
71 (((x) << 8) & 0x00ff0000) | \
72 (((x) >> 8) & 0x0000ff00) | \
73 (((x) >> 24) & 0x000000ff))
74 #endif /* CONFIG_CPU_BIG_ENDIAN */
77 #define __emit_inst(x) .long __INSTR_BSWAP(x)
78 #else /* __ASSEMBLY__ */
79 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
80 #endif /* __ASSEMBLY__ */
82 #endif /* CONFIG_BROKEN_GAS_INST */
84 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
85 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
87 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
89 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
92 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
93 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
94 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
95 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
96 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
97 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
98 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
99 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
100 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
101 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
102 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
103 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
104 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
105 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
106 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
107 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
108 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
109 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
110 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
111 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
112 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
113 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
115 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
116 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
117 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
119 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
120 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
121 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
122 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
123 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
124 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
125 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
127 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
128 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
129 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
130 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
131 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
132 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
133 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
135 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
136 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
137 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
139 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
140 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
142 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
143 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
145 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
146 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
148 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
149 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
150 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
152 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
154 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
155 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
157 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
158 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
159 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
160 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
161 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
162 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
163 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
164 #define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
166 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
167 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
169 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
170 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
171 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
172 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
173 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
174 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
175 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
176 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
177 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
178 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
179 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
180 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
181 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
183 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
185 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
186 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
187 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
189 #define __PMEV_op2(n) ((n) & 0x7)
190 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
191 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
192 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
193 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
195 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7)
197 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
198 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
199 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
200 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
201 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
203 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
204 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
205 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
206 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
207 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
209 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
210 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
211 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
212 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
213 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
214 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
215 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
216 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
218 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
219 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
220 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
221 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
222 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
223 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
224 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
225 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
226 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
228 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
229 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
230 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
231 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
232 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
233 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
234 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
235 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
236 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
238 /* Common SCTLR_ELx flags. */
239 #define SCTLR_ELx_EE (1 << 25)
240 #define SCTLR_ELx_I (1 << 12)
241 #define SCTLR_ELx_SA (1 << 3)
242 #define SCTLR_ELx_C (1 << 2)
243 #define SCTLR_ELx_A (1 << 1)
244 #define SCTLR_ELx_M 1
246 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
247 SCTLR_ELx_SA | SCTLR_ELx_I)
249 /* SCTLR_EL1 specific flags. */
250 #define SCTLR_EL1_UCI (1 << 26)
251 #define SCTLR_EL1_SPAN (1 << 23)
252 #define SCTLR_EL1_UCT (1 << 15)
253 #define SCTLR_EL1_SED (1 << 8)
254 #define SCTLR_EL1_CP15BEN (1 << 5)
257 #define ID_AA64ISAR0_RDM_SHIFT 28
258 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
259 #define ID_AA64ISAR0_CRC32_SHIFT 16
260 #define ID_AA64ISAR0_SHA2_SHIFT 12
261 #define ID_AA64ISAR0_SHA1_SHIFT 8
262 #define ID_AA64ISAR0_AES_SHIFT 4
265 #define ID_AA64PFR0_GIC_SHIFT 24
266 #define ID_AA64PFR0_ASIMD_SHIFT 20
267 #define ID_AA64PFR0_FP_SHIFT 16
268 #define ID_AA64PFR0_EL3_SHIFT 12
269 #define ID_AA64PFR0_EL2_SHIFT 8
270 #define ID_AA64PFR0_EL1_SHIFT 4
271 #define ID_AA64PFR0_EL0_SHIFT 0
273 #define ID_AA64PFR0_FP_NI 0xf
274 #define ID_AA64PFR0_FP_SUPPORTED 0x0
275 #define ID_AA64PFR0_ASIMD_NI 0xf
276 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
277 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
278 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
279 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
282 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
283 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
284 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
285 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
286 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
287 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
288 #define ID_AA64MMFR0_ASID_SHIFT 4
289 #define ID_AA64MMFR0_PARANGE_SHIFT 0
291 #define ID_AA64MMFR0_TGRAN4_NI 0xf
292 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
293 #define ID_AA64MMFR0_TGRAN64_NI 0xf
294 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
295 #define ID_AA64MMFR0_TGRAN16_NI 0x0
296 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
299 #define ID_AA64MMFR1_PAN_SHIFT 20
300 #define ID_AA64MMFR1_LOR_SHIFT 16
301 #define ID_AA64MMFR1_HPD_SHIFT 12
302 #define ID_AA64MMFR1_VHE_SHIFT 8
303 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
304 #define ID_AA64MMFR1_HADBS_SHIFT 0
306 #define ID_AA64MMFR1_VMIDBITS_8 0
307 #define ID_AA64MMFR1_VMIDBITS_16 2
310 #define ID_AA64MMFR2_LVA_SHIFT 16
311 #define ID_AA64MMFR2_IESB_SHIFT 12
312 #define ID_AA64MMFR2_LSM_SHIFT 8
313 #define ID_AA64MMFR2_UAO_SHIFT 4
314 #define ID_AA64MMFR2_CNP_SHIFT 0
317 #define ID_AA64DFR0_PMSVER_SHIFT 32
318 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
319 #define ID_AA64DFR0_WRPS_SHIFT 20
320 #define ID_AA64DFR0_BRPS_SHIFT 12
321 #define ID_AA64DFR0_PMUVER_SHIFT 8
322 #define ID_AA64DFR0_TRACEVER_SHIFT 4
323 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
325 #define ID_ISAR5_RDM_SHIFT 24
326 #define ID_ISAR5_CRC32_SHIFT 16
327 #define ID_ISAR5_SHA2_SHIFT 12
328 #define ID_ISAR5_SHA1_SHIFT 8
329 #define ID_ISAR5_AES_SHIFT 4
330 #define ID_ISAR5_SEVL_SHIFT 0
332 #define MVFR0_FPROUND_SHIFT 28
333 #define MVFR0_FPSHVEC_SHIFT 24
334 #define MVFR0_FPSQRT_SHIFT 20
335 #define MVFR0_FPDIVIDE_SHIFT 16
336 #define MVFR0_FPTRAP_SHIFT 12
337 #define MVFR0_FPDP_SHIFT 8
338 #define MVFR0_FPSP_SHIFT 4
339 #define MVFR0_SIMD_SHIFT 0
341 #define MVFR1_SIMDFMAC_SHIFT 28
342 #define MVFR1_FPHP_SHIFT 24
343 #define MVFR1_SIMDHP_SHIFT 20
344 #define MVFR1_SIMDSP_SHIFT 16
345 #define MVFR1_SIMDINT_SHIFT 12
346 #define MVFR1_SIMDLS_SHIFT 8
347 #define MVFR1_FPDNAN_SHIFT 4
348 #define MVFR1_FPFTZ_SHIFT 0
351 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
352 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
353 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
355 #define ID_AA64MMFR0_TGRAN4_NI 0xf
356 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
357 #define ID_AA64MMFR0_TGRAN64_NI 0xf
358 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
359 #define ID_AA64MMFR0_TGRAN16_NI 0x0
360 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
362 #if defined(CONFIG_ARM64_4K_PAGES)
363 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
364 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
365 #elif defined(CONFIG_ARM64_16K_PAGES)
366 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
367 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
368 #elif defined(CONFIG_ARM64_64K_PAGES)
369 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
370 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
374 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
375 #define SYS_MPIDR_SAFE_VAL (1UL << 31)
379 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
380 .equ .L__reg_num_x\num, \num
382 .equ .L__reg_num_xzr, 31
384 .macro mrs_s, rt, sreg
385 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
388 .macro msr_s, sreg, rt
389 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
394 #include <linux/types.h>
397 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
398 " .equ .L__reg_num_x\\num, \\num\n"
400 " .equ .L__reg_num_xzr, 31\n"
402 " .macro mrs_s, rt, sreg\n"
403 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))
406 " .macro msr_s, sreg, rt\n"
407 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))
412 * Unlike read_cpuid, calls to read_sysreg are never expected to be
413 * optimized away or replaced with synthetic values.
415 #define read_sysreg(r) ({ \
417 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
422 * The "Z" constraint normally means a zero immediate, but when combined with
423 * the "%x0" template means XZR.
425 #define write_sysreg(v, r) do { \
426 u64 __val = (u64)v; \
427 asm volatile("msr " __stringify(r) ", %x0" \
432 * For registers without architectural names, or simply unsupported by
435 #define read_sysreg_s(r) ({ \
437 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \
441 #define write_sysreg_s(v, r) do { \
442 u64 __val = (u64)v; \
443 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
446 static inline void config_sctlr_el1(u32 clear, u32 set)
450 val = read_sysreg(sctlr_el1);
453 write_sysreg(val, sctlr_el1);
458 #endif /* __ASM_SYSREG_H */