2 * Macros for accessing system registers with older binutils.
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ASM_SYSREG_H
21 #define __ASM_SYSREG_H
23 #include <linux/stringify.h>
26 * ARMv8 ARM reserves the following encoding for system registers:
27 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
28 * C5.2, version:ARM DDI 0487A.f)
46 #define sys_reg(op0, op1, crn, crm, op2) \
47 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
48 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
51 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
52 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
53 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
54 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
55 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
57 #ifndef CONFIG_BROKEN_GAS_INST
60 #define __emit_inst(x) .inst (x)
62 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
65 #else /* CONFIG_BROKEN_GAS_INST */
67 #ifndef CONFIG_CPU_BIG_ENDIAN
68 #define __INSTR_BSWAP(x) (x)
69 #else /* CONFIG_CPU_BIG_ENDIAN */
70 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
71 (((x) << 8) & 0x00ff0000) | \
72 (((x) >> 8) & 0x0000ff00) | \
73 (((x) >> 24) & 0x000000ff))
74 #endif /* CONFIG_CPU_BIG_ENDIAN */
77 #define __emit_inst(x) .long __INSTR_BSWAP(x)
78 #else /* __ASSEMBLY__ */
79 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
80 #endif /* __ASSEMBLY__ */
82 #endif /* CONFIG_BROKEN_GAS_INST */
84 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
85 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
87 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
89 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
92 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
93 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
94 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
95 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
96 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
97 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
98 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
99 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
100 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
101 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
102 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
103 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
104 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
105 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
106 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
107 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
108 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
109 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
110 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
111 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
112 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
113 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
115 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
116 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
117 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
119 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
120 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
121 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
122 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
123 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
124 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
125 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
127 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
128 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
129 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
130 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
131 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
132 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
133 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
135 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
136 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
137 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
139 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
140 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
142 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
143 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
145 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
146 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
148 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
149 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
150 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
152 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
153 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
155 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
157 /* Common SCTLR_ELx flags. */
158 #define SCTLR_ELx_EE (1 << 25)
159 #define SCTLR_ELx_I (1 << 12)
160 #define SCTLR_ELx_SA (1 << 3)
161 #define SCTLR_ELx_C (1 << 2)
162 #define SCTLR_ELx_A (1 << 1)
163 #define SCTLR_ELx_M 1
165 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
166 SCTLR_ELx_SA | SCTLR_ELx_I)
168 /* SCTLR_EL1 specific flags. */
169 #define SCTLR_EL1_UCI (1 << 26)
170 #define SCTLR_EL1_SPAN (1 << 23)
171 #define SCTLR_EL1_UCT (1 << 15)
172 #define SCTLR_EL1_SED (1 << 8)
173 #define SCTLR_EL1_CP15BEN (1 << 5)
176 #define ID_AA64ISAR0_RDM_SHIFT 28
177 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
178 #define ID_AA64ISAR0_CRC32_SHIFT 16
179 #define ID_AA64ISAR0_SHA2_SHIFT 12
180 #define ID_AA64ISAR0_SHA1_SHIFT 8
181 #define ID_AA64ISAR0_AES_SHIFT 4
184 #define ID_AA64PFR0_GIC_SHIFT 24
185 #define ID_AA64PFR0_ASIMD_SHIFT 20
186 #define ID_AA64PFR0_FP_SHIFT 16
187 #define ID_AA64PFR0_EL3_SHIFT 12
188 #define ID_AA64PFR0_EL2_SHIFT 8
189 #define ID_AA64PFR0_EL1_SHIFT 4
190 #define ID_AA64PFR0_EL0_SHIFT 0
192 #define ID_AA64PFR0_FP_NI 0xf
193 #define ID_AA64PFR0_FP_SUPPORTED 0x0
194 #define ID_AA64PFR0_ASIMD_NI 0xf
195 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
196 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
197 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
198 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
201 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
202 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
203 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
204 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
205 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
206 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
207 #define ID_AA64MMFR0_ASID_SHIFT 4
208 #define ID_AA64MMFR0_PARANGE_SHIFT 0
210 #define ID_AA64MMFR0_TGRAN4_NI 0xf
211 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
212 #define ID_AA64MMFR0_TGRAN64_NI 0xf
213 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
214 #define ID_AA64MMFR0_TGRAN16_NI 0x0
215 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
218 #define ID_AA64MMFR1_PAN_SHIFT 20
219 #define ID_AA64MMFR1_LOR_SHIFT 16
220 #define ID_AA64MMFR1_HPD_SHIFT 12
221 #define ID_AA64MMFR1_VHE_SHIFT 8
222 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
223 #define ID_AA64MMFR1_HADBS_SHIFT 0
225 #define ID_AA64MMFR1_VMIDBITS_8 0
226 #define ID_AA64MMFR1_VMIDBITS_16 2
229 #define ID_AA64MMFR2_LVA_SHIFT 16
230 #define ID_AA64MMFR2_IESB_SHIFT 12
231 #define ID_AA64MMFR2_LSM_SHIFT 8
232 #define ID_AA64MMFR2_UAO_SHIFT 4
233 #define ID_AA64MMFR2_CNP_SHIFT 0
236 #define ID_AA64DFR0_PMSVER_SHIFT 32
237 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
238 #define ID_AA64DFR0_WRPS_SHIFT 20
239 #define ID_AA64DFR0_BRPS_SHIFT 12
240 #define ID_AA64DFR0_PMUVER_SHIFT 8
241 #define ID_AA64DFR0_TRACEVER_SHIFT 4
242 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
244 #define ID_ISAR5_RDM_SHIFT 24
245 #define ID_ISAR5_CRC32_SHIFT 16
246 #define ID_ISAR5_SHA2_SHIFT 12
247 #define ID_ISAR5_SHA1_SHIFT 8
248 #define ID_ISAR5_AES_SHIFT 4
249 #define ID_ISAR5_SEVL_SHIFT 0
251 #define MVFR0_FPROUND_SHIFT 28
252 #define MVFR0_FPSHVEC_SHIFT 24
253 #define MVFR0_FPSQRT_SHIFT 20
254 #define MVFR0_FPDIVIDE_SHIFT 16
255 #define MVFR0_FPTRAP_SHIFT 12
256 #define MVFR0_FPDP_SHIFT 8
257 #define MVFR0_FPSP_SHIFT 4
258 #define MVFR0_SIMD_SHIFT 0
260 #define MVFR1_SIMDFMAC_SHIFT 28
261 #define MVFR1_FPHP_SHIFT 24
262 #define MVFR1_SIMDHP_SHIFT 20
263 #define MVFR1_SIMDSP_SHIFT 16
264 #define MVFR1_SIMDINT_SHIFT 12
265 #define MVFR1_SIMDLS_SHIFT 8
266 #define MVFR1_FPDNAN_SHIFT 4
267 #define MVFR1_FPFTZ_SHIFT 0
270 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
271 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
272 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
274 #define ID_AA64MMFR0_TGRAN4_NI 0xf
275 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
276 #define ID_AA64MMFR0_TGRAN64_NI 0xf
277 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
278 #define ID_AA64MMFR0_TGRAN16_NI 0x0
279 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
281 #if defined(CONFIG_ARM64_4K_PAGES)
282 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
283 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
284 #elif defined(CONFIG_ARM64_16K_PAGES)
285 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
286 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
287 #elif defined(CONFIG_ARM64_64K_PAGES)
288 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
289 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
293 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
294 #define SYS_MPIDR_SAFE_VAL (1UL << 31)
298 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
299 .equ .L__reg_num_x\num, \num
301 .equ .L__reg_num_xzr, 31
303 .macro mrs_s, rt, sreg
304 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
307 .macro msr_s, sreg, rt
308 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
313 #include <linux/types.h>
316 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
317 " .equ .L__reg_num_x\\num, \\num\n"
319 " .equ .L__reg_num_xzr, 31\n"
321 " .macro mrs_s, rt, sreg\n"
322 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))
325 " .macro msr_s, sreg, rt\n"
326 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))
331 * Unlike read_cpuid, calls to read_sysreg are never expected to be
332 * optimized away or replaced with synthetic values.
334 #define read_sysreg(r) ({ \
336 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
341 * The "Z" constraint normally means a zero immediate, but when combined with
342 * the "%x0" template means XZR.
344 #define write_sysreg(v, r) do { \
345 u64 __val = (u64)v; \
346 asm volatile("msr " __stringify(r) ", %x0" \
351 * For registers without architectural names, or simply unsupported by
354 #define read_sysreg_s(r) ({ \
356 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \
360 #define write_sysreg_s(v, r) do { \
361 u64 __val = (u64)v; \
362 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
365 static inline void config_sctlr_el1(u32 clear, u32 set)
369 val = read_sysreg(sctlr_el1);
372 write_sysreg(val, sctlr_el1);
377 #endif /* __ASM_SYSREG_H */