2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Derived from arch/arm/include/uapi/asm/kvm.h:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #define KVM_SPSR_EL1 0
26 #define KVM_SPSR_SVC KVM_SPSR_EL1
27 #define KVM_SPSR_ABT 1
28 #define KVM_SPSR_UND 2
29 #define KVM_SPSR_IRQ 3
30 #define KVM_SPSR_FIQ 4
34 #include <asm/types.h>
35 #include <asm/ptrace.h>
37 #define __KVM_HAVE_GUEST_DEBUG
38 #define __KVM_HAVE_IRQ_LINE
40 #define KVM_REG_SIZE(id) \
41 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
44 struct user_pt_regs regs; /* sp = sp_el0 */
49 __u64 spsr[KVM_NR_SPSR];
51 struct user_fpsimd_state fp_regs;
54 /* Supported Processor Types */
55 #define KVM_ARM_TARGET_AEM_V8 0
56 #define KVM_ARM_TARGET_FOUNDATION_V8 1
57 #define KVM_ARM_TARGET_CORTEX_A57 2
58 #define KVM_ARM_TARGET_XGENE_POTENZA 3
60 #define KVM_ARM_NUM_TARGETS 4
62 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
63 #define KVM_ARM_DEVICE_TYPE_SHIFT 0
64 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
65 #define KVM_ARM_DEVICE_ID_SHIFT 16
66 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
68 /* Supported device IDs */
69 #define KVM_ARM_DEVICE_VGIC_V2 0
71 /* Supported VGIC address types */
72 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0
73 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1
75 #define KVM_VGIC_V2_DIST_SIZE 0x1000
76 #define KVM_VGIC_V2_CPU_SIZE 0x2000
78 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
79 #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
81 struct kvm_vcpu_init {
92 struct kvm_guest_debug_arch {
95 struct kvm_debug_exit_arch {
98 struct kvm_sync_regs {
101 struct kvm_arch_memory_slot {
104 /* If you need to interpret the index values, here is the key: */
105 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
106 #define KVM_REG_ARM_COPROC_SHIFT 16
108 /* Normal registers are mapped as coprocessor 16. */
109 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
110 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
112 /* Some registers need more space to represent values. */
113 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
114 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
115 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8
116 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
117 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
118 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
120 /* AArch64 system registers */
121 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
122 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
123 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
124 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
125 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
126 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
127 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
128 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
129 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
130 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
131 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
133 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \
134 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
135 KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
137 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
138 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
139 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
140 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
141 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
142 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
143 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
145 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
147 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
148 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
149 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
151 /* KVM_IRQ_LINE irq field index values */
152 #define KVM_ARM_IRQ_TYPE_SHIFT 24
153 #define KVM_ARM_IRQ_TYPE_MASK 0xff
154 #define KVM_ARM_IRQ_VCPU_SHIFT 16
155 #define KVM_ARM_IRQ_VCPU_MASK 0xff
156 #define KVM_ARM_IRQ_NUM_SHIFT 0
157 #define KVM_ARM_IRQ_NUM_MASK 0xffff
160 #define KVM_ARM_IRQ_TYPE_CPU 0
161 #define KVM_ARM_IRQ_TYPE_SPI 1
162 #define KVM_ARM_IRQ_TYPE_PPI 2
164 /* out-of-kernel GIC cpu interrupt injection irq_number field */
165 #define KVM_ARM_IRQ_CPU_IRQ 0
166 #define KVM_ARM_IRQ_CPU_FIQ 1
168 /* Highest supported SPI, from VGIC_NR_IRQS */
169 #define KVM_ARM_IRQ_GIC_MAX 127
172 #define KVM_PSCI_FN_BASE 0x95c1ba5e
173 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
175 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
176 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
177 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
178 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
180 #define KVM_PSCI_RET_SUCCESS 0
181 #define KVM_PSCI_RET_NI ((unsigned long)-1)
182 #define KVM_PSCI_RET_INVAL ((unsigned long)-2)
183 #define KVM_PSCI_RET_DENIED ((unsigned long)-3)
187 #endif /* __ARM_KVM_H__ */