2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
5 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/bitops.h>
20 #include <linux/bug.h>
21 #include <linux/compiler.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/spinlock.h>
26 #include <linux/stop_machine.h>
27 #include <linux/types.h>
28 #include <linux/uaccess.h>
30 #include <asm/cacheflush.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/fixmap.h>
34 #include <asm/kprobes.h>
36 #define AARCH64_INSN_SF_BIT BIT(31)
37 #define AARCH64_INSN_N_BIT BIT(22)
39 static int aarch64_insn_encoding_class[] = {
40 AARCH64_INSN_CLS_UNKNOWN,
41 AARCH64_INSN_CLS_UNKNOWN,
42 AARCH64_INSN_CLS_UNKNOWN,
43 AARCH64_INSN_CLS_UNKNOWN,
44 AARCH64_INSN_CLS_LDST,
45 AARCH64_INSN_CLS_DP_REG,
46 AARCH64_INSN_CLS_LDST,
47 AARCH64_INSN_CLS_DP_FPSIMD,
48 AARCH64_INSN_CLS_DP_IMM,
49 AARCH64_INSN_CLS_DP_IMM,
50 AARCH64_INSN_CLS_BR_SYS,
51 AARCH64_INSN_CLS_BR_SYS,
52 AARCH64_INSN_CLS_LDST,
53 AARCH64_INSN_CLS_DP_REG,
54 AARCH64_INSN_CLS_LDST,
55 AARCH64_INSN_CLS_DP_FPSIMD,
58 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
60 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
63 /* NOP is an alias of HINT */
64 bool __kprobes aarch64_insn_is_nop(u32 insn)
66 if (!aarch64_insn_is_hint(insn))
69 switch (insn & 0xFE0) {
70 case AARCH64_INSN_HINT_YIELD:
71 case AARCH64_INSN_HINT_WFE:
72 case AARCH64_INSN_HINT_WFI:
73 case AARCH64_INSN_HINT_SEV:
74 case AARCH64_INSN_HINT_SEVL:
81 bool aarch64_insn_is_branch_imm(u32 insn)
83 return (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn) ||
84 aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn) ||
85 aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
86 aarch64_insn_is_bcond(insn));
89 static DEFINE_RAW_SPINLOCK(patch_lock);
91 static void __kprobes *patch_map(void *addr, int fixmap)
93 unsigned long uintaddr = (uintptr_t) addr;
94 bool module = !core_kernel_text(uintaddr);
97 if (module && IS_ENABLED(CONFIG_STRICT_MODULE_RWX))
98 page = vmalloc_to_page(addr);
100 page = phys_to_page(__pa_symbol(addr));
105 return (void *)set_fixmap_offset(fixmap, page_to_phys(page) +
106 (uintaddr & ~PAGE_MASK));
109 static void __kprobes patch_unmap(int fixmap)
111 clear_fixmap(fixmap);
114 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
117 int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
122 ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
124 *insnp = le32_to_cpu(val);
129 static int __kprobes __aarch64_insn_write(void *addr, u32 insn)
132 unsigned long flags = 0;
135 raw_spin_lock_irqsave(&patch_lock, flags);
136 waddr = patch_map(addr, FIX_TEXT_POKE0);
138 ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE);
140 patch_unmap(FIX_TEXT_POKE0);
141 raw_spin_unlock_irqrestore(&patch_lock, flags);
146 int __kprobes aarch64_insn_write(void *addr, u32 insn)
148 insn = cpu_to_le32(insn);
149 return __aarch64_insn_write(addr, insn);
152 static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
154 if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
157 return aarch64_insn_is_b(insn) ||
158 aarch64_insn_is_bl(insn) ||
159 aarch64_insn_is_svc(insn) ||
160 aarch64_insn_is_hvc(insn) ||
161 aarch64_insn_is_smc(insn) ||
162 aarch64_insn_is_brk(insn) ||
163 aarch64_insn_is_nop(insn);
166 bool __kprobes aarch64_insn_uses_literal(u32 insn)
168 /* ldr/ldrsw (literal), prfm */
170 return aarch64_insn_is_ldr_lit(insn) ||
171 aarch64_insn_is_ldrsw_lit(insn) ||
172 aarch64_insn_is_adr_adrp(insn) ||
173 aarch64_insn_is_prfm_lit(insn);
176 bool __kprobes aarch64_insn_is_branch(u32 insn)
178 /* b, bl, cb*, tb*, b.cond, br, blr */
180 return aarch64_insn_is_b(insn) ||
181 aarch64_insn_is_bl(insn) ||
182 aarch64_insn_is_cbz(insn) ||
183 aarch64_insn_is_cbnz(insn) ||
184 aarch64_insn_is_tbz(insn) ||
185 aarch64_insn_is_tbnz(insn) ||
186 aarch64_insn_is_ret(insn) ||
187 aarch64_insn_is_br(insn) ||
188 aarch64_insn_is_blr(insn) ||
189 aarch64_insn_is_bcond(insn);
193 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
194 * Section B2.6.5 "Concurrent modification and execution of instructions":
195 * Concurrent modification and execution of instructions can lead to the
196 * resulting instruction performing any behavior that can be achieved by
197 * executing any sequence of instructions that can be executed from the
198 * same Exception level, except where the instruction before modification
199 * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
200 * or SMC instruction.
202 bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
204 return __aarch64_insn_hotpatch_safe(old_insn) &&
205 __aarch64_insn_hotpatch_safe(new_insn);
208 int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
213 /* A64 instructions must be word aligned */
214 if ((uintptr_t)tp & 0x3)
217 ret = aarch64_insn_write(tp, insn);
219 flush_icache_range((uintptr_t)tp,
220 (uintptr_t)tp + AARCH64_INSN_SIZE);
225 struct aarch64_insn_patch {
232 static int __kprobes aarch64_insn_patch_text_cb(void *arg)
235 struct aarch64_insn_patch *pp = arg;
237 /* The first CPU becomes master */
238 if (atomic_inc_return(&pp->cpu_count) == 1) {
239 for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
240 ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
243 * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
244 * which ends with "dsb; isb" pair guaranteeing global
247 /* Notify other processors with an additional increment. */
248 atomic_inc(&pp->cpu_count);
250 while (atomic_read(&pp->cpu_count) <= num_online_cpus())
258 int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
260 struct aarch64_insn_patch patch = {
264 .cpu_count = ATOMIC_INIT(0),
270 return stop_machine(aarch64_insn_patch_text_cb, &patch,
274 int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
279 /* Unsafe to patch multiple instructions without synchronizaiton */
281 ret = aarch64_insn_read(addrs[0], &insn);
285 if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
287 * ARMv8 architecture doesn't guarantee all CPUs see
288 * the new instruction after returning from function
289 * aarch64_insn_patch_text_nosync(). So send IPIs to
290 * all other CPUs to achieve instruction
293 ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
294 kick_all_cpus_sync();
299 return aarch64_insn_patch_text_sync(addrs, insns, cnt);
302 static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
303 u32 *maskp, int *shiftp)
309 case AARCH64_INSN_IMM_26:
313 case AARCH64_INSN_IMM_19:
317 case AARCH64_INSN_IMM_16:
321 case AARCH64_INSN_IMM_14:
325 case AARCH64_INSN_IMM_12:
329 case AARCH64_INSN_IMM_9:
333 case AARCH64_INSN_IMM_7:
337 case AARCH64_INSN_IMM_6:
338 case AARCH64_INSN_IMM_S:
342 case AARCH64_INSN_IMM_R:
356 #define ADR_IMM_HILOSPLIT 2
357 #define ADR_IMM_SIZE SZ_2M
358 #define ADR_IMM_LOMASK ((1 << ADR_IMM_HILOSPLIT) - 1)
359 #define ADR_IMM_HIMASK ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1)
360 #define ADR_IMM_LOSHIFT 29
361 #define ADR_IMM_HISHIFT 5
363 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn)
365 u32 immlo, immhi, mask;
369 case AARCH64_INSN_IMM_ADR:
371 immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK;
372 immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK;
373 insn = (immhi << ADR_IMM_HILOSPLIT) | immlo;
374 mask = ADR_IMM_SIZE - 1;
377 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
378 pr_err("aarch64_insn_decode_immediate: unknown immediate encoding %d\n",
384 return (insn >> shift) & mask;
387 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
390 u32 immlo, immhi, mask;
393 if (insn == AARCH64_BREAK_FAULT)
394 return AARCH64_BREAK_FAULT;
397 case AARCH64_INSN_IMM_ADR:
399 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT;
400 imm >>= ADR_IMM_HILOSPLIT;
401 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT;
403 mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) |
404 (ADR_IMM_HIMASK << ADR_IMM_HISHIFT));
407 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
408 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
410 return AARCH64_BREAK_FAULT;
414 /* Update the immediate field. */
415 insn &= ~(mask << shift);
416 insn |= (imm & mask) << shift;
421 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
427 case AARCH64_INSN_REGTYPE_RT:
428 case AARCH64_INSN_REGTYPE_RD:
431 case AARCH64_INSN_REGTYPE_RN:
434 case AARCH64_INSN_REGTYPE_RT2:
435 case AARCH64_INSN_REGTYPE_RA:
438 case AARCH64_INSN_REGTYPE_RM:
442 pr_err("%s: unknown register type encoding %d\n", __func__,
447 return (insn >> shift) & GENMASK(4, 0);
450 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
452 enum aarch64_insn_register reg)
456 if (insn == AARCH64_BREAK_FAULT)
457 return AARCH64_BREAK_FAULT;
459 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
460 pr_err("%s: unknown register encoding %d\n", __func__, reg);
461 return AARCH64_BREAK_FAULT;
465 case AARCH64_INSN_REGTYPE_RT:
466 case AARCH64_INSN_REGTYPE_RD:
469 case AARCH64_INSN_REGTYPE_RN:
472 case AARCH64_INSN_REGTYPE_RT2:
473 case AARCH64_INSN_REGTYPE_RA:
476 case AARCH64_INSN_REGTYPE_RM:
480 pr_err("%s: unknown register type encoding %d\n", __func__,
482 return AARCH64_BREAK_FAULT;
485 insn &= ~(GENMASK(4, 0) << shift);
486 insn |= reg << shift;
491 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
497 case AARCH64_INSN_SIZE_8:
500 case AARCH64_INSN_SIZE_16:
503 case AARCH64_INSN_SIZE_32:
506 case AARCH64_INSN_SIZE_64:
510 pr_err("%s: unknown size encoding %d\n", __func__, type);
511 return AARCH64_BREAK_FAULT;
514 insn &= ~GENMASK(31, 30);
520 static inline long branch_imm_common(unsigned long pc, unsigned long addr,
525 if ((pc & 0x3) || (addr & 0x3)) {
526 pr_err("%s: A64 instructions must be word aligned\n", __func__);
530 offset = ((long)addr - (long)pc);
532 if (offset < -range || offset >= range) {
533 pr_err("%s: offset out of range\n", __func__);
540 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
541 enum aarch64_insn_branch_type type)
547 * B/BL support [-128M, 128M) offset
548 * ARM64 virtual address arrangement guarantees all kernel and module
549 * texts are within +/-128M.
551 offset = branch_imm_common(pc, addr, SZ_128M);
552 if (offset >= SZ_128M)
553 return AARCH64_BREAK_FAULT;
556 case AARCH64_INSN_BRANCH_LINK:
557 insn = aarch64_insn_get_bl_value();
559 case AARCH64_INSN_BRANCH_NOLINK:
560 insn = aarch64_insn_get_b_value();
563 pr_err("%s: unknown branch encoding %d\n", __func__, type);
564 return AARCH64_BREAK_FAULT;
567 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
571 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
572 enum aarch64_insn_register reg,
573 enum aarch64_insn_variant variant,
574 enum aarch64_insn_branch_type type)
579 offset = branch_imm_common(pc, addr, SZ_1M);
581 return AARCH64_BREAK_FAULT;
584 case AARCH64_INSN_BRANCH_COMP_ZERO:
585 insn = aarch64_insn_get_cbz_value();
587 case AARCH64_INSN_BRANCH_COMP_NONZERO:
588 insn = aarch64_insn_get_cbnz_value();
591 pr_err("%s: unknown branch encoding %d\n", __func__, type);
592 return AARCH64_BREAK_FAULT;
596 case AARCH64_INSN_VARIANT_32BIT:
598 case AARCH64_INSN_VARIANT_64BIT:
599 insn |= AARCH64_INSN_SF_BIT;
602 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
603 return AARCH64_BREAK_FAULT;
606 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
608 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
612 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
613 enum aarch64_insn_condition cond)
618 offset = branch_imm_common(pc, addr, SZ_1M);
620 insn = aarch64_insn_get_bcond_value();
622 if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) {
623 pr_err("%s: unknown condition encoding %d\n", __func__, cond);
624 return AARCH64_BREAK_FAULT;
628 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
632 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
634 return aarch64_insn_get_hint_value() | op;
637 u32 __kprobes aarch64_insn_gen_nop(void)
639 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
642 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
643 enum aarch64_insn_branch_type type)
648 case AARCH64_INSN_BRANCH_NOLINK:
649 insn = aarch64_insn_get_br_value();
651 case AARCH64_INSN_BRANCH_LINK:
652 insn = aarch64_insn_get_blr_value();
654 case AARCH64_INSN_BRANCH_RETURN:
655 insn = aarch64_insn_get_ret_value();
658 pr_err("%s: unknown branch encoding %d\n", __func__, type);
659 return AARCH64_BREAK_FAULT;
662 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
665 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
666 enum aarch64_insn_register base,
667 enum aarch64_insn_register offset,
668 enum aarch64_insn_size_type size,
669 enum aarch64_insn_ldst_type type)
674 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
675 insn = aarch64_insn_get_ldr_reg_value();
677 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
678 insn = aarch64_insn_get_str_reg_value();
681 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
682 return AARCH64_BREAK_FAULT;
685 insn = aarch64_insn_encode_ldst_size(size, insn);
687 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
689 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
692 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
696 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
697 enum aarch64_insn_register reg2,
698 enum aarch64_insn_register base,
700 enum aarch64_insn_variant variant,
701 enum aarch64_insn_ldst_type type)
707 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
708 insn = aarch64_insn_get_ldp_pre_value();
710 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
711 insn = aarch64_insn_get_stp_pre_value();
713 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
714 insn = aarch64_insn_get_ldp_post_value();
716 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
717 insn = aarch64_insn_get_stp_post_value();
720 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
721 return AARCH64_BREAK_FAULT;
725 case AARCH64_INSN_VARIANT_32BIT:
726 if ((offset & 0x3) || (offset < -256) || (offset > 252)) {
727 pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n",
729 return AARCH64_BREAK_FAULT;
733 case AARCH64_INSN_VARIANT_64BIT:
734 if ((offset & 0x7) || (offset < -512) || (offset > 504)) {
735 pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n",
737 return AARCH64_BREAK_FAULT;
740 insn |= AARCH64_INSN_SF_BIT;
743 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
744 return AARCH64_BREAK_FAULT;
747 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
750 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
753 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
756 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
760 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
761 enum aarch64_insn_register src,
762 int imm, enum aarch64_insn_variant variant,
763 enum aarch64_insn_adsb_type type)
768 case AARCH64_INSN_ADSB_ADD:
769 insn = aarch64_insn_get_add_imm_value();
771 case AARCH64_INSN_ADSB_SUB:
772 insn = aarch64_insn_get_sub_imm_value();
774 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
775 insn = aarch64_insn_get_adds_imm_value();
777 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
778 insn = aarch64_insn_get_subs_imm_value();
781 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
782 return AARCH64_BREAK_FAULT;
786 case AARCH64_INSN_VARIANT_32BIT:
788 case AARCH64_INSN_VARIANT_64BIT:
789 insn |= AARCH64_INSN_SF_BIT;
792 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
793 return AARCH64_BREAK_FAULT;
796 if (imm & ~(SZ_4K - 1)) {
797 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
798 return AARCH64_BREAK_FAULT;
801 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
803 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
805 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
808 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
809 enum aarch64_insn_register src,
811 enum aarch64_insn_variant variant,
812 enum aarch64_insn_bitfield_type type)
818 case AARCH64_INSN_BITFIELD_MOVE:
819 insn = aarch64_insn_get_bfm_value();
821 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
822 insn = aarch64_insn_get_ubfm_value();
824 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
825 insn = aarch64_insn_get_sbfm_value();
828 pr_err("%s: unknown bitfield encoding %d\n", __func__, type);
829 return AARCH64_BREAK_FAULT;
833 case AARCH64_INSN_VARIANT_32BIT:
834 mask = GENMASK(4, 0);
836 case AARCH64_INSN_VARIANT_64BIT:
837 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
838 mask = GENMASK(5, 0);
841 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
842 return AARCH64_BREAK_FAULT;
846 pr_err("%s: invalid immr encoding %d\n", __func__, immr);
847 return AARCH64_BREAK_FAULT;
850 pr_err("%s: invalid imms encoding %d\n", __func__, imms);
851 return AARCH64_BREAK_FAULT;
854 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
856 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
858 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
860 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
863 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
865 enum aarch64_insn_variant variant,
866 enum aarch64_insn_movewide_type type)
871 case AARCH64_INSN_MOVEWIDE_ZERO:
872 insn = aarch64_insn_get_movz_value();
874 case AARCH64_INSN_MOVEWIDE_KEEP:
875 insn = aarch64_insn_get_movk_value();
877 case AARCH64_INSN_MOVEWIDE_INVERSE:
878 insn = aarch64_insn_get_movn_value();
881 pr_err("%s: unknown movewide encoding %d\n", __func__, type);
882 return AARCH64_BREAK_FAULT;
885 if (imm & ~(SZ_64K - 1)) {
886 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
887 return AARCH64_BREAK_FAULT;
891 case AARCH64_INSN_VARIANT_32BIT:
892 if (shift != 0 && shift != 16) {
893 pr_err("%s: invalid shift encoding %d\n", __func__,
895 return AARCH64_BREAK_FAULT;
898 case AARCH64_INSN_VARIANT_64BIT:
899 insn |= AARCH64_INSN_SF_BIT;
900 if (shift != 0 && shift != 16 && shift != 32 && shift != 48) {
901 pr_err("%s: invalid shift encoding %d\n", __func__,
903 return AARCH64_BREAK_FAULT;
907 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
908 return AARCH64_BREAK_FAULT;
911 insn |= (shift >> 4) << 21;
913 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
915 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
918 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
919 enum aarch64_insn_register src,
920 enum aarch64_insn_register reg,
922 enum aarch64_insn_variant variant,
923 enum aarch64_insn_adsb_type type)
928 case AARCH64_INSN_ADSB_ADD:
929 insn = aarch64_insn_get_add_value();
931 case AARCH64_INSN_ADSB_SUB:
932 insn = aarch64_insn_get_sub_value();
934 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
935 insn = aarch64_insn_get_adds_value();
937 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
938 insn = aarch64_insn_get_subs_value();
941 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
942 return AARCH64_BREAK_FAULT;
946 case AARCH64_INSN_VARIANT_32BIT:
947 if (shift & ~(SZ_32 - 1)) {
948 pr_err("%s: invalid shift encoding %d\n", __func__,
950 return AARCH64_BREAK_FAULT;
953 case AARCH64_INSN_VARIANT_64BIT:
954 insn |= AARCH64_INSN_SF_BIT;
955 if (shift & ~(SZ_64 - 1)) {
956 pr_err("%s: invalid shift encoding %d\n", __func__,
958 return AARCH64_BREAK_FAULT;
962 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
963 return AARCH64_BREAK_FAULT;
967 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
969 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
971 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
973 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
976 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
977 enum aarch64_insn_register src,
978 enum aarch64_insn_variant variant,
979 enum aarch64_insn_data1_type type)
984 case AARCH64_INSN_DATA1_REVERSE_16:
985 insn = aarch64_insn_get_rev16_value();
987 case AARCH64_INSN_DATA1_REVERSE_32:
988 insn = aarch64_insn_get_rev32_value();
990 case AARCH64_INSN_DATA1_REVERSE_64:
991 if (variant != AARCH64_INSN_VARIANT_64BIT) {
992 pr_err("%s: invalid variant for reverse64 %d\n",
994 return AARCH64_BREAK_FAULT;
996 insn = aarch64_insn_get_rev64_value();
999 pr_err("%s: unknown data1 encoding %d\n", __func__, type);
1000 return AARCH64_BREAK_FAULT;
1004 case AARCH64_INSN_VARIANT_32BIT:
1006 case AARCH64_INSN_VARIANT_64BIT:
1007 insn |= AARCH64_INSN_SF_BIT;
1010 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1011 return AARCH64_BREAK_FAULT;
1014 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1016 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1019 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
1020 enum aarch64_insn_register src,
1021 enum aarch64_insn_register reg,
1022 enum aarch64_insn_variant variant,
1023 enum aarch64_insn_data2_type type)
1028 case AARCH64_INSN_DATA2_UDIV:
1029 insn = aarch64_insn_get_udiv_value();
1031 case AARCH64_INSN_DATA2_SDIV:
1032 insn = aarch64_insn_get_sdiv_value();
1034 case AARCH64_INSN_DATA2_LSLV:
1035 insn = aarch64_insn_get_lslv_value();
1037 case AARCH64_INSN_DATA2_LSRV:
1038 insn = aarch64_insn_get_lsrv_value();
1040 case AARCH64_INSN_DATA2_ASRV:
1041 insn = aarch64_insn_get_asrv_value();
1043 case AARCH64_INSN_DATA2_RORV:
1044 insn = aarch64_insn_get_rorv_value();
1047 pr_err("%s: unknown data2 encoding %d\n", __func__, type);
1048 return AARCH64_BREAK_FAULT;
1052 case AARCH64_INSN_VARIANT_32BIT:
1054 case AARCH64_INSN_VARIANT_64BIT:
1055 insn |= AARCH64_INSN_SF_BIT;
1058 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1059 return AARCH64_BREAK_FAULT;
1062 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1064 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1066 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1069 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
1070 enum aarch64_insn_register src,
1071 enum aarch64_insn_register reg1,
1072 enum aarch64_insn_register reg2,
1073 enum aarch64_insn_variant variant,
1074 enum aarch64_insn_data3_type type)
1079 case AARCH64_INSN_DATA3_MADD:
1080 insn = aarch64_insn_get_madd_value();
1082 case AARCH64_INSN_DATA3_MSUB:
1083 insn = aarch64_insn_get_msub_value();
1086 pr_err("%s: unknown data3 encoding %d\n", __func__, type);
1087 return AARCH64_BREAK_FAULT;
1091 case AARCH64_INSN_VARIANT_32BIT:
1093 case AARCH64_INSN_VARIANT_64BIT:
1094 insn |= AARCH64_INSN_SF_BIT;
1097 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1098 return AARCH64_BREAK_FAULT;
1101 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1103 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
1105 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
1108 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
1112 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
1113 enum aarch64_insn_register src,
1114 enum aarch64_insn_register reg,
1116 enum aarch64_insn_variant variant,
1117 enum aarch64_insn_logic_type type)
1122 case AARCH64_INSN_LOGIC_AND:
1123 insn = aarch64_insn_get_and_value();
1125 case AARCH64_INSN_LOGIC_BIC:
1126 insn = aarch64_insn_get_bic_value();
1128 case AARCH64_INSN_LOGIC_ORR:
1129 insn = aarch64_insn_get_orr_value();
1131 case AARCH64_INSN_LOGIC_ORN:
1132 insn = aarch64_insn_get_orn_value();
1134 case AARCH64_INSN_LOGIC_EOR:
1135 insn = aarch64_insn_get_eor_value();
1137 case AARCH64_INSN_LOGIC_EON:
1138 insn = aarch64_insn_get_eon_value();
1140 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1141 insn = aarch64_insn_get_ands_value();
1143 case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
1144 insn = aarch64_insn_get_bics_value();
1147 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1148 return AARCH64_BREAK_FAULT;
1152 case AARCH64_INSN_VARIANT_32BIT:
1153 if (shift & ~(SZ_32 - 1)) {
1154 pr_err("%s: invalid shift encoding %d\n", __func__,
1156 return AARCH64_BREAK_FAULT;
1159 case AARCH64_INSN_VARIANT_64BIT:
1160 insn |= AARCH64_INSN_SF_BIT;
1161 if (shift & ~(SZ_64 - 1)) {
1162 pr_err("%s: invalid shift encoding %d\n", __func__,
1164 return AARCH64_BREAK_FAULT;
1168 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1169 return AARCH64_BREAK_FAULT;
1173 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1175 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1177 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1179 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1183 * Decode the imm field of a branch, and return the byte offset as a
1184 * signed value (so it can be used when computing a new branch
1187 s32 aarch64_get_branch_offset(u32 insn)
1191 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) {
1192 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn);
1193 return (imm << 6) >> 4;
1196 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1197 aarch64_insn_is_bcond(insn)) {
1198 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn);
1199 return (imm << 13) >> 11;
1202 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) {
1203 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn);
1204 return (imm << 18) >> 16;
1207 /* Unhandled instruction */
1212 * Encode the displacement of a branch in the imm field and return the
1213 * updated instruction.
1215 u32 aarch64_set_branch_offset(u32 insn, s32 offset)
1217 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn))
1218 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
1221 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1222 aarch64_insn_is_bcond(insn))
1223 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
1226 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn))
1227 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_14, insn,
1230 /* Unhandled instruction */
1234 s32 aarch64_insn_adrp_get_offset(u32 insn)
1236 BUG_ON(!aarch64_insn_is_adrp(insn));
1237 return aarch64_insn_decode_immediate(AARCH64_INSN_IMM_ADR, insn) << 12;
1240 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
1242 BUG_ON(!aarch64_insn_is_adrp(insn));
1243 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn,
1248 * Extract the Op/CR data from a msr/mrs instruction.
1250 u32 aarch64_insn_extract_system_reg(u32 insn)
1252 return (insn & 0x1FFFE0) >> 5;
1255 bool aarch32_insn_is_wide(u32 insn)
1257 return insn >= 0xe800;
1261 * Macros/defines for extracting register numbers from instruction.
1263 u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
1265 return (insn & (0xf << offset)) >> offset;
1268 #define OPC2_MASK 0x7
1269 #define OPC2_OFFSET 5
1270 u32 aarch32_insn_mcr_extract_opc2(u32 insn)
1272 return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
1275 #define CRM_MASK 0xf
1276 u32 aarch32_insn_mcr_extract_crm(u32 insn)
1278 return insn & CRM_MASK;
1281 static bool __kprobes __check_eq(unsigned long pstate)
1283 return (pstate & PSR_Z_BIT) != 0;
1286 static bool __kprobes __check_ne(unsigned long pstate)
1288 return (pstate & PSR_Z_BIT) == 0;
1291 static bool __kprobes __check_cs(unsigned long pstate)
1293 return (pstate & PSR_C_BIT) != 0;
1296 static bool __kprobes __check_cc(unsigned long pstate)
1298 return (pstate & PSR_C_BIT) == 0;
1301 static bool __kprobes __check_mi(unsigned long pstate)
1303 return (pstate & PSR_N_BIT) != 0;
1306 static bool __kprobes __check_pl(unsigned long pstate)
1308 return (pstate & PSR_N_BIT) == 0;
1311 static bool __kprobes __check_vs(unsigned long pstate)
1313 return (pstate & PSR_V_BIT) != 0;
1316 static bool __kprobes __check_vc(unsigned long pstate)
1318 return (pstate & PSR_V_BIT) == 0;
1321 static bool __kprobes __check_hi(unsigned long pstate)
1323 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1324 return (pstate & PSR_C_BIT) != 0;
1327 static bool __kprobes __check_ls(unsigned long pstate)
1329 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1330 return (pstate & PSR_C_BIT) == 0;
1333 static bool __kprobes __check_ge(unsigned long pstate)
1335 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1336 return (pstate & PSR_N_BIT) == 0;
1339 static bool __kprobes __check_lt(unsigned long pstate)
1341 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1342 return (pstate & PSR_N_BIT) != 0;
1345 static bool __kprobes __check_gt(unsigned long pstate)
1347 /*PSR_N_BIT ^= PSR_V_BIT */
1348 unsigned long temp = pstate ^ (pstate << 3);
1350 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
1351 return (temp & PSR_N_BIT) == 0;
1354 static bool __kprobes __check_le(unsigned long pstate)
1356 /*PSR_N_BIT ^= PSR_V_BIT */
1357 unsigned long temp = pstate ^ (pstate << 3);
1359 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
1360 return (temp & PSR_N_BIT) != 0;
1363 static bool __kprobes __check_al(unsigned long pstate)
1369 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
1370 * it behaves identically to 0b1110 ("al").
1372 pstate_check_t * const aarch32_opcode_cond_checks[16] = {
1373 __check_eq, __check_ne, __check_cs, __check_cc,
1374 __check_mi, __check_pl, __check_vs, __check_vc,
1375 __check_hi, __check_ls, __check_ge, __check_lt,
1376 __check_gt, __check_le, __check_al, __check_al