2 * AArch64 loadable module support.
4 * Copyright (C) 2012 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 * Author: Will Deacon <will.deacon@arm.com>
21 #include <linux/bitops.h>
22 #include <linux/elf.h>
23 #include <linux/gfp.h>
24 #include <linux/kernel.h>
26 #include <linux/moduleloader.h>
27 #include <linux/vmalloc.h>
29 void *module_alloc(unsigned long size)
31 return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
32 GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
33 __builtin_return_address(0));
36 enum aarch64_reloc_op {
43 static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val)
49 return val - (u64)place;
51 return (val & ~0xfff) - ((u64)place & ~0xfff);
56 pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
60 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
62 u64 imm_mask = (1 << len) - 1;
63 s64 sval = do_reloc(op, place, val);
76 pr_err("Invalid length (%d) for data relocation\n", len);
81 * Extract the upper value bits (including the sign bit) and
82 * shift them to bit 0.
84 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
87 * Overflow has occurred if the value is not representable in
88 * len bits (i.e the bottom len bits are not sign-extended and
89 * the top bits are not all zero).
91 if ((u64)(sval + 1) > 2)
97 enum aarch64_imm_type {
109 static u32 encode_insn_immediate(enum aarch64_imm_type type, u32 insn, u64 imm)
111 u32 immlo, immhi, lomask, himask, mask;
117 * For signed MOVW relocations, we have to manipulate the
118 * instruction encoding depending on whether or not the
119 * immediate is less than zero.
123 /* >=0: Set the instruction to MOVZ (opcode 10b). */
127 * <0: Set the instruction to MOVN (opcode 00b).
128 * Since we've masked the opcode already, we
129 * don't need to do anything other than
130 * inverting the new immediate field.
141 immlo = imm & lomask;
143 immhi = imm & himask;
144 imm = (immlo << 24) | (immhi);
145 mask = (lomask << 24) | (himask);
173 pr_err("encode_insn_immediate: unknown immediate encoding %d\n",
178 /* Update the immediate field. */
179 insn &= ~(mask << shift);
180 insn |= (imm & mask) << shift;
185 static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
186 int lsb, enum aarch64_imm_type imm_type)
190 u32 insn = *(u32 *)place;
192 sval = do_reloc(op, place, val);
196 /* Update the instruction with the new encoding. */
197 *(u32 *)place = encode_insn_immediate(imm_type, insn, imm);
199 /* Shift out the immediate field. */
203 * For unsigned immediates, the overflow check is straightforward.
204 * For signed immediates, the sign bit is actually the bit past the
205 * most significant bit of the field.
206 * The INSN_IMM_16 immediate type is unsigned.
208 if (imm_type != INSN_IMM_16) {
213 /* Check the upper bits depending on the sign of the immediate. */
214 if ((u64)sval > limit)
220 static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val,
221 int lsb, int len, enum aarch64_imm_type imm_type)
225 u32 insn = *(u32 *)place;
227 /* Calculate the relocation value. */
228 sval = do_reloc(op, place, val);
231 /* Extract the value bits and shift them to bit 0. */
232 imm_mask = (BIT(lsb + len) - 1) >> lsb;
233 imm = sval & imm_mask;
235 /* Update the instruction's immediate field. */
236 *(u32 *)place = encode_insn_immediate(imm_type, insn, imm);
239 * Extract the upper value bits (including the sign bit) and
240 * shift them to bit 0.
242 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
245 * Overflow has occurred if the upper bits are not all equal to
246 * the sign bit of the value.
248 if ((u64)(sval + 1) >= 2)
254 int apply_relocate_add(Elf64_Shdr *sechdrs,
256 unsigned int symindex,
266 Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
268 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
269 /* loc corresponds to P in the AArch64 ELF document. */
270 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
273 /* sym is the ELF symbol we're referring to. */
274 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
275 + ELF64_R_SYM(rel[i].r_info);
277 /* val corresponds to (S + A) in the AArch64 ELF document. */
278 val = sym->st_value + rel[i].r_addend;
280 /* Check for overflow by default. */
281 overflow_check = true;
283 /* Perform the static relocation. */
284 switch (ELF64_R_TYPE(rel[i].r_info)) {
285 /* Null relocations. */
291 /* Data relocations. */
292 case R_AARCH64_ABS64:
293 overflow_check = false;
294 ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
296 case R_AARCH64_ABS32:
297 ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
299 case R_AARCH64_ABS16:
300 ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
302 case R_AARCH64_PREL64:
303 overflow_check = false;
304 ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
306 case R_AARCH64_PREL32:
307 ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
309 case R_AARCH64_PREL16:
310 ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
313 /* MOVW instruction relocations. */
314 case R_AARCH64_MOVW_UABS_G0_NC:
315 overflow_check = false;
316 case R_AARCH64_MOVW_UABS_G0:
317 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
320 case R_AARCH64_MOVW_UABS_G1_NC:
321 overflow_check = false;
322 case R_AARCH64_MOVW_UABS_G1:
323 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
326 case R_AARCH64_MOVW_UABS_G2_NC:
327 overflow_check = false;
328 case R_AARCH64_MOVW_UABS_G2:
329 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
332 case R_AARCH64_MOVW_UABS_G3:
333 /* We're using the top bits so we can't overflow. */
334 overflow_check = false;
335 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
338 case R_AARCH64_MOVW_SABS_G0:
339 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
342 case R_AARCH64_MOVW_SABS_G1:
343 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
346 case R_AARCH64_MOVW_SABS_G2:
347 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
350 case R_AARCH64_MOVW_PREL_G0_NC:
351 overflow_check = false;
352 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
355 case R_AARCH64_MOVW_PREL_G0:
356 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
359 case R_AARCH64_MOVW_PREL_G1_NC:
360 overflow_check = false;
361 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
364 case R_AARCH64_MOVW_PREL_G1:
365 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
368 case R_AARCH64_MOVW_PREL_G2_NC:
369 overflow_check = false;
370 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
373 case R_AARCH64_MOVW_PREL_G2:
374 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
377 case R_AARCH64_MOVW_PREL_G3:
378 /* We're using the top bits so we can't overflow. */
379 overflow_check = false;
380 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
384 /* Immediate instruction relocations. */
385 case R_AARCH64_LD_PREL_LO19:
386 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
389 case R_AARCH64_ADR_PREL_LO21:
390 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
393 case R_AARCH64_ADR_PREL_PG_HI21_NC:
394 overflow_check = false;
395 case R_AARCH64_ADR_PREL_PG_HI21:
396 ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
399 case R_AARCH64_ADD_ABS_LO12_NC:
400 case R_AARCH64_LDST8_ABS_LO12_NC:
401 overflow_check = false;
402 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
405 case R_AARCH64_LDST16_ABS_LO12_NC:
406 overflow_check = false;
407 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
410 case R_AARCH64_LDST32_ABS_LO12_NC:
411 overflow_check = false;
412 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
415 case R_AARCH64_LDST64_ABS_LO12_NC:
416 overflow_check = false;
417 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
420 case R_AARCH64_LDST128_ABS_LO12_NC:
421 overflow_check = false;
422 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
425 case R_AARCH64_TSTBR14:
426 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
429 case R_AARCH64_CONDBR19:
430 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
433 case R_AARCH64_JUMP26:
434 case R_AARCH64_CALL26:
435 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
440 pr_err("module %s: unsupported RELA relocation: %llu\n",
441 me->name, ELF64_R_TYPE(rel[i].r_info));
445 if (overflow_check && ovf == -ERANGE)
453 pr_err("module %s: overflow in relocation type %d val %Lx\n",
454 me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);