4 * Copyright (C) 2012 ARM Limited
5 * Author: Will Deacon <will.deacon@arm.com>
7 * This code is based heavily on the ARMv7 perf event code.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #define pr_fmt(fmt) "hw perfevents: " fmt
23 #include <linux/bitmap.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/export.h>
29 #include <linux/perf_event.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33 #include <linux/uaccess.h>
35 #include <asm/cputype.h>
37 #include <asm/irq_regs.h>
39 #include <asm/stacktrace.h>
42 * ARMv8 supports a maximum of 32 events.
43 * The cycle counter is included in this total.
45 #define ARMPMU_MAX_HWEVENTS 32
47 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
48 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
49 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
51 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
53 /* Set at runtime when we know what CPU type we are. */
54 static struct arm_pmu *cpu_pmu;
57 armpmu_get_max_events(void)
62 max_events = cpu_pmu->num_events;
66 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
68 int perf_num_counters(void)
70 return armpmu_get_max_events();
72 EXPORT_SYMBOL_GPL(perf_num_counters);
74 #define HW_OP_UNSUPPORTED 0xFFFF
77 PERF_COUNT_HW_CACHE_##_x
79 #define CACHE_OP_UNSUPPORTED 0xFFFF
82 armpmu_map_cache_event(const unsigned (*cache_map)
83 [PERF_COUNT_HW_CACHE_MAX]
84 [PERF_COUNT_HW_CACHE_OP_MAX]
85 [PERF_COUNT_HW_CACHE_RESULT_MAX],
88 unsigned int cache_type, cache_op, cache_result, ret;
90 cache_type = (config >> 0) & 0xff;
91 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
94 cache_op = (config >> 8) & 0xff;
95 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
98 cache_result = (config >> 16) & 0xff;
99 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
102 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
104 if (ret == CACHE_OP_UNSUPPORTED)
111 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
115 if (config >= PERF_COUNT_HW_MAX)
118 mapping = (*event_map)[config];
119 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
123 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
125 return (int)(config & raw_event_mask);
128 static int map_cpu_event(struct perf_event *event,
129 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
130 const unsigned (*cache_map)
131 [PERF_COUNT_HW_CACHE_MAX]
132 [PERF_COUNT_HW_CACHE_OP_MAX]
133 [PERF_COUNT_HW_CACHE_RESULT_MAX],
136 u64 config = event->attr.config;
138 switch (event->attr.type) {
139 case PERF_TYPE_HARDWARE:
140 return armpmu_map_event(event_map, config);
141 case PERF_TYPE_HW_CACHE:
142 return armpmu_map_cache_event(cache_map, config);
144 return armpmu_map_raw_event(raw_event_mask, config);
151 armpmu_event_set_period(struct perf_event *event,
152 struct hw_perf_event *hwc,
155 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
156 s64 left = local64_read(&hwc->period_left);
157 s64 period = hwc->sample_period;
160 if (unlikely(left <= -period)) {
162 local64_set(&hwc->period_left, left);
163 hwc->last_period = period;
167 if (unlikely(left <= 0)) {
169 local64_set(&hwc->period_left, left);
170 hwc->last_period = period;
175 * Limit the maximum period to prevent the counter value
176 * from overtaking the one we are about to program. In
177 * effect we are reducing max_period to account for
178 * interrupt latency (and we are being very conservative).
180 if (left > (armpmu->max_period >> 1))
181 left = armpmu->max_period >> 1;
183 local64_set(&hwc->prev_count, (u64)-left);
185 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
187 perf_event_update_userpage(event);
193 armpmu_event_update(struct perf_event *event,
194 struct hw_perf_event *hwc,
197 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
198 u64 delta, prev_raw_count, new_raw_count;
201 prev_raw_count = local64_read(&hwc->prev_count);
202 new_raw_count = armpmu->read_counter(idx);
204 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
205 new_raw_count) != prev_raw_count)
208 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
210 local64_add(delta, &event->count);
211 local64_sub(delta, &hwc->period_left);
213 return new_raw_count;
217 armpmu_read(struct perf_event *event)
219 struct hw_perf_event *hwc = &event->hw;
221 /* Don't read disabled counters! */
225 armpmu_event_update(event, hwc, hwc->idx);
229 armpmu_stop(struct perf_event *event, int flags)
231 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
232 struct hw_perf_event *hwc = &event->hw;
235 * ARM pmu always has to update the counter, so ignore
236 * PERF_EF_UPDATE, see comments in armpmu_start().
238 if (!(hwc->state & PERF_HES_STOPPED)) {
239 armpmu->disable(hwc, hwc->idx);
240 barrier(); /* why? */
241 armpmu_event_update(event, hwc, hwc->idx);
242 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
247 armpmu_start(struct perf_event *event, int flags)
249 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
250 struct hw_perf_event *hwc = &event->hw;
253 * ARM pmu always has to reprogram the period, so ignore
254 * PERF_EF_RELOAD, see the comment below.
256 if (flags & PERF_EF_RELOAD)
257 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
261 * Set the period again. Some counters can't be stopped, so when we
262 * were stopped we simply disabled the IRQ source and the counter
263 * may have been left counting. If we don't do this step then we may
264 * get an interrupt too soon or *way* too late if the overflow has
265 * happened since disabling.
267 armpmu_event_set_period(event, hwc, hwc->idx);
268 armpmu->enable(hwc, hwc->idx);
272 armpmu_del(struct perf_event *event, int flags)
274 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
275 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
276 struct hw_perf_event *hwc = &event->hw;
281 armpmu_stop(event, PERF_EF_UPDATE);
282 hw_events->events[idx] = NULL;
283 clear_bit(idx, hw_events->used_mask);
285 perf_event_update_userpage(event);
289 armpmu_add(struct perf_event *event, int flags)
291 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
292 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
293 struct hw_perf_event *hwc = &event->hw;
297 perf_pmu_disable(event->pmu);
299 /* If we don't have a space for the counter then finish early. */
300 idx = armpmu->get_event_idx(hw_events, hwc);
307 * If there is an event in the counter we are going to use then make
308 * sure it is disabled.
311 armpmu->disable(hwc, idx);
312 hw_events->events[idx] = event;
314 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
315 if (flags & PERF_EF_START)
316 armpmu_start(event, PERF_EF_RELOAD);
318 /* Propagate our changes to the userspace mapping. */
319 perf_event_update_userpage(event);
322 perf_pmu_enable(event->pmu);
327 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
328 struct perf_event *event)
330 struct arm_pmu *armpmu;
331 struct hw_perf_event fake_event = event->hw;
332 struct pmu *leader_pmu = event->group_leader->pmu;
334 if (is_software_event(event))
338 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
339 * core perf code won't check that the pmu->ctx == leader->ctx
340 * until after pmu->event_init(event).
342 if (event->pmu != pmu)
345 if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
348 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
351 armpmu = to_arm_pmu(event->pmu);
352 return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
356 validate_group(struct perf_event *event)
358 struct perf_event *sibling, *leader = event->group_leader;
359 struct pmu_hw_events fake_pmu;
360 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
363 * Initialise the fake PMU. We only need to populate the
364 * used_mask for the purposes of validation.
366 memset(fake_used_mask, 0, sizeof(fake_used_mask));
367 fake_pmu.used_mask = fake_used_mask;
369 if (!validate_event(event->pmu, &fake_pmu, leader))
372 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
373 if (!validate_event(event->pmu, &fake_pmu, sibling))
377 if (!validate_event(event->pmu, &fake_pmu, event))
384 armpmu_disable_percpu_irq(void *data)
386 unsigned int irq = *(unsigned int *)data;
387 disable_percpu_irq(irq);
391 armpmu_release_hardware(struct arm_pmu *armpmu)
394 unsigned int i, irqs;
395 struct platform_device *pmu_device = armpmu->plat_device;
397 irqs = min(pmu_device->num_resources, num_possible_cpus());
401 irq = platform_get_irq(pmu_device, 0);
405 if (irq_is_percpu(irq)) {
406 on_each_cpu(armpmu_disable_percpu_irq, &irq, 1);
407 free_percpu_irq(irq, &cpu_hw_events);
409 for (i = 0; i < irqs; ++i) {
412 if (armpmu->irq_affinity)
413 cpu = armpmu->irq_affinity[i];
415 if (!cpumask_test_and_clear_cpu(cpu, &armpmu->active_irqs))
417 irq = platform_get_irq(pmu_device, i);
419 free_irq(irq, armpmu);
425 armpmu_enable_percpu_irq(void *data)
427 unsigned int irq = *(unsigned int *)data;
428 enable_percpu_irq(irq, IRQ_TYPE_NONE);
432 armpmu_reserve_hardware(struct arm_pmu *armpmu)
435 unsigned int i, irqs;
436 struct platform_device *pmu_device = armpmu->plat_device;
439 pr_err("no PMU device registered\n");
443 irqs = min(pmu_device->num_resources, num_possible_cpus());
445 pr_err("no irqs for PMUs defined\n");
449 irq = platform_get_irq(pmu_device, 0);
451 pr_err("failed to get valid irq for PMU device\n");
455 if (irq_is_percpu(irq)) {
456 err = request_percpu_irq(irq, armpmu->handle_irq,
457 "arm-pmu", &cpu_hw_events);
460 pr_err("unable to request percpu IRQ%d for ARM PMU counters\n",
462 armpmu_release_hardware(armpmu);
466 on_each_cpu(armpmu_enable_percpu_irq, &irq, 1);
468 for (i = 0; i < irqs; ++i) {
472 irq = platform_get_irq(pmu_device, i);
476 if (armpmu->irq_affinity)
477 cpu = armpmu->irq_affinity[i];
480 * If we have a single PMU interrupt that we can't shift,
481 * assume that we're running on a uniprocessor machine and
482 * continue. Otherwise, continue without this interrupt.
484 if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
485 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
490 err = request_irq(irq, armpmu->handle_irq,
494 pr_err("unable to request IRQ%d for ARM PMU counters\n",
496 armpmu_release_hardware(armpmu);
500 cpumask_set_cpu(cpu, &armpmu->active_irqs);
508 hw_perf_event_destroy(struct perf_event *event)
510 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
511 atomic_t *active_events = &armpmu->active_events;
512 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
514 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
515 armpmu_release_hardware(armpmu);
516 mutex_unlock(pmu_reserve_mutex);
521 event_requires_mode_exclusion(struct perf_event_attr *attr)
523 return attr->exclude_idle || attr->exclude_user ||
524 attr->exclude_kernel || attr->exclude_hv;
528 __hw_perf_event_init(struct perf_event *event)
530 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
531 struct hw_perf_event *hwc = &event->hw;
534 mapping = armpmu->map_event(event);
537 pr_debug("event %x:%llx not supported\n", event->attr.type,
543 * We don't assign an index until we actually place the event onto
544 * hardware. Use -1 to signify that we haven't decided where to put it
545 * yet. For SMP systems, each core has it's own PMU so we can't do any
546 * clever allocation or constraints checking at this point.
549 hwc->config_base = 0;
554 * Check whether we need to exclude the counter from certain modes.
556 if ((!armpmu->set_event_filter ||
557 armpmu->set_event_filter(hwc, &event->attr)) &&
558 event_requires_mode_exclusion(&event->attr)) {
559 pr_debug("ARM performance counters do not support mode exclusion\n");
564 * Store the event encoding into the config_base field.
566 hwc->config_base |= (unsigned long)mapping;
568 if (!hwc->sample_period) {
570 * For non-sampling runs, limit the sample_period to half
571 * of the counter width. That way, the new counter value
572 * is far less likely to overtake the previous one unless
573 * you have some serious IRQ latency issues.
575 hwc->sample_period = armpmu->max_period >> 1;
576 hwc->last_period = hwc->sample_period;
577 local64_set(&hwc->period_left, hwc->sample_period);
581 if (event->group_leader != event) {
582 err = validate_group(event);
590 static int armpmu_event_init(struct perf_event *event)
592 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
594 atomic_t *active_events = &armpmu->active_events;
596 if (armpmu->map_event(event) == -ENOENT)
599 event->destroy = hw_perf_event_destroy;
601 if (!atomic_inc_not_zero(active_events)) {
602 mutex_lock(&armpmu->reserve_mutex);
603 if (atomic_read(active_events) == 0)
604 err = armpmu_reserve_hardware(armpmu);
607 atomic_inc(active_events);
608 mutex_unlock(&armpmu->reserve_mutex);
614 err = __hw_perf_event_init(event);
616 hw_perf_event_destroy(event);
621 static void armpmu_enable(struct pmu *pmu)
623 struct arm_pmu *armpmu = to_arm_pmu(pmu);
624 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
625 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
631 static void armpmu_disable(struct pmu *pmu)
633 struct arm_pmu *armpmu = to_arm_pmu(pmu);
637 static void __init armpmu_init(struct arm_pmu *armpmu)
639 atomic_set(&armpmu->active_events, 0);
640 mutex_init(&armpmu->reserve_mutex);
642 armpmu->pmu = (struct pmu) {
643 .pmu_enable = armpmu_enable,
644 .pmu_disable = armpmu_disable,
645 .event_init = armpmu_event_init,
648 .start = armpmu_start,
654 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
657 return perf_pmu_register(&armpmu->pmu, name, type);
661 * ARMv8 PMUv3 Performance Events handling code.
662 * Common event types.
664 enum armv8_pmuv3_perf_types {
665 /* Required events. */
666 ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR = 0x00,
667 ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL = 0x03,
668 ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS = 0x04,
669 ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
670 ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES = 0x11,
671 ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED = 0x12,
673 /* At least one of the following is required. */
674 ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED = 0x08,
675 ARMV8_PMUV3_PERFCTR_OP_SPEC = 0x1B,
677 /* Common architectural events. */
678 ARMV8_PMUV3_PERFCTR_MEM_READ = 0x06,
679 ARMV8_PMUV3_PERFCTR_MEM_WRITE = 0x07,
680 ARMV8_PMUV3_PERFCTR_EXC_TAKEN = 0x09,
681 ARMV8_PMUV3_PERFCTR_EXC_EXECUTED = 0x0A,
682 ARMV8_PMUV3_PERFCTR_CID_WRITE = 0x0B,
683 ARMV8_PMUV3_PERFCTR_PC_WRITE = 0x0C,
684 ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH = 0x0D,
685 ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN = 0x0E,
686 ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
687 ARMV8_PMUV3_PERFCTR_TTBR_WRITE = 0x1C,
689 /* Common microarchitectural events. */
690 ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL = 0x01,
691 ARMV8_PMUV3_PERFCTR_ITLB_REFILL = 0x02,
692 ARMV8_PMUV3_PERFCTR_DTLB_REFILL = 0x05,
693 ARMV8_PMUV3_PERFCTR_MEM_ACCESS = 0x13,
694 ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS = 0x14,
695 ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB = 0x15,
696 ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS = 0x16,
697 ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL = 0x17,
698 ARMV8_PMUV3_PERFCTR_L2_CACHE_WB = 0x18,
699 ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19,
700 ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A,
701 ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D,
704 /* PMUv3 HW events mapping. */
705 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
706 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
707 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
708 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
709 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
710 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = HW_OP_UNSUPPORTED,
711 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
712 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
713 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
714 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
717 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
718 [PERF_COUNT_HW_CACHE_OP_MAX]
719 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
722 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
723 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
726 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
727 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
730 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
731 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
736 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
737 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
740 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
741 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
744 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
745 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
750 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
751 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
754 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
755 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
758 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
759 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
764 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
765 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
768 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
769 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
772 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
773 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
778 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
779 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
782 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
783 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
786 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
787 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
792 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
793 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
796 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
797 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
800 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
801 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
806 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
807 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
810 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
811 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
814 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
815 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
821 * Perf Events' indices
823 #define ARMV8_IDX_CYCLE_COUNTER 0
824 #define ARMV8_IDX_COUNTER0 1
825 #define ARMV8_IDX_COUNTER_LAST (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
827 #define ARMV8_MAX_COUNTERS 32
828 #define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1)
831 * ARMv8 low level PMU access
835 * Perf Event to low level counters mapping
837 #define ARMV8_IDX_TO_COUNTER(x) \
838 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
841 * Per-CPU PMCR: config reg
843 #define ARMV8_PMCR_E (1 << 0) /* Enable all counters */
844 #define ARMV8_PMCR_P (1 << 1) /* Reset all counters */
845 #define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */
846 #define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
847 #define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
848 #define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
849 #define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */
850 #define ARMV8_PMCR_N_MASK 0x1f
851 #define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
854 * PMOVSR: counters overflow flag status reg
856 #define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */
857 #define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK
860 * PMXEVTYPER: Event selection reg
862 #define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */
863 #define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */
866 * Event filters for PMUv3
868 #define ARMV8_EXCLUDE_EL1 (1 << 31)
869 #define ARMV8_EXCLUDE_EL0 (1 << 30)
870 #define ARMV8_INCLUDE_EL2 (1 << 27)
872 static inline u32 armv8pmu_pmcr_read(void)
875 asm volatile("mrs %0, pmcr_el0" : "=r" (val));
879 static inline void armv8pmu_pmcr_write(u32 val)
881 val &= ARMV8_PMCR_MASK;
883 asm volatile("msr pmcr_el0, %0" :: "r" (val));
886 static inline int armv8pmu_has_overflowed(u32 pmovsr)
888 return pmovsr & ARMV8_OVERFLOWED_MASK;
891 static inline int armv8pmu_counter_valid(int idx)
893 return idx >= ARMV8_IDX_CYCLE_COUNTER && idx <= ARMV8_IDX_COUNTER_LAST;
896 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
901 if (!armv8pmu_counter_valid(idx)) {
902 pr_err("CPU%u checking wrong counter %d overflow status\n",
903 smp_processor_id(), idx);
905 counter = ARMV8_IDX_TO_COUNTER(idx);
906 ret = pmnc & BIT(counter);
912 static inline int armv8pmu_select_counter(int idx)
916 if (!armv8pmu_counter_valid(idx)) {
917 pr_err("CPU%u selecting wrong PMNC counter %d\n",
918 smp_processor_id(), idx);
922 counter = ARMV8_IDX_TO_COUNTER(idx);
923 asm volatile("msr pmselr_el0, %0" :: "r" (counter));
929 static inline u32 armv8pmu_read_counter(int idx)
933 if (!armv8pmu_counter_valid(idx))
934 pr_err("CPU%u reading wrong counter %d\n",
935 smp_processor_id(), idx);
936 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
937 asm volatile("mrs %0, pmccntr_el0" : "=r" (value));
938 else if (armv8pmu_select_counter(idx) == idx)
939 asm volatile("mrs %0, pmxevcntr_el0" : "=r" (value));
944 static inline void armv8pmu_write_counter(int idx, u32 value)
946 if (!armv8pmu_counter_valid(idx))
947 pr_err("CPU%u writing wrong counter %d\n",
948 smp_processor_id(), idx);
949 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
950 asm volatile("msr pmccntr_el0, %0" :: "r" (value));
951 else if (armv8pmu_select_counter(idx) == idx)
952 asm volatile("msr pmxevcntr_el0, %0" :: "r" (value));
955 static inline void armv8pmu_write_evtype(int idx, u32 val)
957 if (armv8pmu_select_counter(idx) == idx) {
958 val &= ARMV8_EVTYPE_MASK;
959 asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
963 static inline int armv8pmu_enable_counter(int idx)
967 if (!armv8pmu_counter_valid(idx)) {
968 pr_err("CPU%u enabling wrong PMNC counter %d\n",
969 smp_processor_id(), idx);
973 counter = ARMV8_IDX_TO_COUNTER(idx);
974 asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter)));
978 static inline int armv8pmu_disable_counter(int idx)
982 if (!armv8pmu_counter_valid(idx)) {
983 pr_err("CPU%u disabling wrong PMNC counter %d\n",
984 smp_processor_id(), idx);
988 counter = ARMV8_IDX_TO_COUNTER(idx);
989 asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter)));
993 static inline int armv8pmu_enable_intens(int idx)
997 if (!armv8pmu_counter_valid(idx)) {
998 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
999 smp_processor_id(), idx);
1003 counter = ARMV8_IDX_TO_COUNTER(idx);
1004 asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter)));
1008 static inline int armv8pmu_disable_intens(int idx)
1012 if (!armv8pmu_counter_valid(idx)) {
1013 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
1014 smp_processor_id(), idx);
1018 counter = ARMV8_IDX_TO_COUNTER(idx);
1019 asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter)));
1021 /* Clear the overflow flag in case an interrupt is pending. */
1022 asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter)));
1027 static inline u32 armv8pmu_getreset_flags(void)
1032 asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
1034 /* Write to clear flags */
1035 value &= ARMV8_OVSR_MASK;
1036 asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
1041 static void armv8pmu_enable_event(struct hw_perf_event *hwc, int idx)
1043 unsigned long flags;
1044 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1047 * Enable counter and interrupt, and set the counter to count
1048 * the event that we're interested in.
1050 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1055 armv8pmu_disable_counter(idx);
1058 * Set event (if destined for PMNx counters).
1060 armv8pmu_write_evtype(idx, hwc->config_base);
1063 * Enable interrupt for this counter
1065 armv8pmu_enable_intens(idx);
1070 armv8pmu_enable_counter(idx);
1072 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1075 static void armv8pmu_disable_event(struct hw_perf_event *hwc, int idx)
1077 unsigned long flags;
1078 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1081 * Disable counter and interrupt
1083 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1088 armv8pmu_disable_counter(idx);
1091 * Disable interrupt for this counter
1093 armv8pmu_disable_intens(idx);
1095 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1098 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
1101 struct perf_sample_data data;
1102 struct pmu_hw_events *cpuc;
1103 struct pt_regs *regs;
1107 * Get and reset the IRQ flags
1109 pmovsr = armv8pmu_getreset_flags();
1112 * Did an overflow occur?
1114 if (!armv8pmu_has_overflowed(pmovsr))
1118 * Handle the counter(s) overflow(s)
1120 regs = get_irq_regs();
1122 cpuc = this_cpu_ptr(&cpu_hw_events);
1123 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
1124 struct perf_event *event = cpuc->events[idx];
1125 struct hw_perf_event *hwc;
1127 /* Ignore if we don't have an event. */
1132 * We have a single interrupt for all counters. Check that
1133 * each counter has overflowed before we process it.
1135 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
1139 armpmu_event_update(event, hwc, idx);
1140 perf_sample_data_init(&data, 0, hwc->last_period);
1141 if (!armpmu_event_set_period(event, hwc, idx))
1144 if (perf_event_overflow(event, &data, regs))
1145 cpu_pmu->disable(hwc, idx);
1149 * Handle the pending perf events.
1151 * Note: this call *must* be run with interrupts disabled. For
1152 * platforms that can have the PMU interrupts raised as an NMI, this
1160 static void armv8pmu_start(void)
1162 unsigned long flags;
1163 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1165 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1166 /* Enable all counters */
1167 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
1168 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1171 static void armv8pmu_stop(void)
1173 unsigned long flags;
1174 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1176 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1177 /* Disable all counters */
1178 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
1179 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1182 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
1183 struct hw_perf_event *event)
1186 unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT;
1188 /* Always place a cycle counter into the cycle counter. */
1189 if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
1190 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
1193 return ARMV8_IDX_CYCLE_COUNTER;
1197 * For anything other than a cycle counter, try and use
1198 * the events counters
1200 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
1201 if (!test_and_set_bit(idx, cpuc->used_mask))
1205 /* The counters are all in use. */
1210 * Add an event filter to a given event. This will only work for PMUv2 PMUs.
1212 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
1213 struct perf_event_attr *attr)
1215 unsigned long config_base = 0;
1217 if (attr->exclude_idle)
1219 if (attr->exclude_user)
1220 config_base |= ARMV8_EXCLUDE_EL0;
1221 if (attr->exclude_kernel)
1222 config_base |= ARMV8_EXCLUDE_EL1;
1223 if (!attr->exclude_hv)
1224 config_base |= ARMV8_INCLUDE_EL2;
1227 * Install the filter into config_base as this is used to
1228 * construct the event type.
1230 event->config_base = config_base;
1235 static void armv8pmu_reset(void *info)
1237 u32 idx, nb_cnt = cpu_pmu->num_events;
1239 /* The counter and interrupt enable registers are unknown at reset. */
1240 for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
1241 armv8pmu_disable_event(NULL, idx);
1243 /* Initialize & Reset PMNC: C and P bits. */
1244 armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
1246 /* Disable access from userspace. */
1247 asm volatile("msr pmuserenr_el0, %0" :: "r" (0));
1250 static int armv8_pmuv3_map_event(struct perf_event *event)
1252 return map_cpu_event(event, &armv8_pmuv3_perf_map,
1253 &armv8_pmuv3_perf_cache_map,
1254 ARMV8_EVTYPE_EVENT);
1257 static struct arm_pmu armv8pmu = {
1258 .handle_irq = armv8pmu_handle_irq,
1259 .enable = armv8pmu_enable_event,
1260 .disable = armv8pmu_disable_event,
1261 .read_counter = armv8pmu_read_counter,
1262 .write_counter = armv8pmu_write_counter,
1263 .get_event_idx = armv8pmu_get_event_idx,
1264 .start = armv8pmu_start,
1265 .stop = armv8pmu_stop,
1266 .reset = armv8pmu_reset,
1267 .max_period = (1LLU << 32) - 1,
1270 static u32 __init armv8pmu_read_num_pmnc_events(void)
1274 /* Read the nb of CNTx counters supported from PMNC */
1275 nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
1277 /* Add the CPU cycles counter and return */
1281 static struct arm_pmu *__init armv8_pmuv3_pmu_init(void)
1283 armv8pmu.name = "arm/armv8-pmuv3";
1284 armv8pmu.map_event = armv8_pmuv3_map_event;
1285 armv8pmu.num_events = armv8pmu_read_num_pmnc_events();
1286 armv8pmu.set_event_filter = armv8pmu_set_event_filter;
1291 * Ensure the PMU has sane values out of reset.
1292 * This requires SMP to be available, so exists as a separate initcall.
1297 if (cpu_pmu && cpu_pmu->reset)
1298 return on_each_cpu(cpu_pmu->reset, NULL, 1);
1301 arch_initcall(cpu_pmu_reset);
1304 * PMU platform driver and devicetree bindings.
1306 static const struct of_device_id armpmu_of_device_ids[] = {
1307 {.compatible = "arm,armv8-pmuv3"},
1311 static int armpmu_device_probe(struct platform_device *pdev)
1318 irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
1322 for (i = 0; i < pdev->num_resources; ++i) {
1323 struct device_node *dn;
1326 dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity",
1329 pr_warn("Failed to parse %s/interrupt-affinity[%d]\n",
1330 of_node_full_name(dn), i);
1334 for_each_possible_cpu(cpu)
1335 if (arch_find_n_match_cpu_physical_id(dn, cpu, NULL))
1339 if (cpu >= nr_cpu_ids) {
1340 pr_warn("Failed to find logical CPU for %s\n",
1348 if (i == pdev->num_resources)
1349 cpu_pmu->irq_affinity = irqs;
1353 cpu_pmu->plat_device = pdev;
1357 static struct platform_driver armpmu_driver = {
1360 .of_match_table = armpmu_of_device_ids,
1362 .probe = armpmu_device_probe,
1365 static int __init register_pmu_driver(void)
1367 return platform_driver_register(&armpmu_driver);
1369 device_initcall(register_pmu_driver);
1371 static struct pmu_hw_events *armpmu_get_cpu_events(void)
1373 return this_cpu_ptr(&cpu_hw_events);
1376 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
1379 for_each_possible_cpu(cpu) {
1380 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
1381 events->events = per_cpu(hw_events, cpu);
1382 events->used_mask = per_cpu(used_mask, cpu);
1383 raw_spin_lock_init(&events->pmu_lock);
1385 armpmu->get_hw_events = armpmu_get_cpu_events;
1388 static int __init init_hw_perf_events(void)
1390 u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
1392 switch ((dfr >> 8) & 0xf) {
1393 case 0x1: /* PMUv3 */
1394 cpu_pmu = armv8_pmuv3_pmu_init();
1399 pr_info("enabled with %s PMU driver, %d counters available\n",
1400 cpu_pmu->name, cpu_pmu->num_events);
1401 cpu_pmu_init(cpu_pmu);
1402 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
1404 pr_info("no hardware support available\n");
1409 early_initcall(init_hw_perf_events);
1412 * Callchain handling code.
1415 struct frame_tail __user *fp;
1417 } __attribute__((packed));
1420 * Get the return address for a single stackframe and return a pointer to the
1423 static struct frame_tail __user *
1424 user_backtrace(struct frame_tail __user *tail,
1425 struct perf_callchain_entry *entry)
1427 struct frame_tail buftail;
1430 /* Also check accessibility of one struct frame_tail beyond */
1431 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
1434 pagefault_disable();
1435 err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
1441 perf_callchain_store(entry, buftail.lr);
1444 * Frame pointers should strictly progress back up the stack
1445 * (towards higher addresses).
1447 if (tail >= buftail.fp)
1453 #ifdef CONFIG_COMPAT
1455 * The registers we're interested in are at the end of the variable
1456 * length saved register structure. The fp points at the end of this
1457 * structure so the address of this struct is:
1458 * (struct compat_frame_tail *)(xxx->fp)-1
1460 * This code has been adapted from the ARM OProfile support.
1462 struct compat_frame_tail {
1463 compat_uptr_t fp; /* a (struct compat_frame_tail *) in compat mode */
1466 } __attribute__((packed));
1468 static struct compat_frame_tail __user *
1469 compat_user_backtrace(struct compat_frame_tail __user *tail,
1470 struct perf_callchain_entry *entry)
1472 struct compat_frame_tail buftail;
1475 /* Also check accessibility of one struct frame_tail beyond */
1476 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
1479 pagefault_disable();
1480 err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
1486 perf_callchain_store(entry, buftail.lr);
1489 * Frame pointers should strictly progress back up the stack
1490 * (towards higher addresses).
1492 if (tail + 1 >= (struct compat_frame_tail __user *)
1493 compat_ptr(buftail.fp))
1496 return (struct compat_frame_tail __user *)compat_ptr(buftail.fp) - 1;
1498 #endif /* CONFIG_COMPAT */
1500 void perf_callchain_user(struct perf_callchain_entry *entry,
1501 struct pt_regs *regs)
1503 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1504 /* We don't support guest os callchain now */
1508 perf_callchain_store(entry, regs->pc);
1510 if (!compat_user_mode(regs)) {
1512 struct frame_tail __user *tail;
1514 tail = (struct frame_tail __user *)regs->regs[29];
1516 while (entry->nr < PERF_MAX_STACK_DEPTH &&
1517 tail && !((unsigned long)tail & 0xf))
1518 tail = user_backtrace(tail, entry);
1520 #ifdef CONFIG_COMPAT
1521 /* AARCH32 compat mode */
1522 struct compat_frame_tail __user *tail;
1524 tail = (struct compat_frame_tail __user *)regs->compat_fp - 1;
1526 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
1527 tail && !((unsigned long)tail & 0x3))
1528 tail = compat_user_backtrace(tail, entry);
1534 * Gets called by walk_stackframe() for every stackframe. This will be called
1535 * whist unwinding the stackframe and is like a subroutine return so we use
1538 static int callchain_trace(struct stackframe *frame, void *data)
1540 struct perf_callchain_entry *entry = data;
1541 perf_callchain_store(entry, frame->pc);
1545 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1546 struct pt_regs *regs)
1548 struct stackframe frame;
1550 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1551 /* We don't support guest os callchain now */
1555 frame.fp = regs->regs[29];
1556 frame.sp = regs->sp;
1557 frame.pc = regs->pc;
1559 walk_stackframe(&frame, callchain_trace, entry);
1562 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1564 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1565 return perf_guest_cbs->get_guest_ip();
1567 return instruction_pointer(regs);
1570 unsigned long perf_misc_flags(struct pt_regs *regs)
1574 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1575 if (perf_guest_cbs->is_user_mode())
1576 misc |= PERF_RECORD_MISC_GUEST_USER;
1578 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1580 if (user_mode(regs))
1581 misc |= PERF_RECORD_MISC_USER;
1583 misc |= PERF_RECORD_MISC_KERNEL;