2 * Based on arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/export.h>
21 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/ioport.h>
24 #include <linux/delay.h>
25 #include <linux/utsname.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/cache.h>
29 #include <linux/bootmem.h>
30 #include <linux/seq_file.h>
31 #include <linux/screen_info.h>
32 #include <linux/init.h>
33 #include <linux/kexec.h>
34 #include <linux/crash_dump.h>
35 #include <linux/root_dev.h>
36 #include <linux/clk-provider.h>
37 #include <linux/cpu.h>
38 #include <linux/interrupt.h>
39 #include <linux/smp.h>
41 #include <linux/proc_fs.h>
42 #include <linux/memblock.h>
43 #include <linux/of_fdt.h>
44 #include <linux/of_platform.h>
45 #include <linux/efi.h>
46 #include <linux/personality.h>
48 #include <asm/fixmap.h>
50 #include <asm/cputype.h>
52 #include <asm/cputable.h>
53 #include <asm/cpufeature.h>
54 #include <asm/cpu_ops.h>
55 #include <asm/sections.h>
56 #include <asm/setup.h>
57 #include <asm/smp_plat.h>
58 #include <asm/cacheflush.h>
59 #include <asm/tlbflush.h>
60 #include <asm/traps.h>
61 #include <asm/memblock.h>
65 unsigned int processor_id;
66 EXPORT_SYMBOL(processor_id);
68 unsigned long elf_hwcap __read_mostly;
69 EXPORT_SYMBOL_GPL(elf_hwcap);
72 #define COMPAT_ELF_HWCAP_DEFAULT \
73 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
74 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
75 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
76 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
77 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
79 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
80 unsigned int compat_elf_hwcap2 __read_mostly;
83 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
85 static const char *cpu_name;
86 phys_addr_t __fdt_pointer __initdata;
89 * Standard memory resources
91 static struct resource mem_res[] = {
93 .name = "Kernel code",
96 .flags = IORESOURCE_MEM
99 .name = "Kernel data",
102 .flags = IORESOURCE_MEM
106 #define kernel_code mem_res[0]
107 #define kernel_data mem_res[1]
109 void __init early_print(const char *str, ...)
115 vsnprintf(buf, sizeof(buf), str, ap);
121 void __init smp_setup_processor_id(void)
123 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
124 cpu_logical_map(0) = mpidr;
127 * clear __my_cpu_offset on boot CPU to avoid hang caused by
128 * using percpu variable early, for example, lockdep will
129 * access percpu variable inside lock_release
131 set_my_cpu_offset(0);
132 pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
135 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
137 return phys_id == cpu_logical_map(cpu);
140 struct mpidr_hash mpidr_hash;
143 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
144 * level in order to build a linear index from an
145 * MPIDR value. Resulting algorithm is a collision
146 * free hash carried out through shifting and ORing
148 static void __init smp_build_mpidr_hash(void)
150 u32 i, affinity, fs[4], bits[4], ls;
153 * Pre-scan the list of MPIDRS and filter out bits that do
154 * not contribute to affinity levels, ie they never toggle.
156 for_each_possible_cpu(i)
157 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
158 pr_debug("mask of set bits %#llx\n", mask);
160 * Find and stash the last and first bit set at all affinity levels to
161 * check how many bits are required to represent them.
163 for (i = 0; i < 4; i++) {
164 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
166 * Find the MSB bit and LSB bits position
167 * to determine how many bits are required
168 * to express the affinity level.
171 fs[i] = affinity ? ffs(affinity) - 1 : 0;
172 bits[i] = ls - fs[i];
175 * An index can be created from the MPIDR_EL1 by isolating the
176 * significant bits at each affinity level and by shifting
177 * them in order to compress the 32 bits values space to a
178 * compressed set of values. This is equivalent to hashing
179 * the MPIDR_EL1 through shifting and ORing. It is a collision free
180 * hash though not minimal since some levels might contain a number
181 * of CPUs that is not an exact power of 2 and their bit
182 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
184 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
185 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
186 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
188 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
189 fs[3] - (bits[2] + bits[1] + bits[0]);
190 mpidr_hash.mask = mask;
191 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
192 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
193 mpidr_hash.shift_aff[0],
194 mpidr_hash.shift_aff[1],
195 mpidr_hash.shift_aff[2],
196 mpidr_hash.shift_aff[3],
200 * 4x is an arbitrary value used to warn on a hash table much bigger
201 * than expected on most systems.
203 if (mpidr_hash_size() > 4 * num_possible_cpus())
204 pr_warn("Large number of MPIDR hash buckets detected\n");
205 __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
209 static void __init setup_processor(void)
211 struct cpu_info *cpu_info;
216 cpu_info = lookup_processor_type(read_cpuid_id());
218 printk("CPU configuration botched (ID %08x), unable to continue.\n",
223 cpu_name = cpu_info->cpu_name;
225 printk("CPU: %s [%08x] revision %d\n",
226 cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
228 sprintf(init_utsname()->machine, ELF_PLATFORM);
231 cpuinfo_store_boot_cpu();
234 * Check for sane CTR_EL0.CWG value.
236 cwg = cache_type_cwg();
237 cls = cache_line_size();
239 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
241 if (L1_CACHE_BYTES < cls)
242 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
243 L1_CACHE_BYTES, cls);
246 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
247 * The blocks we test below represent incremental functionality
248 * for non-negative values. Negative values are reserved.
250 features = read_cpuid(ID_AA64ISAR0_EL1);
251 block = (features >> 4) & 0xf;
252 if (!(block & 0x8)) {
256 elf_hwcap |= HWCAP_PMULL;
258 elf_hwcap |= HWCAP_AES;
264 block = (features >> 8) & 0xf;
265 if (block && !(block & 0x8))
266 elf_hwcap |= HWCAP_SHA1;
268 block = (features >> 12) & 0xf;
269 if (block && !(block & 0x8))
270 elf_hwcap |= HWCAP_SHA2;
272 block = (features >> 16) & 0xf;
273 if (block && !(block & 0x8))
274 elf_hwcap |= HWCAP_CRC32;
278 * ID_ISAR5_EL1 carries similar information as above, but pertaining to
279 * the Aarch32 32-bit execution state.
281 features = read_cpuid(ID_ISAR5_EL1);
282 block = (features >> 4) & 0xf;
283 if (!(block & 0x8)) {
287 compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
289 compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
295 block = (features >> 8) & 0xf;
296 if (block && !(block & 0x8))
297 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
299 block = (features >> 12) & 0xf;
300 if (block && !(block & 0x8))
301 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
303 block = (features >> 16) & 0xf;
304 if (block && !(block & 0x8))
305 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
309 static void __init setup_machine_fdt(phys_addr_t dt_phys)
311 if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
313 "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
314 "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
315 "\nPlease check your bootloader.\n",
316 dt_phys, phys_to_virt(dt_phys));
322 dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
326 * Limit the memory size that was specified via FDT.
328 static int __init early_mem(char *p)
335 limit = memparse(p, &p) & PAGE_MASK;
336 pr_notice("Memory limited to %lldMB\n", limit >> 20);
338 memblock_enforce_memory_limit(limit);
342 early_param("mem", early_mem);
344 static void __init request_standard_resources(void)
346 struct memblock_region *region;
347 struct resource *res;
349 kernel_code.start = virt_to_phys(_text);
350 kernel_code.end = virt_to_phys(_etext - 1);
351 kernel_data.start = virt_to_phys(_sdata);
352 kernel_data.end = virt_to_phys(_end - 1);
354 for_each_memblock(memory, region) {
355 res = alloc_bootmem_low(sizeof(*res));
356 res->name = "System RAM";
357 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
358 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
359 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
361 request_resource(&iomem_resource, res);
363 if (kernel_code.start >= res->start &&
364 kernel_code.end <= res->end)
365 request_resource(res, &kernel_code);
366 if (kernel_data.start >= res->start &&
367 kernel_data.end <= res->end)
368 request_resource(res, &kernel_data);
372 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
374 void __init setup_arch(char **cmdline_p)
378 setup_machine_fdt(__fdt_pointer);
380 init_mm.start_code = (unsigned long) _text;
381 init_mm.end_code = (unsigned long) _etext;
382 init_mm.end_data = (unsigned long) _edata;
383 init_mm.brk = (unsigned long) _end;
385 *cmdline_p = boot_command_line;
388 early_ioremap_init();
393 * Unmask asynchronous aborts after bringing up possible earlycon.
394 * (Report possible System Errors once we can report this occurred)
396 local_async_enable();
399 arm64_memblock_init();
402 request_standard_resources();
406 unflatten_device_tree();
410 cpu_read_bootcpu_ops();
413 smp_build_mpidr_hash();
417 #if defined(CONFIG_VGA_CONSOLE)
418 conswitchp = &vga_con;
419 #elif defined(CONFIG_DUMMY_CONSOLE)
420 conswitchp = &dummy_con;
425 static int __init arm64_device_init(void)
427 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
430 arch_initcall_sync(arm64_device_init);
432 static int __init topology_init(void)
436 for_each_possible_cpu(i) {
437 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
438 cpu->hotpluggable = 1;
439 register_cpu(cpu, i);
444 subsys_initcall(topology_init);
446 static const char *hwcap_str[] = {
459 static const char *compat_hwcap_str[] = {
484 static const char *compat_hwcap2_str[] = {
492 #endif /* CONFIG_COMPAT */
494 static int c_show(struct seq_file *m, void *v)
498 for_each_online_cpu(i) {
499 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
500 u32 midr = cpuinfo->reg_midr;
503 * glibc reads /proc/cpuinfo to determine the number of
504 * online processors, looking for lines beginning with
505 * "processor". Give glibc what it expects.
508 seq_printf(m, "processor\t: %d\n", i);
512 * Dump out the common processor features in a single line.
513 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
514 * rather than attempting to parse this, but there's a body of
515 * software which does already (at least for 32-bit).
517 seq_puts(m, "Features\t:");
518 if (personality(current->personality) == PER_LINUX32) {
520 for (j = 0; compat_hwcap_str[j]; j++)
521 if (compat_elf_hwcap & (1 << j))
522 seq_printf(m, " %s", compat_hwcap_str[j]);
524 for (j = 0; compat_hwcap2_str[j]; j++)
525 if (compat_elf_hwcap2 & (1 << j))
526 seq_printf(m, " %s", compat_hwcap2_str[j]);
527 #endif /* CONFIG_COMPAT */
529 for (j = 0; hwcap_str[j]; j++)
530 if (elf_hwcap & (1 << j))
531 seq_printf(m, " %s", hwcap_str[j]);
535 seq_printf(m, "CPU implementer\t: 0x%02x\n",
536 MIDR_IMPLEMENTOR(midr));
537 seq_printf(m, "CPU architecture: 8\n");
538 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
539 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
540 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
546 static void *c_start(struct seq_file *m, loff_t *pos)
548 return *pos < 1 ? (void *)1 : NULL;
551 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
557 static void c_stop(struct seq_file *m, void *v)
561 const struct seq_operations cpuinfo_op = {