2 * Copyright (C) 2012-2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/compiler.h>
19 #include <linux/kvm_host.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/kvm_mmu.h>
27 * Non-VHE: Both host and guest must save everything.
29 * VHE: Host must save tpidr*_el[01], actlr_el1, sp0, pc, pstate, and
30 * guest must save everything.
33 static void __hyp_text __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
35 ctxt->sys_regs[ACTLR_EL1] = read_sysreg(actlr_el1);
36 ctxt->sys_regs[TPIDR_EL0] = read_sysreg(tpidr_el0);
37 ctxt->sys_regs[TPIDRRO_EL0] = read_sysreg(tpidrro_el0);
38 ctxt->sys_regs[TPIDR_EL1] = read_sysreg(tpidr_el1);
39 ctxt->gp_regs.regs.sp = read_sysreg(sp_el0);
40 ctxt->gp_regs.regs.pc = read_sysreg_el2(elr);
41 ctxt->gp_regs.regs.pstate = read_sysreg_el2(spsr);
44 static void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
46 ctxt->sys_regs[MPIDR_EL1] = read_sysreg(vmpidr_el2);
47 ctxt->sys_regs[CSSELR_EL1] = read_sysreg(csselr_el1);
48 ctxt->sys_regs[SCTLR_EL1] = read_sysreg_el1(sctlr);
49 ctxt->sys_regs[CPACR_EL1] = read_sysreg_el1(cpacr);
50 ctxt->sys_regs[TTBR0_EL1] = read_sysreg_el1(ttbr0);
51 ctxt->sys_regs[TTBR1_EL1] = read_sysreg_el1(ttbr1);
52 ctxt->sys_regs[TCR_EL1] = read_sysreg_el1(tcr);
53 ctxt->sys_regs[ESR_EL1] = read_sysreg_el1(esr);
54 ctxt->sys_regs[AFSR0_EL1] = read_sysreg_el1(afsr0);
55 ctxt->sys_regs[AFSR1_EL1] = read_sysreg_el1(afsr1);
56 ctxt->sys_regs[FAR_EL1] = read_sysreg_el1(far);
57 ctxt->sys_regs[MAIR_EL1] = read_sysreg_el1(mair);
58 ctxt->sys_regs[VBAR_EL1] = read_sysreg_el1(vbar);
59 ctxt->sys_regs[CONTEXTIDR_EL1] = read_sysreg_el1(contextidr);
60 ctxt->sys_regs[AMAIR_EL1] = read_sysreg_el1(amair);
61 ctxt->sys_regs[CNTKCTL_EL1] = read_sysreg_el1(cntkctl);
62 ctxt->sys_regs[PAR_EL1] = read_sysreg(par_el1);
63 ctxt->sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1);
65 ctxt->gp_regs.sp_el1 = read_sysreg(sp_el1);
66 ctxt->gp_regs.elr_el1 = read_sysreg_el1(elr);
67 ctxt->gp_regs.spsr[KVM_SPSR_EL1]= read_sysreg_el1(spsr);
70 void __hyp_text __sysreg_save_host_state(struct kvm_cpu_context *ctxt)
72 __sysreg_save_state(ctxt);
73 __sysreg_save_common_state(ctxt);
76 void __hyp_text __sysreg_save_guest_state(struct kvm_cpu_context *ctxt)
78 __sysreg_save_state(ctxt);
79 __sysreg_save_common_state(ctxt);
82 static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
84 write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
85 write_sysreg(ctxt->sys_regs[TPIDR_EL0], tpidr_el0);
86 write_sysreg(ctxt->sys_regs[TPIDRRO_EL0], tpidrro_el0);
87 write_sysreg(ctxt->sys_regs[TPIDR_EL1], tpidr_el1);
88 write_sysreg(ctxt->gp_regs.regs.sp, sp_el0);
89 write_sysreg_el2(ctxt->gp_regs.regs.pc, elr);
90 write_sysreg_el2(ctxt->gp_regs.regs.pstate, spsr);
93 static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt)
95 write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2);
96 write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1);
97 write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], sctlr);
98 write_sysreg_el1(ctxt->sys_regs[CPACR_EL1], cpacr);
99 write_sysreg_el1(ctxt->sys_regs[TTBR0_EL1], ttbr0);
100 write_sysreg_el1(ctxt->sys_regs[TTBR1_EL1], ttbr1);
101 write_sysreg_el1(ctxt->sys_regs[TCR_EL1], tcr);
102 write_sysreg_el1(ctxt->sys_regs[ESR_EL1], esr);
103 write_sysreg_el1(ctxt->sys_regs[AFSR0_EL1], afsr0);
104 write_sysreg_el1(ctxt->sys_regs[AFSR1_EL1], afsr1);
105 write_sysreg_el1(ctxt->sys_regs[FAR_EL1], far);
106 write_sysreg_el1(ctxt->sys_regs[MAIR_EL1], mair);
107 write_sysreg_el1(ctxt->sys_regs[VBAR_EL1], vbar);
108 write_sysreg_el1(ctxt->sys_regs[CONTEXTIDR_EL1],contextidr);
109 write_sysreg_el1(ctxt->sys_regs[AMAIR_EL1], amair);
110 write_sysreg_el1(ctxt->sys_regs[CNTKCTL_EL1], cntkctl);
111 write_sysreg(ctxt->sys_regs[PAR_EL1], par_el1);
112 write_sysreg(ctxt->sys_regs[MDSCR_EL1], mdscr_el1);
114 write_sysreg(ctxt->gp_regs.sp_el1, sp_el1);
115 write_sysreg_el1(ctxt->gp_regs.elr_el1, elr);
116 write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],spsr);
119 void __hyp_text __sysreg_restore_host_state(struct kvm_cpu_context *ctxt)
121 __sysreg_restore_state(ctxt);
122 __sysreg_restore_common_state(ctxt);
125 void __hyp_text __sysreg_restore_guest_state(struct kvm_cpu_context *ctxt)
127 __sysreg_restore_state(ctxt);
128 __sysreg_restore_common_state(ctxt);
131 void __hyp_text __sysreg32_save_state(struct kvm_vcpu *vcpu)
135 if (read_sysreg(hcr_el2) & HCR_RW)
138 spsr = vcpu->arch.ctxt.gp_regs.spsr;
139 sysreg = vcpu->arch.ctxt.sys_regs;
141 spsr[KVM_SPSR_ABT] = read_sysreg(spsr_abt);
142 spsr[KVM_SPSR_UND] = read_sysreg(spsr_und);
143 spsr[KVM_SPSR_IRQ] = read_sysreg(spsr_irq);
144 spsr[KVM_SPSR_FIQ] = read_sysreg(spsr_fiq);
146 sysreg[DACR32_EL2] = read_sysreg(dacr32_el2);
147 sysreg[IFSR32_EL2] = read_sysreg(ifsr32_el2);
149 if (__fpsimd_enabled())
150 sysreg[FPEXC32_EL2] = read_sysreg(fpexc32_el2);
152 if (vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY)
153 sysreg[DBGVCR32_EL2] = read_sysreg(dbgvcr32_el2);
156 void __hyp_text __sysreg32_restore_state(struct kvm_vcpu *vcpu)
160 if (read_sysreg(hcr_el2) & HCR_RW)
163 spsr = vcpu->arch.ctxt.gp_regs.spsr;
164 sysreg = vcpu->arch.ctxt.sys_regs;
166 write_sysreg(spsr[KVM_SPSR_ABT], spsr_abt);
167 write_sysreg(spsr[KVM_SPSR_UND], spsr_und);
168 write_sysreg(spsr[KVM_SPSR_IRQ], spsr_irq);
169 write_sysreg(spsr[KVM_SPSR_FIQ], spsr_fiq);
171 write_sysreg(sysreg[DACR32_EL2], dacr32_el2);
172 write_sysreg(sysreg[IFSR32_EL2], ifsr32_el2);
174 if (vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY)
175 write_sysreg(sysreg[DBGVCR32_EL2], dbgvcr32_el2);