2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/linkage.h>
19 #include <linux/irqchip/arm-gic.h>
21 #include <asm/assembler.h>
22 #include <asm/memory.h>
23 #include <asm/asm-offsets.h>
24 #include <asm/fpsimdmacros.h>
26 #include <asm/kvm_asm.h>
27 #include <asm/kvm_arm.h>
28 #include <asm/kvm_mmu.h>
30 #define CPU_GP_REG_OFFSET(x) (CPU_GP_REGS + x)
31 #define CPU_XREG_OFFSET(x) CPU_GP_REG_OFFSET(CPU_USER_PT_REGS + 8*x)
32 #define CPU_SPSR_OFFSET(x) CPU_GP_REG_OFFSET(CPU_SPSR + 8*x)
33 #define CPU_SYSREG_OFFSET(x) (CPU_SYSREGS + 8*x)
36 .pushsection .hyp.text, "ax"
40 .globl __kvm_hyp_code_start
42 .macro save_common_regs
43 // x2: base address for cpu context
46 add x3, x2, #CPU_XREG_OFFSET(19)
48 stp x21, x22, [x3, #16]
49 stp x23, x24, [x3, #32]
50 stp x25, x26, [x3, #48]
51 stp x27, x28, [x3, #64]
52 stp x29, lr, [x3, #80]
55 mrs x20, elr_el2 // EL1 PC
56 mrs x21, spsr_el2 // EL1 pstate
58 stp x19, x20, [x3, #96]
65 str x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
66 str x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
67 str x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
70 .macro restore_common_regs
71 // x2: base address for cpu context
74 ldr x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
75 ldr x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
76 ldr x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
82 add x3, x2, #CPU_XREG_OFFSET(31) // SP_EL0
87 msr elr_el2, x20 // EL1 PC
88 msr spsr_el2, x21 // EL1 pstate
90 add x3, x2, #CPU_XREG_OFFSET(19)
92 ldp x21, x22, [x3, #16]
93 ldp x23, x24, [x3, #32]
94 ldp x25, x26, [x3, #48]
95 ldp x27, x28, [x3, #64]
96 ldp x29, lr, [x3, #80]
103 .macro restore_host_regs
108 // x2: cpu context address
110 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
114 .macro restore_fpsimd
115 // x2: cpu context address
117 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
121 .macro save_guest_regs
122 // x0 is the vcpu address
123 // x1 is the return code, do not corrupt!
124 // x2 is the cpu context
125 // x3 is a tmp register
126 // Guest's x0-x3 are on the stack
128 // Compute base to save registers
129 add x3, x2, #CPU_XREG_OFFSET(4)
131 stp x6, x7, [x3, #16]
132 stp x8, x9, [x3, #32]
133 stp x10, x11, [x3, #48]
134 stp x12, x13, [x3, #64]
135 stp x14, x15, [x3, #80]
136 stp x16, x17, [x3, #96]
142 add x3, x2, #CPU_XREG_OFFSET(0)
144 stp x6, x7, [x3, #16]
149 .macro restore_guest_regs
150 // x0 is the vcpu address.
151 // x2 is the cpu context
152 // x3 is a tmp register
154 // Prepare x0-x3 for later restore
155 add x3, x2, #CPU_XREG_OFFSET(0)
157 ldp x6, x7, [x3, #16]
158 push x4, x5 // Push x0-x3 on the stack
162 ldp x4, x5, [x3, #32]
163 ldp x6, x7, [x3, #48]
164 ldp x8, x9, [x3, #64]
165 ldp x10, x11, [x3, #80]
166 ldp x12, x13, [x3, #96]
167 ldp x14, x15, [x3, #112]
168 ldp x16, x17, [x3, #128]
171 // x19-x29, lr, sp*, elr*, spsr*
174 // Last bits of the 64bit state
178 // Do not touch any register after this!
182 * Macros to perform system register save/restore.
184 * Ordering here is absolutely critical, and must be kept consistent
185 * in {save,restore}_sysregs, {save,restore}_guest_32bit_state,
188 * In other words, don't touch any of these unless you know what
192 // x2: base address for cpu context
195 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
211 mrs x18, contextidr_el1
219 stp x6, x7, [x3, #16]
220 stp x8, x9, [x3, #32]
221 stp x10, x11, [x3, #48]
222 stp x12, x13, [x3, #64]
223 stp x14, x15, [x3, #80]
224 stp x16, x17, [x3, #96]
225 stp x18, x19, [x3, #112]
226 stp x20, x21, [x3, #128]
227 stp x22, x23, [x3, #144]
230 .macro restore_sysregs
231 // x2: base address for cpu context
234 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
237 ldp x6, x7, [x3, #16]
238 ldp x8, x9, [x3, #32]
239 ldp x10, x11, [x3, #48]
240 ldp x12, x13, [x3, #64]
241 ldp x14, x15, [x3, #80]
242 ldp x16, x17, [x3, #96]
243 ldp x18, x19, [x3, #112]
244 ldp x20, x21, [x3, #128]
245 ldp x22, x23, [x3, #144]
261 msr contextidr_el1, x18
269 .macro activate_traps
270 ldr x2, [x0, #VCPU_IRQ_LINES]
271 ldr x1, [x0, #VCPU_HCR_EL2]
275 ldr x2, =(CPTR_EL2_TTA)
278 ldr x2, =(1 << 15) // Trap CP15 Cr=15
282 and x2, x2, #MDCR_EL2_HPMN_MASK
283 orr x2, x2, #(MDCR_EL2_TPM | MDCR_EL2_TPMCR)
287 .macro deactivate_traps
294 and x2, x2, #MDCR_EL2_HPMN_MASK
299 ldr x1, [x0, #VCPU_KVM]
301 ldr x2, [x1, #KVM_VTTBR]
310 * Save the VGIC CPU state into memory
311 * x0: Register pointing to VCPU struct
312 * Do not corrupt x1!!!
314 .macro save_vgic_state
315 /* Get VGIC VCTRL base into x2 */
316 ldr x2, [x0, #VCPU_KVM]
318 ldr x2, [x2, #KVM_VGIC_VCTRL]
320 cbz x2, 2f // disabled
322 /* Compute the address of struct vgic_cpu */
323 add x3, x0, #VCPU_VGIC_CPU
325 /* Save all interesting registers */
326 ldr w4, [x2, #GICH_HCR]
327 ldr w5, [x2, #GICH_VMCR]
328 ldr w6, [x2, #GICH_MISR]
329 ldr w7, [x2, #GICH_EISR0]
330 ldr w8, [x2, #GICH_EISR1]
331 ldr w9, [x2, #GICH_ELRSR0]
332 ldr w10, [x2, #GICH_ELRSR1]
333 ldr w11, [x2, #GICH_APR]
335 str w4, [x3, #VGIC_CPU_HCR]
336 str w5, [x3, #VGIC_CPU_VMCR]
337 str w6, [x3, #VGIC_CPU_MISR]
338 str w7, [x3, #VGIC_CPU_EISR]
339 str w8, [x3, #(VGIC_CPU_EISR + 4)]
340 str w9, [x3, #VGIC_CPU_ELRSR]
341 str w10, [x3, #(VGIC_CPU_ELRSR + 4)]
342 str w11, [x3, #VGIC_CPU_APR]
345 str wzr, [x2, #GICH_HCR]
347 /* Save list registers */
348 add x2, x2, #GICH_LR0
349 ldr w4, [x3, #VGIC_CPU_NR_LR]
350 add x3, x3, #VGIC_CPU_LR
359 * Restore the VGIC CPU state from memory
360 * x0: Register pointing to VCPU struct
362 .macro restore_vgic_state
363 /* Get VGIC VCTRL base into x2 */
364 ldr x2, [x0, #VCPU_KVM]
366 ldr x2, [x2, #KVM_VGIC_VCTRL]
368 cbz x2, 2f // disabled
370 /* Compute the address of struct vgic_cpu */
371 add x3, x0, #VCPU_VGIC_CPU
373 /* We only restore a minimal set of registers */
374 ldr w4, [x3, #VGIC_CPU_HCR]
375 ldr w5, [x3, #VGIC_CPU_VMCR]
376 ldr w6, [x3, #VGIC_CPU_APR]
378 str w4, [x2, #GICH_HCR]
379 str w5, [x2, #GICH_VMCR]
380 str w6, [x2, #GICH_APR]
382 /* Restore list registers */
383 add x2, x2, #GICH_LR0
384 ldr w4, [x3, #VGIC_CPU_NR_LR]
385 add x3, x3, #VGIC_CPU_LR
410 * u64 __kvm_vcpu_run(struct kvm_vcpu *vcpu);
412 * This is the world switch. The first half of the function
413 * deals with entering the guest, and anything from __kvm_vcpu_return
414 * to the end of the function deals with reentering the host.
415 * On the enter path, only x0 (vcpu pointer) must be preserved until
416 * the last moment. On the exit path, x0 (vcpu pointer) and x1 (exception
417 * code) must both be preserved until the epilogue.
418 * In both cases, x2 points to the CPU context we're saving/restoring from/to.
420 ENTRY(__kvm_vcpu_run)
422 msr tpidr_el2, x0 // Save the vcpu register
425 ldr x2, [x0, #VCPU_HOST_CONTEXT]
438 add x2, x0, #VCPU_CONTEXT
444 // That's it, no more messing around.
448 // Assume x0 is the vcpu pointer, x1 the return code
449 // Guest's x0-x3 are on the stack
452 add x2, x0, #VCPU_CONTEXT
464 ldr x2, [x0, #VCPU_HOST_CONTEXT]
475 // void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
476 ENTRY(__kvm_tlb_flush_vmid_ipa)
478 ldr x2, [x0, #KVM_VTTBR]
483 * We could do so much better if we had the VA as well.
484 * Instead, we invalidate Stage-2 for this IPA, and the
485 * whole of Stage-1. Weep...
495 ENDPROC(__kvm_tlb_flush_vmid_ipa)
497 ENTRY(__kvm_flush_vm_context)
502 ENDPROC(__kvm_flush_vm_context)
505 // Guess the context by looking at VTTBR:
506 // If zero, then we're already a host.
507 // Otherwise restore a minimal host context before panicing.
516 ldr x2, [x0, #VCPU_HOST_CONTEXT]
521 1: adr x0, __hyp_panic_str
534 mov lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
542 2: .quad HYP_PAGE_OFFSET
544 ENDPROC(__kvm_hyp_panic)
547 .ascii "HYP panic:\nPS:%08x PC:%p ESR:%p\nFAR:%p HPFAR:%p PAR:%p\nVCPU:%p\n\0"
554 ENDPROC(kvm_call_hyp)
556 .macro invalid_vector label, target
563 /* None of these should ever happen */
564 invalid_vector el2t_sync_invalid, __kvm_hyp_panic
565 invalid_vector el2t_irq_invalid, __kvm_hyp_panic
566 invalid_vector el2t_fiq_invalid, __kvm_hyp_panic
567 invalid_vector el2t_error_invalid, __kvm_hyp_panic
568 invalid_vector el2h_sync_invalid, __kvm_hyp_panic
569 invalid_vector el2h_irq_invalid, __kvm_hyp_panic
570 invalid_vector el2h_fiq_invalid, __kvm_hyp_panic
571 invalid_vector el2h_error_invalid, __kvm_hyp_panic
572 invalid_vector el1_sync_invalid, __kvm_hyp_panic
573 invalid_vector el1_irq_invalid, __kvm_hyp_panic
574 invalid_vector el1_fiq_invalid, __kvm_hyp_panic
575 invalid_vector el1_error_invalid, __kvm_hyp_panic
577 el1_sync: // Guest trapped into EL2
582 lsr x2, x1, #ESR_EL2_EC_SHIFT
584 cmp x2, #ESR_EL2_EC_HVC64
587 mrs x3, vttbr_el2 // If vttbr is valid, the 64bit guest
588 cbnz x3, el1_trap // called HVC
590 /* Here, we're pretty sure the host called HVC. */
597 * Compute the function address in EL2, and shuffle the parameters.
614 cmp x2, #ESR_EL2_EC_DABT
615 mov x0, #ESR_EL2_EC_IABT
617 b.ne 1f // Not an abort we care about
619 /* This is an abort. Check for permission fault */
620 and x2, x1, #ESR_EL2_FSC_TYPE
622 b.ne 1f // Not a permission fault
625 * Check for Stage-1 page table walk, which is guaranteed
626 * to give a valid HPFAR_EL2.
628 tbnz x1, #7, 1f // S1PTW is set
631 * Permission fault, HPFAR_EL2 is invalid.
632 * Resolve the IPA the hard way using the guest VA.
633 * Stage-1 translation already validated the memory access rights.
634 * As such, we can use the EL1 translation regime, and don't have
635 * to distinguish between EL0 and EL1 access.
643 tbnz x3, #0, 3f // Bail out if we failed the translation
644 ubfx x3, x3, #12, #36 // Extract IPA
645 lsl x3, x3, #4 // and present it like HPFAR
652 str x1, [x0, #VCPU_ESR_EL2]
653 str x2, [x0, #VCPU_FAR_EL2]
654 str x3, [x0, #VCPU_HPFAR_EL2]
656 mov x1, #ARM_EXCEPTION_TRAP
660 * Translation failed. Just return to the guest and
661 * let it fault again. Another CPU is probably playing
673 mov x1, #ARM_EXCEPTION_IRQ
680 ENTRY(__kvm_hyp_vector)
681 ventry el2t_sync_invalid // Synchronous EL2t
682 ventry el2t_irq_invalid // IRQ EL2t
683 ventry el2t_fiq_invalid // FIQ EL2t
684 ventry el2t_error_invalid // Error EL2t
686 ventry el2h_sync_invalid // Synchronous EL2h
687 ventry el2h_irq_invalid // IRQ EL2h
688 ventry el2h_fiq_invalid // FIQ EL2h
689 ventry el2h_error_invalid // Error EL2h
691 ventry el1_sync // Synchronous 64-bit EL1
692 ventry el1_irq // IRQ 64-bit EL1
693 ventry el1_fiq_invalid // FIQ 64-bit EL1
694 ventry el1_error_invalid // Error 64-bit EL1
696 ventry el1_sync // Synchronous 32-bit EL1
697 ventry el1_irq // IRQ 32-bit EL1
698 ventry el1_fiq_invalid // FIQ 32-bit EL1
699 ventry el1_error_invalid // Error 32-bit EL1
700 ENDPROC(__kvm_hyp_vector)
703 .globl __kvm_hyp_code_end