arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/bsearch.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/mm.h>
  26 #include <linux/uaccess.h>
  27
  28 #include <asm/cacheflush.h>
  29 #include <asm/cputype.h>
  30 #include <asm/debug-monitors.h>
  31 #include <asm/esr.h>
  32 #include <asm/kvm_arm.h>
  33 #include <asm/kvm_asm.h>
  34 #include <asm/kvm_coproc.h>
  35 #include <asm/kvm_emulate.h>
  36 #include <asm/kvm_host.h>
  37 #include <asm/kvm_mmu.h>
  38 #include <asm/perf_event.h>
  39 #include <asm/sysreg.h>
  40
  41 #include <trace/events/kvm.h>
  42
  43 #include "sys_regs.h"
  44
  45 #include "trace.h"
  46
  47 /*
  48  * All of this file is extremly similar to the ARM coproc.c, but the
  49  * types are different. My gut feeling is that it should be pretty
  50  * easy to merge, but that would be an ABI breakage -- again. VFP
  51  * would also need to be abstracted.
  52  *
  53  * For AArch32, we only take care of what is being trapped. Anything
  54  * that has to do with init and userspace access has to go via the
  55  * 64bit interface.
  56  */
  57
  58 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  59 static u32 cache_levels;
  60
  61 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  62 #define CSSELR_MAX 12
  63
  64 /* Which cache CCSIDR represents depends on CSSELR value. */
  65 static u32 get_ccsidr(u32 csselr)
  66 {
  67         u32 ccsidr;
  68
  69         /* Make sure noone else changes CSSELR during this! */
  70         local_irq_disable();
  71         write_sysreg(csselr, csselr_el1);
  72         isb();
  73         ccsidr = read_sysreg(ccsidr_el1);
  74         local_irq_enable();
  75
  76         return ccsidr;
  77 }
  78
  79 /*
  80  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
  81  */
  82 static bool access_dcsw(struct kvm_vcpu *vcpu,
  83                         struct sys_reg_params *p,
  84                         const struct sys_reg_desc *r)
  85 {
  86         if (!p->is_write)
  87                 return read_from_write_only(vcpu, p);
  88
  89         kvm_set_way_flush(vcpu);
  90         return true;
  91 }
  92
  93 /*
  94  * Generic accessor for VM registers. Only called as long as HCR_TVM
  95  * is set. If the guest enables the MMU, we stop trapping the VM
  96  * sys_regs and leave it in complete control of the caches.
  97  */
  98 static bool access_vm_reg(struct kvm_vcpu *vcpu,
  99                           struct sys_reg_params *p,
 100                           const struct sys_reg_desc *r)
 101 {
 102         bool was_enabled = vcpu_has_cache_enabled(vcpu);
 103
 104         BUG_ON(!p->is_write);
 105
 106         if (!p->is_aarch32) {
 107                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 108         } else {
 109                 if (!p->is_32bit)
 110                         vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
 111                 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
 112         }
 113
 114         kvm_toggle_cache(vcpu, was_enabled);
 115         return true;
 116 }
 117
 118 /*
 119  * Trap handler for the GICv3 SGI generation system register.
 120  * Forward the request to the VGIC emulation.
 121  * The cp15_64 code makes sure this automatically works
 122  * for both AArch64 and AArch32 accesses.
 123  */
 124 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
 125                            struct sys_reg_params *p,
 126                            const struct sys_reg_desc *r)
 127 {
 128         if (!p->is_write)
 129                 return read_from_write_only(vcpu, p);
 130
 131         vgic_v3_dispatch_sgi(vcpu, p->regval);
 132
 133         return true;
 134 }
 135
 136 static bool access_gic_sre(struct kvm_vcpu *vcpu,
 137                            struct sys_reg_params *p,
 138                            const struct sys_reg_desc *r)
 139 {
 140         if (p->is_write)
 141                 return ignore_write(vcpu, p);
 142
 143         p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
 144         return true;
 145 }
 146
 147 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 148                         struct sys_reg_params *p,
 149                         const struct sys_reg_desc *r)
 150 {
 151         if (p->is_write)
 152                 return ignore_write(vcpu, p);
 153         else
 154                 return read_zero(vcpu, p);
 155 }
 156
 157 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 158                            struct sys_reg_params *p,
 159                            const struct sys_reg_desc *r)
 160 {
 161         if (p->is_write) {
 162                 return ignore_write(vcpu, p);
 163         } else {
 164                 p->regval = (1 << 3);
 165                 return true;
 166         }
 167 }
 168
 169 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 170                                    struct sys_reg_params *p,
 171                                    const struct sys_reg_desc *r)
 172 {
 173         if (p->is_write) {
 174                 return ignore_write(vcpu, p);
 175         } else {
 176                 p->regval = read_sysreg(dbgauthstatus_el1);
 177                 return true;
 178         }
 179 }
 180
 181 /*
 182  * We want to avoid world-switching all the DBG registers all the
 183  * time:
 184  *
 185  * - If we've touched any debug register, it is likely that we're
 186  *   going to touch more of them. It then makes sense to disable the
 187  *   traps and start doing the save/restore dance
 188  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 189  *   then mandatory to save/restore the registers, as the guest
 190  *   depends on them.
 191  *
 192  * For this, we use a DIRTY bit, indicating the guest has modified the
 193  * debug registers, used as follow:
 194  *
 195  * On guest entry:
 196  * - If the dirty bit is set (because we're coming back from trapping),
 197  *   disable the traps, save host registers, restore guest registers.
 198  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 199  *   set the dirty bit, disable the traps, save host registers,
 200  *   restore guest registers.
 201  * - Otherwise, enable the traps
 202  *
 203  * On guest exit:
 204  * - If the dirty bit is set, save guest registers, restore host
 205  *   registers and clear the dirty bit. This ensure that the host can
 206  *   now use the debug registers.
 207  */
 208 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 209                             struct sys_reg_params *p,
 210                             const struct sys_reg_desc *r)
 211 {
 212         if (p->is_write) {
 213                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 214                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 215         } else {
 216                 p->regval = vcpu_sys_reg(vcpu, r->reg);
 217         }
 218
 219         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
 220
 221         return true;
 222 }
 223
 224 /*
 225  * reg_to_dbg/dbg_to_reg
 226  *
 227  * A 32 bit write to a debug register leave top bits alone
 228  * A 32 bit read from a debug register only returns the bottom bits
 229  *
 230  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
 231  * hyp.S code switches between host and guest values in future.
 232  */
 233 static void reg_to_dbg(struct kvm_vcpu *vcpu,
 234                        struct sys_reg_params *p,
 235                        u64 *dbg_reg)
 236 {
 237         u64 val = p->regval;
 238
 239         if (p->is_32bit) {
 240                 val &= 0xffffffffUL;
 241                 val |= ((*dbg_reg >> 32) << 32);
 242         }
 243
 244         *dbg_reg = val;
 245         vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 246 }
 247
 248 static void dbg_to_reg(struct kvm_vcpu *vcpu,
 249                        struct sys_reg_params *p,
 250                        u64 *dbg_reg)
 251 {
 252         p->regval = *dbg_reg;
 253         if (p->is_32bit)
 254                 p->regval &= 0xffffffffUL;
 255 }
 256
 257 static bool trap_bvr(struct kvm_vcpu *vcpu,
 258                      struct sys_reg_params *p,
 259                      const struct sys_reg_desc *rd)
 260 {
 261         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 262
 263         if (p->is_write)
 264                 reg_to_dbg(vcpu, p, dbg_reg);
 265         else
 266                 dbg_to_reg(vcpu, p, dbg_reg);
 267
 268         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 269
 270         return true;
 271 }
 272
 273 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 274                 const struct kvm_one_reg *reg, void __user *uaddr)
 275 {
 276         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 277
 278         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 279                 return -EFAULT;
 280         return 0;
 281 }
 282
 283 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 284         const struct kvm_one_reg *reg, void __user *uaddr)
 285 {
 286         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 287
 288         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 289                 return -EFAULT;
 290         return 0;
 291 }
 292
 293 static void reset_bvr(struct kvm_vcpu *vcpu,
 294                       const struct sys_reg_desc *rd)
 295 {
 296         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
 297 }
 298
 299 static bool trap_bcr(struct kvm_vcpu *vcpu,
 300                      struct sys_reg_params *p,
 301                      const struct sys_reg_desc *rd)
 302 {
 303         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 304
 305         if (p->is_write)
 306                 reg_to_dbg(vcpu, p, dbg_reg);
 307         else
 308                 dbg_to_reg(vcpu, p, dbg_reg);
 309
 310         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 311
 312         return true;
 313 }
 314
 315 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 316                 const struct kvm_one_reg *reg, void __user *uaddr)
 317 {
 318         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 319
 320         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 321                 return -EFAULT;
 322
 323         return 0;
 324 }
 325
 326 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 327         const struct kvm_one_reg *reg, void __user *uaddr)
 328 {
 329         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 330
 331         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 332                 return -EFAULT;
 333         return 0;
 334 }
 335
 336 static void reset_bcr(struct kvm_vcpu *vcpu,
 337                       const struct sys_reg_desc *rd)
 338 {
 339         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
 340 }
 341
 342 static bool trap_wvr(struct kvm_vcpu *vcpu,
 343                      struct sys_reg_params *p,
 344                      const struct sys_reg_desc *rd)
 345 {
 346         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 347
 348         if (p->is_write)
 349                 reg_to_dbg(vcpu, p, dbg_reg);
 350         else
 351                 dbg_to_reg(vcpu, p, dbg_reg);
 352
 353         trace_trap_reg(__func__, rd->reg, p->is_write,
 354                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
 355
 356         return true;
 357 }
 358
 359 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 360                 const struct kvm_one_reg *reg, void __user *uaddr)
 361 {
 362         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 363
 364         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 365                 return -EFAULT;
 366         return 0;
 367 }
 368
 369 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 370         const struct kvm_one_reg *reg, void __user *uaddr)
 371 {
 372         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 373
 374         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 375                 return -EFAULT;
 376         return 0;
 377 }
 378
 379 static void reset_wvr(struct kvm_vcpu *vcpu,
 380                       const struct sys_reg_desc *rd)
 381 {
 382         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
 383 }
 384
 385 static bool trap_wcr(struct kvm_vcpu *vcpu,
 386                      struct sys_reg_params *p,
 387                      const struct sys_reg_desc *rd)
 388 {
 389         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 390
 391         if (p->is_write)
 392                 reg_to_dbg(vcpu, p, dbg_reg);
 393         else
 394                 dbg_to_reg(vcpu, p, dbg_reg);
 395
 396         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 397
 398         return true;
 399 }
 400
 401 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 402                 const struct kvm_one_reg *reg, void __user *uaddr)
 403 {
 404         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 405
 406         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 407                 return -EFAULT;
 408         return 0;
 409 }
 410
 411 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 412         const struct kvm_one_reg *reg, void __user *uaddr)
 413 {
 414         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 415
 416         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 417                 return -EFAULT;
 418         return 0;
 419 }
 420
 421 static void reset_wcr(struct kvm_vcpu *vcpu,
 422                       const struct sys_reg_desc *rd)
 423 {
 424         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
 425 }
 426
 427 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 428 {
 429         vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
 430 }
 431
 432 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 433 {
 434         u64 mpidr;
 435
 436         /*
 437          * Map the vcpu_id into the first three affinity level fields of
 438          * the MPIDR. We limit the number of VCPUs in level 0 due to a
 439          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
 440          * of the GICv3 to be able to address each CPU directly when
 441          * sending IPIs.
 442          */
 443         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 444         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 445         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 446         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
 447 }
 448
 449 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 450 {
 451         u64 pmcr, val;
 452
 453         pmcr = read_sysreg(pmcr_el0);
 454         /*
 455          * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
 456          * except PMCR.E resetting to zero.
 457          */
 458         val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
 459                | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
 460         vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 461 }
 462
 463 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
 464 {
 465         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 466
 467         return !((reg & ARMV8_PMU_USERENR_EN) || vcpu_mode_priv(vcpu));
 468 }
 469
 470 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
 471 {
 472         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 473
 474         return !((reg & (ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN))
 475                  || vcpu_mode_priv(vcpu));
 476 }
 477
 478 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
 479 {
 480         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 481
 482         return !((reg & (ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN))
 483                  || vcpu_mode_priv(vcpu));
 484 }
 485
 486 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
 487 {
 488         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 489
 490         return !((reg & (ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN))
 491                  || vcpu_mode_priv(vcpu));
 492 }
 493
 494 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 495                         const struct sys_reg_desc *r)
 496 {
 497         u64 val;
 498
 499         if (!kvm_arm_pmu_v3_ready(vcpu))
 500                 return trap_raz_wi(vcpu, p, r);
 501
 502         if (pmu_access_el0_disabled(vcpu))
 503                 return false;
 504
 505         if (p->is_write) {
 506                 /* Only update writeable bits of PMCR */
 507                 val = vcpu_sys_reg(vcpu, PMCR_EL0);
 508                 val &= ~ARMV8_PMU_PMCR_MASK;
 509                 val |= p->regval & ARMV8_PMU_PMCR_MASK;
 510                 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 511                 kvm_pmu_handle_pmcr(vcpu, val);
 512         } else {
 513                 /* PMCR.P & PMCR.C are RAZ */
 514                 val = vcpu_sys_reg(vcpu, PMCR_EL0)
 515                       & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
 516                 p->regval = val;
 517         }
 518
 519         return true;
 520 }
 521
 522 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 523                           const struct sys_reg_desc *r)
 524 {
 525         if (!kvm_arm_pmu_v3_ready(vcpu))
 526                 return trap_raz_wi(vcpu, p, r);
 527
 528         if (pmu_access_event_counter_el0_disabled(vcpu))
 529                 return false;
 530
 531         if (p->is_write)
 532                 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
 533         else
 534                 /* return PMSELR.SEL field */
 535                 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
 536                             & ARMV8_PMU_COUNTER_MASK;
 537
 538         return true;
 539 }
 540
 541 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 542                           const struct sys_reg_desc *r)
 543 {
 544         u64 pmceid;
 545
 546         if (!kvm_arm_pmu_v3_ready(vcpu))
 547                 return trap_raz_wi(vcpu, p, r);
 548
 549         BUG_ON(p->is_write);
 550
 551         if (pmu_access_el0_disabled(vcpu))
 552                 return false;
 553
 554         if (!(p->Op2 & 1))
 555                 pmceid = read_sysreg(pmceid0_el0);
 556         else
 557                 pmceid = read_sysreg(pmceid1_el0);
 558
 559         p->regval = pmceid;
 560
 561         return true;
 562 }
 563
 564 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
 565 {
 566         u64 pmcr, val;
 567
 568         pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
 569         val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
 570         if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX)
 571                 return false;
 572
 573         return true;
 574 }
 575
 576 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
 577                               struct sys_reg_params *p,
 578                               const struct sys_reg_desc *r)
 579 {
 580         u64 idx;
 581
 582         if (!kvm_arm_pmu_v3_ready(vcpu))
 583                 return trap_raz_wi(vcpu, p, r);
 584
 585         if (r->CRn == 9 && r->CRm == 13) {
 586                 if (r->Op2 == 2) {
 587                         /* PMXEVCNTR_EL0 */
 588                         if (pmu_access_event_counter_el0_disabled(vcpu))
 589                                 return false;
 590
 591                         idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
 592                               & ARMV8_PMU_COUNTER_MASK;
 593                 } else if (r->Op2 == 0) {
 594                         /* PMCCNTR_EL0 */
 595                         if (pmu_access_cycle_counter_el0_disabled(vcpu))
 596                                 return false;
 597
 598                         idx = ARMV8_PMU_CYCLE_IDX;
 599                 } else {
 600                         return false;
 601                 }
 602         } else if (r->CRn == 0 && r->CRm == 9) {
 603                 /* PMCCNTR */
 604                 if (pmu_access_event_counter_el0_disabled(vcpu))
 605                         return false;
 606
 607                 idx = ARMV8_PMU_CYCLE_IDX;
 608         } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
 609                 /* PMEVCNTRn_EL0 */
 610                 if (pmu_access_event_counter_el0_disabled(vcpu))
 611                         return false;
 612
 613                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 614         } else {
 615                 return false;
 616         }
 617
 618         if (!pmu_counter_idx_valid(vcpu, idx))
 619                 return false;
 620
 621         if (p->is_write) {
 622                 if (pmu_access_el0_disabled(vcpu))
 623                         return false;
 624
 625                 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
 626         } else {
 627                 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
 628         }
 629
 630         return true;
 631 }
 632
 633 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 634                                const struct sys_reg_desc *r)
 635 {
 636         u64 idx, reg;
 637
 638         if (!kvm_arm_pmu_v3_ready(vcpu))
 639                 return trap_raz_wi(vcpu, p, r);
 640
 641         if (pmu_access_el0_disabled(vcpu))
 642                 return false;
 643
 644         if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
 645                 /* PMXEVTYPER_EL0 */
 646                 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
 647                 reg = PMEVTYPER0_EL0 + idx;
 648         } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
 649                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 650                 if (idx == ARMV8_PMU_CYCLE_IDX)
 651                         reg = PMCCFILTR_EL0;
 652                 else
 653                         /* PMEVTYPERn_EL0 */
 654                         reg = PMEVTYPER0_EL0 + idx;
 655         } else {
 656                 BUG();
 657         }
 658
 659         if (!pmu_counter_idx_valid(vcpu, idx))
 660                 return false;
 661
 662         if (p->is_write) {
 663                 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
 664                 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
 665         } else {
 666                 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
 667         }
 668
 669         return true;
 670 }
 671
 672 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 673                            const struct sys_reg_desc *r)
 674 {
 675         u64 val, mask;
 676
 677         if (!kvm_arm_pmu_v3_ready(vcpu))
 678                 return trap_raz_wi(vcpu, p, r);
 679
 680         if (pmu_access_el0_disabled(vcpu))
 681                 return false;
 682
 683         mask = kvm_pmu_valid_counter_mask(vcpu);
 684         if (p->is_write) {
 685                 val = p->regval & mask;
 686                 if (r->Op2 & 0x1) {
 687                         /* accessing PMCNTENSET_EL0 */
 688                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
 689                         kvm_pmu_enable_counter(vcpu, val);
 690                 } else {
 691                         /* accessing PMCNTENCLR_EL0 */
 692                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
 693                         kvm_pmu_disable_counter(vcpu, val);
 694                 }
 695         } else {
 696                 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
 697         }
 698
 699         return true;
 700 }
 701
 702 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 703                            const struct sys_reg_desc *r)
 704 {
 705         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 706
 707         if (!kvm_arm_pmu_v3_ready(vcpu))
 708                 return trap_raz_wi(vcpu, p, r);
 709
 710         if (!vcpu_mode_priv(vcpu))
 711                 return false;
 712
 713         if (p->is_write) {
 714                 u64 val = p->regval & mask;
 715
 716                 if (r->Op2 & 0x1)
 717                         /* accessing PMINTENSET_EL1 */
 718                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
 719                 else
 720                         /* accessing PMINTENCLR_EL1 */
 721                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
 722         } else {
 723                 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
 724         }
 725
 726         return true;
 727 }
 728
 729 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 730                          const struct sys_reg_desc *r)
 731 {
 732         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 733
 734         if (!kvm_arm_pmu_v3_ready(vcpu))
 735                 return trap_raz_wi(vcpu, p, r);
 736
 737         if (pmu_access_el0_disabled(vcpu))
 738                 return false;
 739
 740         if (p->is_write) {
 741                 if (r->CRm & 0x2)
 742                         /* accessing PMOVSSET_EL0 */
 743                         kvm_pmu_overflow_set(vcpu, p->regval & mask);
 744                 else
 745                         /* accessing PMOVSCLR_EL0 */
 746                         vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
 747         } else {
 748                 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
 749         }
 750
 751         return true;
 752 }
 753
 754 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 755                            const struct sys_reg_desc *r)
 756 {
 757         u64 mask;
 758
 759         if (!kvm_arm_pmu_v3_ready(vcpu))
 760                 return trap_raz_wi(vcpu, p, r);
 761
 762         if (pmu_write_swinc_el0_disabled(vcpu))
 763                 return false;
 764
 765         if (p->is_write) {
 766                 mask = kvm_pmu_valid_counter_mask(vcpu);
 767                 kvm_pmu_software_increment(vcpu, p->regval & mask);
 768                 return true;
 769         }
 770
 771         return false;
 772 }
 773
 774 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 775                              const struct sys_reg_desc *r)
 776 {
 777         if (!kvm_arm_pmu_v3_ready(vcpu))
 778                 return trap_raz_wi(vcpu, p, r);
 779
 780         if (p->is_write) {
 781                 if (!vcpu_mode_priv(vcpu))
 782                         return false;
 783
 784                 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
 785                                                     & ARMV8_PMU_USERENR_MASK;
 786         } else {
 787                 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
 788                             & ARMV8_PMU_USERENR_MASK;
 789         }
 790
 791         return true;
 792 }
 793
 794 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 795 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 796         { SYS_DESC(SYS_DBGBVRn_EL1(n)),                                 \
 797           trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr },                \
 798         { SYS_DESC(SYS_DBGBCRn_EL1(n)),                                 \
 799           trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr },                \
 800         { SYS_DESC(SYS_DBGWVRn_EL1(n)),                                 \
 801           trap_wvr, reset_wvr, n, 0,  get_wvr, set_wvr },               \
 802         { SYS_DESC(SYS_DBGWCRn_EL1(n)),                                 \
 803           trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
 804
 805 /* Macro to expand the PMEVCNTRn_EL0 register */
 806 #define PMU_PMEVCNTR_EL0(n)                                             \
 807         { SYS_DESC(SYS_PMEVCNTRn_EL0(n)),                                       \
 808           access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
 809
 810 /* Macro to expand the PMEVTYPERn_EL0 register */
 811 #define PMU_PMEVTYPER_EL0(n)                                            \
 812         { SYS_DESC(SYS_PMEVTYPERn_EL0(n)),                                      \
 813           access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
 814
 815 static bool access_cntp_tval(struct kvm_vcpu *vcpu,
 816                 struct sys_reg_params *p,
 817                 const struct sys_reg_desc *r)
 818 {
 819         struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
 820         u64 now = kvm_phys_timer_read();
 821
 822         if (p->is_write)
 823                 ptimer->cnt_cval = p->regval + now;
 824         else
 825                 p->regval = ptimer->cnt_cval - now;
 826
 827         return true;
 828 }
 829
 830 static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
 831                 struct sys_reg_params *p,
 832                 const struct sys_reg_desc *r)
 833 {
 834         struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
 835
 836         if (p->is_write) {
 837                 /* ISTATUS bit is read-only */
 838                 ptimer->cnt_ctl = p->regval & ~ARCH_TIMER_CTRL_IT_STAT;
 839         } else {
 840                 u64 now = kvm_phys_timer_read();
 841
 842                 p->regval = ptimer->cnt_ctl;
 843                 /*
 844                  * Set ISTATUS bit if it's expired.
 845                  * Note that according to ARMv8 ARM Issue A.k, ISTATUS bit is
 846                  * UNKNOWN when ENABLE bit is 0, so we chose to set ISTATUS bit
 847                  * regardless of ENABLE bit for our implementation convenience.
 848                  */
 849                 if (ptimer->cnt_cval <= now)
 850                         p->regval |= ARCH_TIMER_CTRL_IT_STAT;
 851         }
 852
 853         return true;
 854 }
 855
 856 static bool access_cntp_cval(struct kvm_vcpu *vcpu,
 857                 struct sys_reg_params *p,
 858                 const struct sys_reg_desc *r)
 859 {
 860         struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
 861
 862         if (p->is_write)
 863                 ptimer->cnt_cval = p->regval;
 864         else
 865                 p->regval = ptimer->cnt_cval;
 866
 867         return true;
 868 }
 869
 870 /*
 871  * Architected system registers.
 872  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 873  *
 874  * Debug handling: We do trap most, if not all debug related system
 875  * registers. The implementation is good enough to ensure that a guest
 876  * can use these with minimal performance degradation. The drawback is
 877  * that we don't implement any of the external debug, none of the
 878  * OSlock protocol. This should be revisited if we ever encounter a
 879  * more demanding guest...
 880  */
 881 static const struct sys_reg_desc sys_reg_descs[] = {
 882         /* DC ISW */
 883         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
 884           access_dcsw },
 885         /* DC CSW */
 886         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
 887           access_dcsw },
 888         /* DC CISW */
 889         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 890           access_dcsw },
 891
 892         DBG_BCR_BVR_WCR_WVR_EL1(0),
 893         DBG_BCR_BVR_WCR_WVR_EL1(1),
 894         { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
 895         { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
 896         DBG_BCR_BVR_WCR_WVR_EL1(2),
 897         DBG_BCR_BVR_WCR_WVR_EL1(3),
 898         DBG_BCR_BVR_WCR_WVR_EL1(4),
 899         DBG_BCR_BVR_WCR_WVR_EL1(5),
 900         DBG_BCR_BVR_WCR_WVR_EL1(6),
 901         DBG_BCR_BVR_WCR_WVR_EL1(7),
 902         DBG_BCR_BVR_WCR_WVR_EL1(8),
 903         DBG_BCR_BVR_WCR_WVR_EL1(9),
 904         DBG_BCR_BVR_WCR_WVR_EL1(10),
 905         DBG_BCR_BVR_WCR_WVR_EL1(11),
 906         DBG_BCR_BVR_WCR_WVR_EL1(12),
 907         DBG_BCR_BVR_WCR_WVR_EL1(13),
 908         DBG_BCR_BVR_WCR_WVR_EL1(14),
 909         DBG_BCR_BVR_WCR_WVR_EL1(15),
 910
 911         { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
 912         { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
 913         { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
 914         { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
 915         { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
 916         { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
 917         { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
 918         { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
 919
 920         { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
 921         { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
 922         // DBGDTR[TR]X_EL0 share the same encoding
 923         { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
 924
 925         { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
 926
 927         /* MPIDR_EL1 */
 928         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 929           NULL, reset_mpidr, MPIDR_EL1 },
 930         /* SCTLR_EL1 */
 931         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 932           access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
 933         /* CPACR_EL1 */
 934         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
 935           NULL, reset_val, CPACR_EL1, 0 },
 936         /* TTBR0_EL1 */
 937         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
 938           access_vm_reg, reset_unknown, TTBR0_EL1 },
 939         /* TTBR1_EL1 */
 940         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
 941           access_vm_reg, reset_unknown, TTBR1_EL1 },
 942         /* TCR_EL1 */
 943         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
 944           access_vm_reg, reset_val, TCR_EL1, 0 },
 945
 946         /* AFSR0_EL1 */
 947         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
 948           access_vm_reg, reset_unknown, AFSR0_EL1 },
 949         /* AFSR1_EL1 */
 950         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
 951           access_vm_reg, reset_unknown, AFSR1_EL1 },
 952         /* ESR_EL1 */
 953         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
 954           access_vm_reg, reset_unknown, ESR_EL1 },
 955         /* FAR_EL1 */
 956         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
 957           access_vm_reg, reset_unknown, FAR_EL1 },
 958         /* PAR_EL1 */
 959         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
 960           NULL, reset_unknown, PAR_EL1 },
 961
 962         { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
 963         { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },
 964
 965         /* MAIR_EL1 */
 966         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
 967           access_vm_reg, reset_unknown, MAIR_EL1 },
 968         /* AMAIR_EL1 */
 969         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
 970           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 971
 972         /* VBAR_EL1 */
 973         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
 974           NULL, reset_val, VBAR_EL1, 0 },
 975
 976         { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
 977         { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
 978
 979         /* CONTEXTIDR_EL1 */
 980         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
 981           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 982         /* TPIDR_EL1 */
 983         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
 984           NULL, reset_unknown, TPIDR_EL1 },
 985
 986         /* CNTKCTL_EL1 */
 987         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
 988           NULL, reset_val, CNTKCTL_EL1, 0},
 989
 990         /* CSSELR_EL1 */
 991         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 992           NULL, reset_unknown, CSSELR_EL1 },
 993
 994         { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, },
 995         { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
 996         { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 },
 997         { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 },
 998         { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
 999         { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1000         { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1001         { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1002         { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1003         { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1004         { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1005         /*
1006          * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1007          * in 32bit mode. Here we choose to reset it as zero for consistency.
1008          */
1009         { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1010         { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1011
1012         /* TPIDR_EL0 */
1013         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
1014           NULL, reset_unknown, TPIDR_EL0 },
1015         /* TPIDRRO_EL0 */
1016         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1017           NULL, reset_unknown, TPIDRRO_EL0 },
1018
1019         /* CNTP_TVAL_EL0 */
1020         { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b000),
1021           access_cntp_tval },
1022         /* CNTP_CTL_EL0 */
1023         { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b001),
1024           access_cntp_ctl },
1025         /* CNTP_CVAL_EL0 */
1026         { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b010),
1027           access_cntp_cval },
1028
1029         /* PMEVCNTRn_EL0 */
1030         PMU_PMEVCNTR_EL0(0),
1031         PMU_PMEVCNTR_EL0(1),
1032         PMU_PMEVCNTR_EL0(2),
1033         PMU_PMEVCNTR_EL0(3),
1034         PMU_PMEVCNTR_EL0(4),
1035         PMU_PMEVCNTR_EL0(5),
1036         PMU_PMEVCNTR_EL0(6),
1037         PMU_PMEVCNTR_EL0(7),
1038         PMU_PMEVCNTR_EL0(8),
1039         PMU_PMEVCNTR_EL0(9),
1040         PMU_PMEVCNTR_EL0(10),
1041         PMU_PMEVCNTR_EL0(11),
1042         PMU_PMEVCNTR_EL0(12),
1043         PMU_PMEVCNTR_EL0(13),
1044         PMU_PMEVCNTR_EL0(14),
1045         PMU_PMEVCNTR_EL0(15),
1046         PMU_PMEVCNTR_EL0(16),
1047         PMU_PMEVCNTR_EL0(17),
1048         PMU_PMEVCNTR_EL0(18),
1049         PMU_PMEVCNTR_EL0(19),
1050         PMU_PMEVCNTR_EL0(20),
1051         PMU_PMEVCNTR_EL0(21),
1052         PMU_PMEVCNTR_EL0(22),
1053         PMU_PMEVCNTR_EL0(23),
1054         PMU_PMEVCNTR_EL0(24),
1055         PMU_PMEVCNTR_EL0(25),
1056         PMU_PMEVCNTR_EL0(26),
1057         PMU_PMEVCNTR_EL0(27),
1058         PMU_PMEVCNTR_EL0(28),
1059         PMU_PMEVCNTR_EL0(29),
1060         PMU_PMEVCNTR_EL0(30),
1061         /* PMEVTYPERn_EL0 */
1062         PMU_PMEVTYPER_EL0(0),
1063         PMU_PMEVTYPER_EL0(1),
1064         PMU_PMEVTYPER_EL0(2),
1065         PMU_PMEVTYPER_EL0(3),
1066         PMU_PMEVTYPER_EL0(4),
1067         PMU_PMEVTYPER_EL0(5),
1068         PMU_PMEVTYPER_EL0(6),
1069         PMU_PMEVTYPER_EL0(7),
1070         PMU_PMEVTYPER_EL0(8),
1071         PMU_PMEVTYPER_EL0(9),
1072         PMU_PMEVTYPER_EL0(10),
1073         PMU_PMEVTYPER_EL0(11),
1074         PMU_PMEVTYPER_EL0(12),
1075         PMU_PMEVTYPER_EL0(13),
1076         PMU_PMEVTYPER_EL0(14),
1077         PMU_PMEVTYPER_EL0(15),
1078         PMU_PMEVTYPER_EL0(16),
1079         PMU_PMEVTYPER_EL0(17),
1080         PMU_PMEVTYPER_EL0(18),
1081         PMU_PMEVTYPER_EL0(19),
1082         PMU_PMEVTYPER_EL0(20),
1083         PMU_PMEVTYPER_EL0(21),
1084         PMU_PMEVTYPER_EL0(22),
1085         PMU_PMEVTYPER_EL0(23),
1086         PMU_PMEVTYPER_EL0(24),
1087         PMU_PMEVTYPER_EL0(25),
1088         PMU_PMEVTYPER_EL0(26),
1089         PMU_PMEVTYPER_EL0(27),
1090         PMU_PMEVTYPER_EL0(28),
1091         PMU_PMEVTYPER_EL0(29),
1092         PMU_PMEVTYPER_EL0(30),
1093         /*
1094          * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1095          * in 32bit mode. Here we choose to reset it as zero for consistency.
1096          */
1097         { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1098
1099         /* DACR32_EL2 */
1100         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
1101           NULL, reset_unknown, DACR32_EL2 },
1102         /* IFSR32_EL2 */
1103         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
1104           NULL, reset_unknown, IFSR32_EL2 },
1105         /* FPEXC32_EL2 */
1106         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
1107           NULL, reset_val, FPEXC32_EL2, 0x70 },
1108 };
1109
1110 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1111                         struct sys_reg_params *p,
1112                         const struct sys_reg_desc *r)
1113 {
1114         if (p->is_write) {
1115                 return ignore_write(vcpu, p);
1116         } else {
1117                 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1118                 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
1119                 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1120
1121                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1122                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1123                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1124                              | (6 << 16) | (el3 << 14) | (el3 << 12));
1125                 return true;
1126         }
1127 }
1128
1129 static bool trap_debug32(struct kvm_vcpu *vcpu,
1130                          struct sys_reg_params *p,
1131                          const struct sys_reg_desc *r)
1132 {
1133         if (p->is_write) {
1134                 vcpu_cp14(vcpu, r->reg) = p->regval;
1135                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1136         } else {
1137                 p->regval = vcpu_cp14(vcpu, r->reg);
1138         }
1139
1140         return true;
1141 }
1142
1143 /* AArch32 debug register mappings
1144  *
1145  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1146  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1147  *
1148  * All control registers and watchpoint value registers are mapped to
1149  * the lower 32 bits of their AArch64 equivalents. We share the trap
1150  * handlers with the above AArch64 code which checks what mode the
1151  * system is in.
1152  */
1153
1154 static bool trap_xvr(struct kvm_vcpu *vcpu,
1155                      struct sys_reg_params *p,
1156                      const struct sys_reg_desc *rd)
1157 {
1158         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1159
1160         if (p->is_write) {
1161                 u64 val = *dbg_reg;
1162
1163                 val &= 0xffffffffUL;
1164                 val |= p->regval << 32;
1165                 *dbg_reg = val;
1166
1167                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1168         } else {
1169                 p->regval = *dbg_reg >> 32;
1170         }
1171
1172         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1173
1174         return true;
1175 }
1176
1177 #define DBG_BCR_BVR_WCR_WVR(n)                                          \
1178         /* DBGBVRn */                                                   \
1179         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n },     \
1180         /* DBGBCRn */                                                   \
1181         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },     \
1182         /* DBGWVRn */                                                   \
1183         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },     \
1184         /* DBGWCRn */                                                   \
1185         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1186
1187 #define DBGBXVR(n)                                                      \
1188         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1189
1190 /*
1191  * Trapped cp14 registers. We generally ignore most of the external
1192  * debug, on the principle that they don't really make sense to a
1193  * guest. Revisit this one day, would this principle change.
1194  */
1195 static const struct sys_reg_desc cp14_regs[] = {
1196         /* DBGIDR */
1197         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1198         /* DBGDTRRXext */
1199         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1200
1201         DBG_BCR_BVR_WCR_WVR(0),
1202         /* DBGDSCRint */
1203         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1204         DBG_BCR_BVR_WCR_WVR(1),
1205         /* DBGDCCINT */
1206         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1207         /* DBGDSCRext */
1208         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1209         DBG_BCR_BVR_WCR_WVR(2),
1210         /* DBGDTR[RT]Xint */
1211         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1212         /* DBGDTR[RT]Xext */
1213         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1214         DBG_BCR_BVR_WCR_WVR(3),
1215         DBG_BCR_BVR_WCR_WVR(4),
1216         DBG_BCR_BVR_WCR_WVR(5),
1217         /* DBGWFAR */
1218         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1219         /* DBGOSECCR */
1220         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1221         DBG_BCR_BVR_WCR_WVR(6),
1222         /* DBGVCR */
1223         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1224         DBG_BCR_BVR_WCR_WVR(7),
1225         DBG_BCR_BVR_WCR_WVR(8),
1226         DBG_BCR_BVR_WCR_WVR(9),
1227         DBG_BCR_BVR_WCR_WVR(10),
1228         DBG_BCR_BVR_WCR_WVR(11),
1229         DBG_BCR_BVR_WCR_WVR(12),
1230         DBG_BCR_BVR_WCR_WVR(13),
1231         DBG_BCR_BVR_WCR_WVR(14),
1232         DBG_BCR_BVR_WCR_WVR(15),
1233
1234         /* DBGDRAR (32bit) */
1235         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1236
1237         DBGBXVR(0),
1238         /* DBGOSLAR */
1239         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1240         DBGBXVR(1),
1241         /* DBGOSLSR */
1242         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1243         DBGBXVR(2),
1244         DBGBXVR(3),
1245         /* DBGOSDLR */
1246         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1247         DBGBXVR(4),
1248         /* DBGPRCR */
1249         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1250         DBGBXVR(5),
1251         DBGBXVR(6),
1252         DBGBXVR(7),
1253         DBGBXVR(8),
1254         DBGBXVR(9),
1255         DBGBXVR(10),
1256         DBGBXVR(11),
1257         DBGBXVR(12),
1258         DBGBXVR(13),
1259         DBGBXVR(14),
1260         DBGBXVR(15),
1261
1262         /* DBGDSAR (32bit) */
1263         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1264
1265         /* DBGDEVID2 */
1266         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1267         /* DBGDEVID1 */
1268         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1269         /* DBGDEVID */
1270         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1271         /* DBGCLAIMSET */
1272         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1273         /* DBGCLAIMCLR */
1274         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1275         /* DBGAUTHSTATUS */
1276         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1277 };
1278
1279 /* Trapped cp14 64bit registers */
1280 static const struct sys_reg_desc cp14_64_regs[] = {
1281         /* DBGDRAR (64bit) */
1282         { Op1( 0), CRm( 1), .access = trap_raz_wi },
1283
1284         /* DBGDSAR (64bit) */
1285         { Op1( 0), CRm( 2), .access = trap_raz_wi },
1286 };
1287
1288 /* Macro to expand the PMEVCNTRn register */
1289 #define PMU_PMEVCNTR(n)                                                 \
1290         /* PMEVCNTRn */                                                 \
1291         { Op1(0), CRn(0b1110),                                          \
1292           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1293           access_pmu_evcntr }
1294
1295 /* Macro to expand the PMEVTYPERn register */
1296 #define PMU_PMEVTYPER(n)                                                \
1297         /* PMEVTYPERn */                                                \
1298         { Op1(0), CRn(0b1110),                                          \
1299           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1300           access_pmu_evtyper }
1301
1302 /*
1303  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1304  * depending on the way they are accessed (as a 32bit or a 64bit
1305  * register).
1306  */
1307 static const struct sys_reg_desc cp15_regs[] = {
1308         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1309
1310         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1311         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1312         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1313         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1314         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1315         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1316         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1317         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1318         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1319         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1320         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1321
1322         /*
1323          * DC{C,I,CI}SW operations:
1324          */
1325         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1326         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1327         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1328
1329         /* PMU */
1330         { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1331         { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1332         { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1333         { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1334         { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1335         { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1336         { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1337         { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1338         { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1339         { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1340         { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1341         { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1342         { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1343         { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1344         { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1345
1346         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1347         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1348         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1349         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1350
1351         /* ICC_SRE */
1352         { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1353
1354         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1355
1356         /* PMEVCNTRn */
1357         PMU_PMEVCNTR(0),
1358         PMU_PMEVCNTR(1),
1359         PMU_PMEVCNTR(2),
1360         PMU_PMEVCNTR(3),
1361         PMU_PMEVCNTR(4),
1362         PMU_PMEVCNTR(5),
1363         PMU_PMEVCNTR(6),
1364         PMU_PMEVCNTR(7),
1365         PMU_PMEVCNTR(8),
1366         PMU_PMEVCNTR(9),
1367         PMU_PMEVCNTR(10),
1368         PMU_PMEVCNTR(11),
1369         PMU_PMEVCNTR(12),
1370         PMU_PMEVCNTR(13),
1371         PMU_PMEVCNTR(14),
1372         PMU_PMEVCNTR(15),
1373         PMU_PMEVCNTR(16),
1374         PMU_PMEVCNTR(17),
1375         PMU_PMEVCNTR(18),
1376         PMU_PMEVCNTR(19),
1377         PMU_PMEVCNTR(20),
1378         PMU_PMEVCNTR(21),
1379         PMU_PMEVCNTR(22),
1380         PMU_PMEVCNTR(23),
1381         PMU_PMEVCNTR(24),
1382         PMU_PMEVCNTR(25),
1383         PMU_PMEVCNTR(26),
1384         PMU_PMEVCNTR(27),
1385         PMU_PMEVCNTR(28),
1386         PMU_PMEVCNTR(29),
1387         PMU_PMEVCNTR(30),
1388         /* PMEVTYPERn */
1389         PMU_PMEVTYPER(0),
1390         PMU_PMEVTYPER(1),
1391         PMU_PMEVTYPER(2),
1392         PMU_PMEVTYPER(3),
1393         PMU_PMEVTYPER(4),
1394         PMU_PMEVTYPER(5),
1395         PMU_PMEVTYPER(6),
1396         PMU_PMEVTYPER(7),
1397         PMU_PMEVTYPER(8),
1398         PMU_PMEVTYPER(9),
1399         PMU_PMEVTYPER(10),
1400         PMU_PMEVTYPER(11),
1401         PMU_PMEVTYPER(12),
1402         PMU_PMEVTYPER(13),
1403         PMU_PMEVTYPER(14),
1404         PMU_PMEVTYPER(15),
1405         PMU_PMEVTYPER(16),
1406         PMU_PMEVTYPER(17),
1407         PMU_PMEVTYPER(18),
1408         PMU_PMEVTYPER(19),
1409         PMU_PMEVTYPER(20),
1410         PMU_PMEVTYPER(21),
1411         PMU_PMEVTYPER(22),
1412         PMU_PMEVTYPER(23),
1413         PMU_PMEVTYPER(24),
1414         PMU_PMEVTYPER(25),
1415         PMU_PMEVTYPER(26),
1416         PMU_PMEVTYPER(27),
1417         PMU_PMEVTYPER(28),
1418         PMU_PMEVTYPER(29),
1419         PMU_PMEVTYPER(30),
1420         /* PMCCFILTR */
1421         { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1422 };
1423
1424 static const struct sys_reg_desc cp15_64_regs[] = {
1425         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1426         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1427         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1428         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1429 };
1430
1431 /* Target specific emulation tables */
1432 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1433
1434 void kvm_register_target_sys_reg_table(unsigned int target,
1435                                        struct kvm_sys_reg_target_table *table)
1436 {
1437         target_tables[target] = table;
1438 }
1439
1440 /* Get specific register table for this target. */
1441 static const struct sys_reg_desc *get_target_table(unsigned target,
1442                                                    bool mode_is_64,
1443                                                    size_t *num)
1444 {
1445         struct kvm_sys_reg_target_table *table;
1446
1447         table = target_tables[target];
1448         if (mode_is_64) {
1449                 *num = table->table64.num;
1450                 return table->table64.table;
1451         } else {
1452                 *num = table->table32.num;
1453                 return table->table32.table;
1454         }
1455 }
1456
1457 #define reg_to_match_value(x)                                           \
1458         ({                                                              \
1459                 unsigned long val;                                      \
1460                 val  = (x)->Op0 << 14;                                  \
1461                 val |= (x)->Op1 << 11;                                  \
1462                 val |= (x)->CRn << 7;                                   \
1463                 val |= (x)->CRm << 3;                                   \
1464                 val |= (x)->Op2;                                        \
1465                 val;                                                    \
1466          })
1467
1468 static int match_sys_reg(const void *key, const void *elt)
1469 {
1470         const unsigned long pval = (unsigned long)key;
1471         const struct sys_reg_desc *r = elt;
1472
1473         return pval - reg_to_match_value(r);
1474 }
1475
1476 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1477                                          const struct sys_reg_desc table[],
1478                                          unsigned int num)
1479 {
1480         unsigned long pval = reg_to_match_value(params);
1481
1482         return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
1483 }
1484
1485 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1486 {
1487         kvm_inject_undefined(vcpu);
1488         return 1;
1489 }
1490
1491 /*
1492  * emulate_cp --  tries to match a sys_reg access in a handling table, and
1493  *                call the corresponding trap handler.
1494  *
1495  * @params: pointer to the descriptor of the access
1496  * @table: array of trap descriptors
1497  * @num: size of the trap descriptor array
1498  *
1499  * Return 0 if the access has been handled, and -1 if not.
1500  */
1501 static int emulate_cp(struct kvm_vcpu *vcpu,
1502                       struct sys_reg_params *params,
1503                       const struct sys_reg_desc *table,
1504                       size_t num)
1505 {
1506         const struct sys_reg_desc *r;
1507
1508         if (!table)
1509                 return -1;      /* Not handled */
1510
1511         r = find_reg(params, table, num);
1512
1513         if (r) {
1514                 /*
1515                  * Not having an accessor means that we have
1516                  * configured a trap that we don't know how to
1517                  * handle. This certainly qualifies as a gross bug
1518                  * that should be fixed right away.
1519                  */
1520                 BUG_ON(!r->access);
1521
1522                 if (likely(r->access(vcpu, params, r))) {
1523                         /* Skip instruction, since it was emulated */
1524                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1525                         /* Handled */
1526                         return 0;
1527                 }
1528         }
1529
1530         /* Not handled */
1531         return -1;
1532 }
1533
1534 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1535                                 struct sys_reg_params *params)
1536 {
1537         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1538         int cp = -1;
1539
1540         switch(hsr_ec) {
1541         case ESR_ELx_EC_CP15_32:
1542         case ESR_ELx_EC_CP15_64:
1543                 cp = 15;
1544                 break;
1545         case ESR_ELx_EC_CP14_MR:
1546         case ESR_ELx_EC_CP14_64:
1547                 cp = 14;
1548                 break;
1549         default:
1550                 WARN_ON(1);
1551         }
1552
1553         kvm_err("Unsupported guest CP%d access at: %08lx\n",
1554                 cp, *vcpu_pc(vcpu));
1555         print_sys_reg_instr(params);
1556         kvm_inject_undefined(vcpu);
1557 }
1558
1559 /**
1560  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
1561  * @vcpu: The VCPU pointer
1562  * @run:  The kvm_run struct
1563  */
1564 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1565                             const struct sys_reg_desc *global,
1566                             size_t nr_global,
1567                             const struct sys_reg_desc *target_specific,
1568                             size_t nr_specific)
1569 {
1570         struct sys_reg_params params;
1571         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1572         int Rt = (hsr >> 5) & 0xf;
1573         int Rt2 = (hsr >> 10) & 0xf;
1574
1575         params.is_aarch32 = true;
1576         params.is_32bit = false;
1577         params.CRm = (hsr >> 1) & 0xf;
1578         params.is_write = ((hsr & 1) == 0);
1579
1580         params.Op0 = 0;
1581         params.Op1 = (hsr >> 16) & 0xf;
1582         params.Op2 = 0;
1583         params.CRn = 0;
1584
1585         /*
1586          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
1587          * backends between AArch32 and AArch64, we get away with it.
1588          */
1589         if (params.is_write) {
1590                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1591                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1592         }
1593
1594         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1595                 goto out;
1596         if (!emulate_cp(vcpu, &params, global, nr_global))
1597                 goto out;
1598
1599         unhandled_cp_access(vcpu, &params);
1600
1601 out:
1602         /* Split up the value between registers for the read side */
1603         if (!params.is_write) {
1604                 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1605                 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1606         }
1607
1608         return 1;
1609 }
1610
1611 /**
1612  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
1613  * @vcpu: The VCPU pointer
1614  * @run:  The kvm_run struct
1615  */
1616 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1617                             const struct sys_reg_desc *global,
1618                             size_t nr_global,
1619                             const struct sys_reg_desc *target_specific,
1620                             size_t nr_specific)
1621 {
1622         struct sys_reg_params params;
1623         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1624         int Rt  = (hsr >> 5) & 0xf;
1625
1626         params.is_aarch32 = true;
1627         params.is_32bit = true;
1628         params.CRm = (hsr >> 1) & 0xf;
1629         params.regval = vcpu_get_reg(vcpu, Rt);
1630         params.is_write = ((hsr & 1) == 0);
1631         params.CRn = (hsr >> 10) & 0xf;
1632         params.Op0 = 0;
1633         params.Op1 = (hsr >> 14) & 0x7;
1634         params.Op2 = (hsr >> 17) & 0x7;
1635
1636         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1637             !emulate_cp(vcpu, &params, global, nr_global)) {
1638                 if (!params.is_write)
1639                         vcpu_set_reg(vcpu, Rt, params.regval);
1640                 return 1;
1641         }
1642
1643         unhandled_cp_access(vcpu, &params);
1644         return 1;
1645 }
1646
1647 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1648 {
1649         const struct sys_reg_desc *target_specific;
1650         size_t num;
1651
1652         target_specific = get_target_table(vcpu->arch.target, false, &num);
1653         return kvm_handle_cp_64(vcpu,
1654                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
1655                                 target_specific, num);
1656 }
1657
1658 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1659 {
1660         const struct sys_reg_desc *target_specific;
1661         size_t num;
1662
1663         target_specific = get_target_table(vcpu->arch.target, false, &num);
1664         return kvm_handle_cp_32(vcpu,
1665                                 cp15_regs, ARRAY_SIZE(cp15_regs),
1666                                 target_specific, num);
1667 }
1668
1669 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1670 {
1671         return kvm_handle_cp_64(vcpu,
1672                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
1673                                 NULL, 0);
1674 }
1675
1676 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1677 {
1678         return kvm_handle_cp_32(vcpu,
1679                                 cp14_regs, ARRAY_SIZE(cp14_regs),
1680                                 NULL, 0);
1681 }
1682
1683 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
1684                            struct sys_reg_params *params)
1685 {
1686         size_t num;
1687         const struct sys_reg_desc *table, *r;
1688
1689         table = get_target_table(vcpu->arch.target, true, &num);
1690
1691         /* Search target-specific then generic table. */
1692         r = find_reg(params, table, num);
1693         if (!r)
1694                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1695
1696         if (likely(r)) {
1697                 /*
1698                  * Not having an accessor means that we have
1699                  * configured a trap that we don't know how to
1700                  * handle. This certainly qualifies as a gross bug
1701                  * that should be fixed right away.
1702                  */
1703                 BUG_ON(!r->access);
1704
1705                 if (likely(r->access(vcpu, params, r))) {
1706                         /* Skip instruction, since it was emulated */
1707                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1708                         return 1;
1709                 }
1710                 /* If access function fails, it should complain. */
1711         } else {
1712                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1713                         *vcpu_pc(vcpu));
1714                 print_sys_reg_instr(params);
1715         }
1716         kvm_inject_undefined(vcpu);
1717         return 1;
1718 }
1719
1720 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1721                               const struct sys_reg_desc *table, size_t num)
1722 {
1723         unsigned long i;
1724
1725         for (i = 0; i < num; i++)
1726                 if (table[i].reset)
1727                         table[i].reset(vcpu, &table[i]);
1728 }
1729
1730 /**
1731  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1732  * @vcpu: The VCPU pointer
1733  * @run:  The kvm_run struct
1734  */
1735 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1736 {
1737         struct sys_reg_params params;
1738         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1739         int Rt = (esr >> 5) & 0x1f;
1740         int ret;
1741
1742         trace_kvm_handle_sys_reg(esr);
1743
1744         params.is_aarch32 = false;
1745         params.is_32bit = false;
1746         params.Op0 = (esr >> 20) & 3;
1747         params.Op1 = (esr >> 14) & 0x7;
1748         params.CRn = (esr >> 10) & 0xf;
1749         params.CRm = (esr >> 1) & 0xf;
1750         params.Op2 = (esr >> 17) & 0x7;
1751         params.regval = vcpu_get_reg(vcpu, Rt);
1752         params.is_write = !(esr & 1);
1753
1754         ret = emulate_sys_reg(vcpu, &params);
1755
1756         if (!params.is_write)
1757                 vcpu_set_reg(vcpu, Rt, params.regval);
1758         return ret;
1759 }
1760
1761 /******************************************************************************
1762  * Userspace API
1763  *****************************************************************************/
1764
1765 static bool index_to_params(u64 id, struct sys_reg_params *params)
1766 {
1767         switch (id & KVM_REG_SIZE_MASK) {
1768         case KVM_REG_SIZE_U64:
1769                 /* Any unused index bits means it's not valid. */
1770                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1771                               | KVM_REG_ARM_COPROC_MASK
1772                               | KVM_REG_ARM64_SYSREG_OP0_MASK
1773                               | KVM_REG_ARM64_SYSREG_OP1_MASK
1774                               | KVM_REG_ARM64_SYSREG_CRN_MASK
1775                               | KVM_REG_ARM64_SYSREG_CRM_MASK
1776                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
1777                         return false;
1778                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1779                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1780                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1781                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1782                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1783                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1784                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1785                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1786                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1787                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1788                 return true;
1789         default:
1790                 return false;
1791         }
1792 }
1793
1794 const struct sys_reg_desc *find_reg_by_id(u64 id,
1795                                           struct sys_reg_params *params,
1796                                           const struct sys_reg_desc table[],
1797                                           unsigned int num)
1798 {
1799         if (!index_to_params(id, params))
1800                 return NULL;
1801
1802         return find_reg(params, table, num);
1803 }
1804
1805 /* Decode an index value, and find the sys_reg_desc entry. */
1806 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1807                                                     u64 id)
1808 {
1809         size_t num;
1810         const struct sys_reg_desc *table, *r;
1811         struct sys_reg_params params;
1812
1813         /* We only do sys_reg for now. */
1814         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1815                 return NULL;
1816
1817         table = get_target_table(vcpu->arch.target, true, &num);
1818         r = find_reg_by_id(id, &params, table, num);
1819         if (!r)
1820                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1821
1822         /* Not saved in the sys_reg array? */
1823         if (r && !r->reg)
1824                 r = NULL;
1825
1826         return r;
1827 }
1828
1829 /*
1830  * These are the invariant sys_reg registers: we let the guest see the
1831  * host versions of these, so they're part of the guest state.
1832  *
1833  * A future CPU may provide a mechanism to present different values to
1834  * the guest, or a future kvm may trap them.
1835  */
1836
1837 #define FUNCTION_INVARIANT(reg)                                         \
1838         static void get_##reg(struct kvm_vcpu *v,                       \
1839                               const struct sys_reg_desc *r)             \
1840         {                                                               \
1841                 ((struct sys_reg_desc *)r)->val = read_sysreg(reg);     \
1842         }
1843
1844 FUNCTION_INVARIANT(midr_el1)
1845 FUNCTION_INVARIANT(ctr_el0)
1846 FUNCTION_INVARIANT(revidr_el1)
1847 FUNCTION_INVARIANT(id_pfr0_el1)
1848 FUNCTION_INVARIANT(id_pfr1_el1)
1849 FUNCTION_INVARIANT(id_dfr0_el1)
1850 FUNCTION_INVARIANT(id_afr0_el1)
1851 FUNCTION_INVARIANT(id_mmfr0_el1)
1852 FUNCTION_INVARIANT(id_mmfr1_el1)
1853 FUNCTION_INVARIANT(id_mmfr2_el1)
1854 FUNCTION_INVARIANT(id_mmfr3_el1)
1855 FUNCTION_INVARIANT(id_isar0_el1)
1856 FUNCTION_INVARIANT(id_isar1_el1)
1857 FUNCTION_INVARIANT(id_isar2_el1)
1858 FUNCTION_INVARIANT(id_isar3_el1)
1859 FUNCTION_INVARIANT(id_isar4_el1)
1860 FUNCTION_INVARIANT(id_isar5_el1)
1861 FUNCTION_INVARIANT(clidr_el1)
1862 FUNCTION_INVARIANT(aidr_el1)
1863
1864 /* ->val is filled in by kvm_sys_reg_table_init() */
1865 static struct sys_reg_desc invariant_sys_regs[] = {
1866         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1867           NULL, get_midr_el1 },
1868         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1869           NULL, get_revidr_el1 },
1870         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1871           NULL, get_id_pfr0_el1 },
1872         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1873           NULL, get_id_pfr1_el1 },
1874         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1875           NULL, get_id_dfr0_el1 },
1876         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1877           NULL, get_id_afr0_el1 },
1878         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1879           NULL, get_id_mmfr0_el1 },
1880         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1881           NULL, get_id_mmfr1_el1 },
1882         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1883           NULL, get_id_mmfr2_el1 },
1884         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1885           NULL, get_id_mmfr3_el1 },
1886         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1887           NULL, get_id_isar0_el1 },
1888         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1889           NULL, get_id_isar1_el1 },
1890         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1891           NULL, get_id_isar2_el1 },
1892         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1893           NULL, get_id_isar3_el1 },
1894         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1895           NULL, get_id_isar4_el1 },
1896         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1897           NULL, get_id_isar5_el1 },
1898         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1899           NULL, get_clidr_el1 },
1900         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1901           NULL, get_aidr_el1 },
1902         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1903           NULL, get_ctr_el0 },
1904 };
1905
1906 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1907 {
1908         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1909                 return -EFAULT;
1910         return 0;
1911 }
1912
1913 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1914 {
1915         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1916                 return -EFAULT;
1917         return 0;
1918 }
1919
1920 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1921 {
1922         struct sys_reg_params params;
1923         const struct sys_reg_desc *r;
1924
1925         r = find_reg_by_id(id, &params, invariant_sys_regs,
1926                            ARRAY_SIZE(invariant_sys_regs));
1927         if (!r)
1928                 return -ENOENT;
1929
1930         return reg_to_user(uaddr, &r->val, id);
1931 }
1932
1933 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1934 {
1935         struct sys_reg_params params;
1936         const struct sys_reg_desc *r;
1937         int err;
1938         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1939
1940         r = find_reg_by_id(id, &params, invariant_sys_regs,
1941                            ARRAY_SIZE(invariant_sys_regs));
1942         if (!r)
1943                 return -ENOENT;
1944
1945         err = reg_from_user(&val, uaddr, id);
1946         if (err)
1947                 return err;
1948
1949         /* This is what we mean by invariant: you can't change it. */
1950         if (r->val != val)
1951                 return -EINVAL;
1952
1953         return 0;
1954 }
1955
1956 static bool is_valid_cache(u32 val)
1957 {
1958         u32 level, ctype;
1959
1960         if (val >= CSSELR_MAX)
1961                 return false;
1962
1963         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1964         level = (val >> 1);
1965         ctype = (cache_levels >> (level * 3)) & 7;
1966
1967         switch (ctype) {
1968         case 0: /* No cache */
1969                 return false;
1970         case 1: /* Instruction cache only */
1971                 return (val & 1);
1972         case 2: /* Data cache only */
1973         case 4: /* Unified cache */
1974                 return !(val & 1);
1975         case 3: /* Separate instruction and data caches */
1976                 return true;
1977         default: /* Reserved: we can't know instruction or data. */
1978                 return false;
1979         }
1980 }
1981
1982 static int demux_c15_get(u64 id, void __user *uaddr)
1983 {
1984         u32 val;
1985         u32 __user *uval = uaddr;
1986
1987         /* Fail if we have unknown bits set. */
1988         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1989                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1990                 return -ENOENT;
1991
1992         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1993         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1994                 if (KVM_REG_SIZE(id) != 4)
1995                         return -ENOENT;
1996                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1997                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1998                 if (!is_valid_cache(val))
1999                         return -ENOENT;
2000
2001                 return put_user(get_ccsidr(val), uval);
2002         default:
2003                 return -ENOENT;
2004         }
2005 }
2006
2007 static int demux_c15_set(u64 id, void __user *uaddr)
2008 {
2009         u32 val, newval;
2010         u32 __user *uval = uaddr;
2011
2012         /* Fail if we have unknown bits set. */
2013         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2014                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2015                 return -ENOENT;
2016
2017         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2018         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2019                 if (KVM_REG_SIZE(id) != 4)
2020                         return -ENOENT;
2021                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2022                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2023                 if (!is_valid_cache(val))
2024                         return -ENOENT;
2025
2026                 if (get_user(newval, uval))
2027                         return -EFAULT;
2028
2029                 /* This is also invariant: you can't change it. */
2030                 if (newval != get_ccsidr(val))
2031                         return -EINVAL;
2032                 return 0;
2033         default:
2034                 return -ENOENT;
2035         }
2036 }
2037
2038 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2039 {
2040         const struct sys_reg_desc *r;
2041         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2042
2043         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2044                 return demux_c15_get(reg->id, uaddr);
2045
2046         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2047                 return -ENOENT;
2048
2049         r = index_to_sys_reg_desc(vcpu, reg->id);
2050         if (!r)
2051                 return get_invariant_sys_reg(reg->id, uaddr);
2052
2053         if (r->get_user)
2054                 return (r->get_user)(vcpu, r, reg, uaddr);
2055
2056         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2057 }
2058
2059 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2060 {
2061         const struct sys_reg_desc *r;
2062         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2063
2064         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2065                 return demux_c15_set(reg->id, uaddr);
2066
2067         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2068                 return -ENOENT;
2069
2070         r = index_to_sys_reg_desc(vcpu, reg->id);
2071         if (!r)
2072                 return set_invariant_sys_reg(reg->id, uaddr);
2073
2074         if (r->set_user)
2075                 return (r->set_user)(vcpu, r, reg, uaddr);
2076
2077         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2078 }
2079
2080 static unsigned int num_demux_regs(void)
2081 {
2082         unsigned int i, count = 0;
2083
2084         for (i = 0; i < CSSELR_MAX; i++)
2085                 if (is_valid_cache(i))
2086                         count++;
2087
2088         return count;
2089 }
2090
2091 static int write_demux_regids(u64 __user *uindices)
2092 {
2093         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2094         unsigned int i;
2095
2096         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2097         for (i = 0; i < CSSELR_MAX; i++) {
2098                 if (!is_valid_cache(i))
2099                         continue;
2100                 if (put_user(val | i, uindices))
2101                         return -EFAULT;
2102                 uindices++;
2103         }
2104         return 0;
2105 }
2106
2107 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2108 {
2109         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2110                 KVM_REG_ARM64_SYSREG |
2111                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2112                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2113                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2114                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2115                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2116 }
2117
2118 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2119 {
2120         if (!*uind)
2121                 return true;
2122
2123         if (put_user(sys_reg_to_index(reg), *uind))
2124                 return false;
2125
2126         (*uind)++;
2127         return true;
2128 }
2129
2130 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2131 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2132 {
2133         const struct sys_reg_desc *i1, *i2, *end1, *end2;
2134         unsigned int total = 0;
2135         size_t num;
2136
2137         /* We check for duplicates here, to allow arch-specific overrides. */
2138         i1 = get_target_table(vcpu->arch.target, true, &num);
2139         end1 = i1 + num;
2140         i2 = sys_reg_descs;
2141         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2142
2143         BUG_ON(i1 == end1 || i2 == end2);
2144
2145         /* Walk carefully, as both tables may refer to the same register. */
2146         while (i1 || i2) {
2147                 int cmp = cmp_sys_reg(i1, i2);
2148                 /* target-specific overrides generic entry. */
2149                 if (cmp <= 0) {
2150                         /* Ignore registers we trap but don't save. */
2151                         if (i1->reg) {
2152                                 if (!copy_reg_to_user(i1, &uind))
2153                                         return -EFAULT;
2154                                 total++;
2155                         }
2156                 } else {
2157                         /* Ignore registers we trap but don't save. */
2158                         if (i2->reg) {
2159                                 if (!copy_reg_to_user(i2, &uind))
2160                                         return -EFAULT;
2161                                 total++;
2162                         }
2163                 }
2164
2165                 if (cmp <= 0 && ++i1 == end1)
2166                         i1 = NULL;
2167                 if (cmp >= 0 && ++i2 == end2)
2168                         i2 = NULL;
2169         }
2170         return total;
2171 }
2172
2173 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2174 {
2175         return ARRAY_SIZE(invariant_sys_regs)
2176                 + num_demux_regs()
2177                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2178 }
2179
2180 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2181 {
2182         unsigned int i;
2183         int err;
2184
2185         /* Then give them all the invariant registers' indices. */
2186         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2187                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2188                         return -EFAULT;
2189                 uindices++;
2190         }
2191
2192         err = walk_sys_regs(vcpu, uindices);
2193         if (err < 0)
2194                 return err;
2195         uindices += err;
2196
2197         return write_demux_regids(uindices);
2198 }
2199
2200 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2201 {
2202         unsigned int i;
2203
2204         for (i = 1; i < n; i++) {
2205                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2206                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2207                         return 1;
2208                 }
2209         }
2210
2211         return 0;
2212 }
2213
2214 void kvm_sys_reg_table_init(void)
2215 {
2216         unsigned int i;
2217         struct sys_reg_desc clidr;
2218
2219         /* Make sure tables are unique and in order. */
2220         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2221         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2222         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2223         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2224         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2225         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2226
2227         /* We abuse the reset function to overwrite the table itself. */
2228         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2229                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2230
2231         /*
2232          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
2233          *
2234          *   If software reads the Cache Type fields from Ctype1
2235          *   upwards, once it has seen a value of 0b000, no caches
2236          *   exist at further-out levels of the hierarchy. So, for
2237          *   example, if Ctype3 is the first Cache Type field with a
2238          *   value of 0b000, the values of Ctype4 to Ctype7 must be
2239          *   ignored.
2240          */
2241         get_clidr_el1(NULL, &clidr); /* Ugly... */
2242         cache_levels = clidr.val;
2243         for (i = 0; i < 7; i++)
2244                 if (((cache_levels >> (i*3)) & 7) == 0)
2245                         break;
2246         /* Clear all higher bits. */
2247         cache_levels &= (1 << (i*3))-1;
2248 }
2249
2250 /**
2251  * kvm_reset_sys_regs - sets system registers to reset value
2252  * @vcpu: The VCPU pointer
2253  *
2254  * This function finds the right table above and sets the registers on the
2255  * virtual CPU struct to their architecturally defined reset values.
2256  */
2257 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2258 {
2259         size_t num;
2260         const struct sys_reg_desc *table;
2261
2262         /* Catch someone adding a register without putting in reset entry. */
2263         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2264
2265         /* Generic chip reset first (so target could override). */
2266         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2267
2268         table = get_target_table(vcpu->arch.target, true, &num);
2269         reset_sys_reg_descs(vcpu, table, num);
2270
2271         for (num = 1; num < NR_SYS_REGS; num++)
2272                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2273                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
2274 }