arch/arm64/mm/dma-mapping.c

   1 /*
   2  * SWIOTLB-based DMA API implementation
   3  *
   4  * Copyright (C) 2012 ARM Ltd.
   5  * Author: Catalin Marinas <catalin.marinas@arm.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/gfp.h>
  21 #include <linux/acpi.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/cache.h>
  24 #include <linux/export.h>
  25 #include <linux/slab.h>
  26 #include <linux/genalloc.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dma-contiguous.h>
  29 #include <linux/vmalloc.h>
  30 #include <linux/swiotlb.h>
  31
  32 #include <asm/cacheflush.h>
  33
  34 static int swiotlb __ro_after_init;
  35
  36 static pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot,
  37                                  bool coherent)
  38 {
  39         if (!coherent || (attrs & DMA_ATTR_WRITE_COMBINE))
  40                 return pgprot_writecombine(prot);
  41         return prot;
  42 }
  43
  44 static struct gen_pool *atomic_pool;
  45
  46 #define DEFAULT_DMA_COHERENT_POOL_SIZE  SZ_256K
  47 static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
  48
  49 static int __init early_coherent_pool(char *p)
  50 {
  51         atomic_pool_size = memparse(p, &p);
  52         return 0;
  53 }
  54 early_param("coherent_pool", early_coherent_pool);
  55
  56 static void *__alloc_from_pool(size_t size, struct page **ret_page, gfp_t flags)
  57 {
  58         unsigned long val;
  59         void *ptr = NULL;
  60
  61         if (!atomic_pool) {
  62                 WARN(1, "coherent pool not initialised!\n");
  63                 return NULL;
  64         }
  65
  66         val = gen_pool_alloc(atomic_pool, size);
  67         if (val) {
  68                 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
  69
  70                 *ret_page = phys_to_page(phys);
  71                 ptr = (void *)val;
  72                 memset(ptr, 0, size);
  73         }
  74
  75         return ptr;
  76 }
  77
  78 static bool __in_atomic_pool(void *start, size_t size)
  79 {
  80         return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
  81 }
  82
  83 static int __free_from_pool(void *start, size_t size)
  84 {
  85         if (!__in_atomic_pool(start, size))
  86                 return 0;
  87
  88         gen_pool_free(atomic_pool, (unsigned long)start, size);
  89
  90         return 1;
  91 }
  92
  93 static void *__dma_alloc_coherent(struct device *dev, size_t size,
  94                                   dma_addr_t *dma_handle, gfp_t flags,
  95                                   unsigned long attrs)
  96 {
  97         if (dev == NULL) {
  98                 WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
  99                 return NULL;
 100         }
 101
 102         if (IS_ENABLED(CONFIG_ZONE_DMA) &&
 103             dev->coherent_dma_mask <= DMA_BIT_MASK(32))
 104                 flags |= GFP_DMA;
 105         if (dev_get_cma_area(dev) && gfpflags_allow_blocking(flags)) {
 106                 struct page *page;
 107                 void *addr;
 108
 109                 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
 110                                                         get_order(size));
 111                 if (!page)
 112                         return NULL;
 113
 114                 *dma_handle = phys_to_dma(dev, page_to_phys(page));
 115                 addr = page_address(page);
 116                 memset(addr, 0, size);
 117                 return addr;
 118         } else {
 119                 return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
 120         }
 121 }
 122
 123 static void __dma_free_coherent(struct device *dev, size_t size,
 124                                 void *vaddr, dma_addr_t dma_handle,
 125                                 unsigned long attrs)
 126 {
 127         bool freed;
 128         phys_addr_t paddr = dma_to_phys(dev, dma_handle);
 129
 130         if (dev == NULL) {
 131                 WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
 132                 return;
 133         }
 134
 135         freed = dma_release_from_contiguous(dev,
 136                                         phys_to_page(paddr),
 137                                         size >> PAGE_SHIFT);
 138         if (!freed)
 139                 swiotlb_free_coherent(dev, size, vaddr, dma_handle);
 140 }
 141
 142 static void *__dma_alloc(struct device *dev, size_t size,
 143                          dma_addr_t *dma_handle, gfp_t flags,
 144                          unsigned long attrs)
 145 {
 146         struct page *page;
 147         void *ptr, *coherent_ptr;
 148         bool coherent = is_device_dma_coherent(dev);
 149         pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, false);
 150
 151         size = PAGE_ALIGN(size);
 152
 153         if (!coherent && !gfpflags_allow_blocking(flags)) {
 154                 struct page *page = NULL;
 155                 void *addr = __alloc_from_pool(size, &page, flags);
 156
 157                 if (addr)
 158                         *dma_handle = phys_to_dma(dev, page_to_phys(page));
 159
 160                 return addr;
 161         }
 162
 163         ptr = __dma_alloc_coherent(dev, size, dma_handle, flags, attrs);
 164         if (!ptr)
 165                 goto no_mem;
 166
 167         /* no need for non-cacheable mapping if coherent */
 168         if (coherent)
 169                 return ptr;
 170
 171         /* remove any dirty cache lines on the kernel alias */
 172         __dma_flush_area(ptr, size);
 173
 174         /* create a coherent mapping */
 175         page = virt_to_page(ptr);
 176         coherent_ptr = dma_common_contiguous_remap(page, size, VM_USERMAP,
 177                                                    prot, NULL);
 178         if (!coherent_ptr)
 179                 goto no_map;
 180
 181         return coherent_ptr;
 182
 183 no_map:
 184         __dma_free_coherent(dev, size, ptr, *dma_handle, attrs);
 185 no_mem:
 186         *dma_handle = DMA_ERROR_CODE;
 187         return NULL;
 188 }
 189
 190 static void __dma_free(struct device *dev, size_t size,
 191                        void *vaddr, dma_addr_t dma_handle,
 192                        unsigned long attrs)
 193 {
 194         void *swiotlb_addr = phys_to_virt(dma_to_phys(dev, dma_handle));
 195
 196         size = PAGE_ALIGN(size);
 197
 198         if (!is_device_dma_coherent(dev)) {
 199                 if (__free_from_pool(vaddr, size))
 200                         return;
 201                 vunmap(vaddr);
 202         }
 203         __dma_free_coherent(dev, size, swiotlb_addr, dma_handle, attrs);
 204 }
 205
 206 static dma_addr_t __swiotlb_map_page(struct device *dev, struct page *page,
 207                                      unsigned long offset, size_t size,
 208                                      enum dma_data_direction dir,
 209                                      unsigned long attrs)
 210 {
 211         dma_addr_t dev_addr;
 212
 213         dev_addr = swiotlb_map_page(dev, page, offset, size, dir, attrs);
 214         if (!is_device_dma_coherent(dev) &&
 215             (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
 216                 __dma_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
 217
 218         return dev_addr;
 219 }
 220
 221
 222 static void __swiotlb_unmap_page(struct device *dev, dma_addr_t dev_addr,
 223                                  size_t size, enum dma_data_direction dir,
 224                                  unsigned long attrs)
 225 {
 226         if (!is_device_dma_coherent(dev) &&
 227             (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
 228                 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
 229         swiotlb_unmap_page(dev, dev_addr, size, dir, attrs);
 230 }
 231
 232 static int __swiotlb_map_sg_attrs(struct device *dev, struct scatterlist *sgl,
 233                                   int nelems, enum dma_data_direction dir,
 234                                   unsigned long attrs)
 235 {
 236         struct scatterlist *sg;
 237         int i, ret;
 238
 239         ret = swiotlb_map_sg_attrs(dev, sgl, nelems, dir, attrs);
 240         if (!is_device_dma_coherent(dev) &&
 241             (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
 242                 for_each_sg(sgl, sg, ret, i)
 243                         __dma_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
 244                                        sg->length, dir);
 245
 246         return ret;
 247 }
 248
 249 static void __swiotlb_unmap_sg_attrs(struct device *dev,
 250                                      struct scatterlist *sgl, int nelems,
 251                                      enum dma_data_direction dir,
 252                                      unsigned long attrs)
 253 {
 254         struct scatterlist *sg;
 255         int i;
 256
 257         if (!is_device_dma_coherent(dev) &&
 258             (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
 259                 for_each_sg(sgl, sg, nelems, i)
 260                         __dma_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
 261                                          sg->length, dir);
 262         swiotlb_unmap_sg_attrs(dev, sgl, nelems, dir, attrs);
 263 }
 264
 265 static void __swiotlb_sync_single_for_cpu(struct device *dev,
 266                                           dma_addr_t dev_addr, size_t size,
 267                                           enum dma_data_direction dir)
 268 {
 269         if (!is_device_dma_coherent(dev))
 270                 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
 271         swiotlb_sync_single_for_cpu(dev, dev_addr, size, dir);
 272 }
 273
 274 static void __swiotlb_sync_single_for_device(struct device *dev,
 275                                              dma_addr_t dev_addr, size_t size,
 276                                              enum dma_data_direction dir)
 277 {
 278         swiotlb_sync_single_for_device(dev, dev_addr, size, dir);
 279         if (!is_device_dma_coherent(dev))
 280                 __dma_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
 281 }
 282
 283 static void __swiotlb_sync_sg_for_cpu(struct device *dev,
 284                                       struct scatterlist *sgl, int nelems,
 285                                       enum dma_data_direction dir)
 286 {
 287         struct scatterlist *sg;
 288         int i;
 289
 290         if (!is_device_dma_coherent(dev))
 291                 for_each_sg(sgl, sg, nelems, i)
 292                         __dma_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
 293                                          sg->length, dir);
 294         swiotlb_sync_sg_for_cpu(dev, sgl, nelems, dir);
 295 }
 296
 297 static void __swiotlb_sync_sg_for_device(struct device *dev,
 298                                          struct scatterlist *sgl, int nelems,
 299                                          enum dma_data_direction dir)
 300 {
 301         struct scatterlist *sg;
 302         int i;
 303
 304         swiotlb_sync_sg_for_device(dev, sgl, nelems, dir);
 305         if (!is_device_dma_coherent(dev))
 306                 for_each_sg(sgl, sg, nelems, i)
 307                         __dma_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
 308                                        sg->length, dir);
 309 }
 310
 311 static int __swiotlb_mmap(struct device *dev,
 312                           struct vm_area_struct *vma,
 313                           void *cpu_addr, dma_addr_t dma_addr, size_t size,
 314                           unsigned long attrs)
 315 {
 316         int ret = -ENXIO;
 317         unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >>
 318                                         PAGE_SHIFT;
 319         unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
 320         unsigned long pfn = dma_to_phys(dev, dma_addr) >> PAGE_SHIFT;
 321         unsigned long off = vma->vm_pgoff;
 322
 323         vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot,
 324                                              is_device_dma_coherent(dev));
 325
 326         if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
 327                 return ret;
 328
 329         if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
 330                 ret = remap_pfn_range(vma, vma->vm_start,
 331                                       pfn + off,
 332                                       vma->vm_end - vma->vm_start,
 333                                       vma->vm_page_prot);
 334         }
 335
 336         return ret;
 337 }
 338
 339 static int __swiotlb_get_sgtable(struct device *dev, struct sg_table *sgt,
 340                                  void *cpu_addr, dma_addr_t handle, size_t size,
 341                                  unsigned long attrs)
 342 {
 343         int ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
 344
 345         if (!ret)
 346                 sg_set_page(sgt->sgl, phys_to_page(dma_to_phys(dev, handle)),
 347                             PAGE_ALIGN(size), 0);
 348
 349         return ret;
 350 }
 351
 352 static int __swiotlb_dma_supported(struct device *hwdev, u64 mask)
 353 {
 354         if (swiotlb)
 355                 return swiotlb_dma_supported(hwdev, mask);
 356         return 1;
 357 }
 358
 359 static struct dma_map_ops swiotlb_dma_ops = {
 360         .alloc = __dma_alloc,
 361         .free = __dma_free,
 362         .mmap = __swiotlb_mmap,
 363         .get_sgtable = __swiotlb_get_sgtable,
 364         .map_page = __swiotlb_map_page,
 365         .unmap_page = __swiotlb_unmap_page,
 366         .map_sg = __swiotlb_map_sg_attrs,
 367         .unmap_sg = __swiotlb_unmap_sg_attrs,
 368         .sync_single_for_cpu = __swiotlb_sync_single_for_cpu,
 369         .sync_single_for_device = __swiotlb_sync_single_for_device,
 370         .sync_sg_for_cpu = __swiotlb_sync_sg_for_cpu,
 371         .sync_sg_for_device = __swiotlb_sync_sg_for_device,
 372         .dma_supported = __swiotlb_dma_supported,
 373         .mapping_error = swiotlb_dma_mapping_error,
 374 };
 375
 376 static int __init atomic_pool_init(void)
 377 {
 378         pgprot_t prot = __pgprot(PROT_NORMAL_NC);
 379         unsigned long nr_pages = atomic_pool_size >> PAGE_SHIFT;
 380         struct page *page;
 381         void *addr;
 382         unsigned int pool_size_order = get_order(atomic_pool_size);
 383
 384         if (dev_get_cma_area(NULL))
 385                 page = dma_alloc_from_contiguous(NULL, nr_pages,
 386                                                         pool_size_order);
 387         else
 388                 page = alloc_pages(GFP_DMA, pool_size_order);
 389
 390         if (page) {
 391                 int ret;
 392                 void *page_addr = page_address(page);
 393
 394                 memset(page_addr, 0, atomic_pool_size);
 395                 __dma_flush_area(page_addr, atomic_pool_size);
 396
 397                 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
 398                 if (!atomic_pool)
 399                         goto free_page;
 400
 401                 addr = dma_common_contiguous_remap(page, atomic_pool_size,
 402                                         VM_USERMAP, prot, atomic_pool_init);
 403
 404                 if (!addr)
 405                         goto destroy_genpool;
 406
 407                 ret = gen_pool_add_virt(atomic_pool, (unsigned long)addr,
 408                                         page_to_phys(page),
 409                                         atomic_pool_size, -1);
 410                 if (ret)
 411                         goto remove_mapping;
 412
 413                 gen_pool_set_algo(atomic_pool,
 414                                   gen_pool_first_fit_order_align,
 415                                   (void *)PAGE_SHIFT);
 416
 417                 pr_info("DMA: preallocated %zu KiB pool for atomic allocations\n",
 418                         atomic_pool_size / 1024);
 419                 return 0;
 420         }
 421         goto out;
 422
 423 remove_mapping:
 424         dma_common_free_remap(addr, atomic_pool_size, VM_USERMAP);
 425 destroy_genpool:
 426         gen_pool_destroy(atomic_pool);
 427         atomic_pool = NULL;
 428 free_page:
 429         if (!dma_release_from_contiguous(NULL, page, nr_pages))
 430                 __free_pages(page, pool_size_order);
 431 out:
 432         pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n",
 433                 atomic_pool_size / 1024);
 434         return -ENOMEM;
 435 }
 436
 437 /********************************************
 438  * The following APIs are for dummy DMA ops *
 439  ********************************************/
 440
 441 static void *__dummy_alloc(struct device *dev, size_t size,
 442                            dma_addr_t *dma_handle, gfp_t flags,
 443                            unsigned long attrs)
 444 {
 445         return NULL;
 446 }
 447
 448 static void __dummy_free(struct device *dev, size_t size,
 449                          void *vaddr, dma_addr_t dma_handle,
 450                          unsigned long attrs)
 451 {
 452 }
 453
 454 static int __dummy_mmap(struct device *dev,
 455                         struct vm_area_struct *vma,
 456                         void *cpu_addr, dma_addr_t dma_addr, size_t size,
 457                         unsigned long attrs)
 458 {
 459         return -ENXIO;
 460 }
 461
 462 static dma_addr_t __dummy_map_page(struct device *dev, struct page *page,
 463                                    unsigned long offset, size_t size,
 464                                    enum dma_data_direction dir,
 465                                    unsigned long attrs)
 466 {
 467         return DMA_ERROR_CODE;
 468 }
 469
 470 static void __dummy_unmap_page(struct device *dev, dma_addr_t dev_addr,
 471                                size_t size, enum dma_data_direction dir,
 472                                unsigned long attrs)
 473 {
 474 }
 475
 476 static int __dummy_map_sg(struct device *dev, struct scatterlist *sgl,
 477                           int nelems, enum dma_data_direction dir,
 478                           unsigned long attrs)
 479 {
 480         return 0;
 481 }
 482
 483 static void __dummy_unmap_sg(struct device *dev,
 484                              struct scatterlist *sgl, int nelems,
 485                              enum dma_data_direction dir,
 486                              unsigned long attrs)
 487 {
 488 }
 489
 490 static void __dummy_sync_single(struct device *dev,
 491                                 dma_addr_t dev_addr, size_t size,
 492                                 enum dma_data_direction dir)
 493 {
 494 }
 495
 496 static void __dummy_sync_sg(struct device *dev,
 497                             struct scatterlist *sgl, int nelems,
 498                             enum dma_data_direction dir)
 499 {
 500 }
 501
 502 static int __dummy_mapping_error(struct device *hwdev, dma_addr_t dma_addr)
 503 {
 504         return 1;
 505 }
 506
 507 static int __dummy_dma_supported(struct device *hwdev, u64 mask)
 508 {
 509         return 0;
 510 }
 511
 512 struct dma_map_ops dummy_dma_ops = {
 513         .alloc                  = __dummy_alloc,
 514         .free                   = __dummy_free,
 515         .mmap                   = __dummy_mmap,
 516         .map_page               = __dummy_map_page,
 517         .unmap_page             = __dummy_unmap_page,
 518         .map_sg                 = __dummy_map_sg,
 519         .unmap_sg               = __dummy_unmap_sg,
 520         .sync_single_for_cpu    = __dummy_sync_single,
 521         .sync_single_for_device = __dummy_sync_single,
 522         .sync_sg_for_cpu        = __dummy_sync_sg,
 523         .sync_sg_for_device     = __dummy_sync_sg,
 524         .mapping_error          = __dummy_mapping_error,
 525         .dma_supported          = __dummy_dma_supported,
 526 };
 527 EXPORT_SYMBOL(dummy_dma_ops);
 528
 529 static int __init arm64_dma_init(void)
 530 {
 531         if (swiotlb_force == SWIOTLB_FORCE ||
 532             max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT))
 533                 swiotlb = 1;
 534
 535         return atomic_pool_init();
 536 }
 537 arch_initcall(arm64_dma_init);
 538
 539 #define PREALLOC_DMA_DEBUG_ENTRIES      4096
 540
 541 static int __init dma_debug_do_init(void)
 542 {
 543         dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
 544         return 0;
 545 }
 546 fs_initcall(dma_debug_do_init);
 547
 548
 549 #ifdef CONFIG_IOMMU_DMA
 550 #include <linux/dma-iommu.h>
 551 #include <linux/platform_device.h>
 552 #include <linux/amba/bus.h>
 553
 554 /* Thankfully, all cache ops are by VA so we can ignore phys here */
 555 static void flush_page(struct device *dev, const void *virt, phys_addr_t phys)
 556 {
 557         __dma_flush_area(virt, PAGE_SIZE);
 558 }
 559
 560 static void *__iommu_alloc_attrs(struct device *dev, size_t size,
 561                                  dma_addr_t *handle, gfp_t gfp,
 562                                  unsigned long attrs)
 563 {
 564         bool coherent = is_device_dma_coherent(dev);
 565         int ioprot = dma_direction_to_prot(DMA_BIDIRECTIONAL, coherent);
 566         size_t iosize = size;
 567         void *addr;
 568
 569         if (WARN(!dev, "cannot create IOMMU mapping for unknown device\n"))
 570                 return NULL;
 571
 572         size = PAGE_ALIGN(size);
 573
 574         /*
 575          * Some drivers rely on this, and we probably don't want the
 576          * possibility of stale kernel data being read by devices anyway.
 577          */
 578         gfp |= __GFP_ZERO;
 579
 580         if (gfpflags_allow_blocking(gfp)) {
 581                 struct page **pages;
 582                 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, coherent);
 583
 584                 pages = iommu_dma_alloc(dev, iosize, gfp, attrs, ioprot,
 585                                         handle, flush_page);
 586                 if (!pages)
 587                         return NULL;
 588
 589                 addr = dma_common_pages_remap(pages, size, VM_USERMAP, prot,
 590                                               __builtin_return_address(0));
 591                 if (!addr)
 592                         iommu_dma_free(dev, pages, iosize, handle);
 593         } else {
 594                 struct page *page;
 595                 /*
 596                  * In atomic context we can't remap anything, so we'll only
 597                  * get the virtually contiguous buffer we need by way of a
 598                  * physically contiguous allocation.
 599                  */
 600                 if (coherent) {
 601                         page = alloc_pages(gfp, get_order(size));
 602                         addr = page ? page_address(page) : NULL;
 603                 } else {
 604                         addr = __alloc_from_pool(size, &page, gfp);
 605                 }
 606                 if (!addr)
 607                         return NULL;
 608
 609                 *handle = iommu_dma_map_page(dev, page, 0, iosize, ioprot);
 610                 if (iommu_dma_mapping_error(dev, *handle)) {
 611                         if (coherent)
 612                                 __free_pages(page, get_order(size));
 613                         else
 614                                 __free_from_pool(addr, size);
 615                         addr = NULL;
 616                 }
 617         }
 618         return addr;
 619 }
 620
 621 static void __iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
 622                                dma_addr_t handle, unsigned long attrs)
 623 {
 624         size_t iosize = size;
 625
 626         size = PAGE_ALIGN(size);
 627         /*
 628          * @cpu_addr will be one of 3 things depending on how it was allocated:
 629          * - A remapped array of pages from iommu_dma_alloc(), for all
 630          *   non-atomic allocations.
 631          * - A non-cacheable alias from the atomic pool, for atomic
 632          *   allocations by non-coherent devices.
 633          * - A normal lowmem address, for atomic allocations by
 634          *   coherent devices.
 635          * Hence how dodgy the below logic looks...
 636          */
 637         if (__in_atomic_pool(cpu_addr, size)) {
 638                 iommu_dma_unmap_page(dev, handle, iosize, 0, 0);
 639                 __free_from_pool(cpu_addr, size);
 640         } else if (is_vmalloc_addr(cpu_addr)){
 641                 struct vm_struct *area = find_vm_area(cpu_addr);
 642
 643                 if (WARN_ON(!area || !area->pages))
 644                         return;
 645                 iommu_dma_free(dev, area->pages, iosize, &handle);
 646                 dma_common_free_remap(cpu_addr, size, VM_USERMAP);
 647         } else {
 648                 iommu_dma_unmap_page(dev, handle, iosize, 0, 0);
 649                 __free_pages(virt_to_page(cpu_addr), get_order(size));
 650         }
 651 }
 652
 653 static int __iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
 654                               void *cpu_addr, dma_addr_t dma_addr, size_t size,
 655                               unsigned long attrs)
 656 {
 657         struct vm_struct *area;
 658         int ret;
 659
 660         vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot,
 661                                              is_device_dma_coherent(dev));
 662
 663         if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
 664                 return ret;
 665
 666         area = find_vm_area(cpu_addr);
 667         if (WARN_ON(!area || !area->pages))
 668                 return -ENXIO;
 669
 670         return iommu_dma_mmap(area->pages, size, vma);
 671 }
 672
 673 static int __iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
 674                                void *cpu_addr, dma_addr_t dma_addr,
 675                                size_t size, unsigned long attrs)
 676 {
 677         unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
 678         struct vm_struct *area = find_vm_area(cpu_addr);
 679
 680         if (WARN_ON(!area || !area->pages))
 681                 return -ENXIO;
 682
 683         return sg_alloc_table_from_pages(sgt, area->pages, count, 0, size,
 684                                          GFP_KERNEL);
 685 }
 686
 687 static void __iommu_sync_single_for_cpu(struct device *dev,
 688                                         dma_addr_t dev_addr, size_t size,
 689                                         enum dma_data_direction dir)
 690 {
 691         phys_addr_t phys;
 692
 693         if (is_device_dma_coherent(dev))
 694                 return;
 695
 696         phys = iommu_iova_to_phys(iommu_get_domain_for_dev(dev), dev_addr);
 697         __dma_unmap_area(phys_to_virt(phys), size, dir);
 698 }
 699
 700 static void __iommu_sync_single_for_device(struct device *dev,
 701                                            dma_addr_t dev_addr, size_t size,
 702                                            enum dma_data_direction dir)
 703 {
 704         phys_addr_t phys;
 705
 706         if (is_device_dma_coherent(dev))
 707                 return;
 708
 709         phys = iommu_iova_to_phys(iommu_get_domain_for_dev(dev), dev_addr);
 710         __dma_map_area(phys_to_virt(phys), size, dir);
 711 }
 712
 713 static dma_addr_t __iommu_map_page(struct device *dev, struct page *page,
 714                                    unsigned long offset, size_t size,
 715                                    enum dma_data_direction dir,
 716                                    unsigned long attrs)
 717 {
 718         bool coherent = is_device_dma_coherent(dev);
 719         int prot = dma_direction_to_prot(dir, coherent);
 720         dma_addr_t dev_addr = iommu_dma_map_page(dev, page, offset, size, prot);
 721
 722         if (!iommu_dma_mapping_error(dev, dev_addr) &&
 723             (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
 724                 __iommu_sync_single_for_device(dev, dev_addr, size, dir);
 725
 726         return dev_addr;
 727 }
 728
 729 static void __iommu_unmap_page(struct device *dev, dma_addr_t dev_addr,
 730                                size_t size, enum dma_data_direction dir,
 731                                unsigned long attrs)
 732 {
 733         if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
 734                 __iommu_sync_single_for_cpu(dev, dev_addr, size, dir);
 735
 736         iommu_dma_unmap_page(dev, dev_addr, size, dir, attrs);
 737 }
 738
 739 static void __iommu_sync_sg_for_cpu(struct device *dev,
 740                                     struct scatterlist *sgl, int nelems,
 741                                     enum dma_data_direction dir)
 742 {
 743         struct scatterlist *sg;
 744         int i;
 745
 746         if (is_device_dma_coherent(dev))
 747                 return;
 748
 749         for_each_sg(sgl, sg, nelems, i)
 750                 __dma_unmap_area(sg_virt(sg), sg->length, dir);
 751 }
 752
 753 static void __iommu_sync_sg_for_device(struct device *dev,
 754                                        struct scatterlist *sgl, int nelems,
 755                                        enum dma_data_direction dir)
 756 {
 757         struct scatterlist *sg;
 758         int i;
 759
 760         if (is_device_dma_coherent(dev))
 761                 return;
 762
 763         for_each_sg(sgl, sg, nelems, i)
 764                 __dma_map_area(sg_virt(sg), sg->length, dir);
 765 }
 766
 767 static int __iommu_map_sg_attrs(struct device *dev, struct scatterlist *sgl,
 768                                 int nelems, enum dma_data_direction dir,
 769                                 unsigned long attrs)
 770 {
 771         bool coherent = is_device_dma_coherent(dev);
 772
 773         if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
 774                 __iommu_sync_sg_for_device(dev, sgl, nelems, dir);
 775
 776         return iommu_dma_map_sg(dev, sgl, nelems,
 777                         dma_direction_to_prot(dir, coherent));
 778 }
 779
 780 static void __iommu_unmap_sg_attrs(struct device *dev,
 781                                    struct scatterlist *sgl, int nelems,
 782                                    enum dma_data_direction dir,
 783                                    unsigned long attrs)
 784 {
 785         if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
 786                 __iommu_sync_sg_for_cpu(dev, sgl, nelems, dir);
 787
 788         iommu_dma_unmap_sg(dev, sgl, nelems, dir, attrs);
 789 }
 790
 791 static struct dma_map_ops iommu_dma_ops = {
 792         .alloc = __iommu_alloc_attrs,
 793         .free = __iommu_free_attrs,
 794         .mmap = __iommu_mmap_attrs,
 795         .get_sgtable = __iommu_get_sgtable,
 796         .map_page = __iommu_map_page,
 797         .unmap_page = __iommu_unmap_page,
 798         .map_sg = __iommu_map_sg_attrs,
 799         .unmap_sg = __iommu_unmap_sg_attrs,
 800         .sync_single_for_cpu = __iommu_sync_single_for_cpu,
 801         .sync_single_for_device = __iommu_sync_single_for_device,
 802         .sync_sg_for_cpu = __iommu_sync_sg_for_cpu,
 803         .sync_sg_for_device = __iommu_sync_sg_for_device,
 804         .map_resource = iommu_dma_map_resource,
 805         .unmap_resource = iommu_dma_unmap_resource,
 806         .dma_supported = iommu_dma_supported,
 807         .mapping_error = iommu_dma_mapping_error,
 808 };
 809
 810 /*
 811  * TODO: Right now __iommu_setup_dma_ops() gets called too early to do
 812  * everything it needs to - the device is only partially created and the
 813  * IOMMU driver hasn't seen it yet, so it can't have a group. Thus we
 814  * need this delayed attachment dance. Once IOMMU probe ordering is sorted
 815  * to move the arch_setup_dma_ops() call later, all the notifier bits below
 816  * become unnecessary, and will go away.
 817  */
 818 struct iommu_dma_notifier_data {
 819         struct list_head list;
 820         struct device *dev;
 821         const struct iommu_ops *ops;
 822         u64 dma_base;
 823         u64 size;
 824 };
 825 static LIST_HEAD(iommu_dma_masters);
 826 static DEFINE_MUTEX(iommu_dma_notifier_lock);
 827
 828 static bool do_iommu_attach(struct device *dev, const struct iommu_ops *ops,
 829                            u64 dma_base, u64 size)
 830 {
 831         struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
 832
 833         /*
 834          * If the IOMMU driver has the DMA domain support that we require,
 835          * then the IOMMU core will have already configured a group for this
 836          * device, and allocated the default domain for that group.
 837          */
 838         if (!domain)
 839                 goto out_err;
 840
 841         if (domain->type == IOMMU_DOMAIN_DMA) {
 842                 if (iommu_dma_init_domain(domain, dma_base, size, dev))
 843                         goto out_err;
 844
 845                 dev->archdata.dma_ops = &iommu_dma_ops;
 846         }
 847
 848         return true;
 849 out_err:
 850         pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
 851                  dev_name(dev));
 852         return false;
 853 }
 854
 855 static void queue_iommu_attach(struct device *dev, const struct iommu_ops *ops,
 856                               u64 dma_base, u64 size)
 857 {
 858         struct iommu_dma_notifier_data *iommudata;
 859
 860         iommudata = kzalloc(sizeof(*iommudata), GFP_KERNEL);
 861         if (!iommudata)
 862                 return;
 863
 864         iommudata->dev = dev;
 865         iommudata->ops = ops;
 866         iommudata->dma_base = dma_base;
 867         iommudata->size = size;
 868
 869         mutex_lock(&iommu_dma_notifier_lock);
 870         list_add(&iommudata->list, &iommu_dma_masters);
 871         mutex_unlock(&iommu_dma_notifier_lock);
 872 }
 873
 874 static int __iommu_attach_notifier(struct notifier_block *nb,
 875                                    unsigned long action, void *data)
 876 {
 877         struct iommu_dma_notifier_data *master, *tmp;
 878
 879         if (action != BUS_NOTIFY_BIND_DRIVER)
 880                 return 0;
 881
 882         mutex_lock(&iommu_dma_notifier_lock);
 883         list_for_each_entry_safe(master, tmp, &iommu_dma_masters, list) {
 884                 if (data == master->dev && do_iommu_attach(master->dev,
 885                                 master->ops, master->dma_base, master->size)) {
 886                         list_del(&master->list);
 887                         kfree(master);
 888                         break;
 889                 }
 890         }
 891         mutex_unlock(&iommu_dma_notifier_lock);
 892         return 0;
 893 }
 894
 895 static int __init register_iommu_dma_ops_notifier(struct bus_type *bus)
 896 {
 897         struct notifier_block *nb = kzalloc(sizeof(*nb), GFP_KERNEL);
 898         int ret;
 899
 900         if (!nb)
 901                 return -ENOMEM;
 902
 903         nb->notifier_call = __iommu_attach_notifier;
 904
 905         ret = bus_register_notifier(bus, nb);
 906         if (ret) {
 907                 pr_warn("Failed to register DMA domain notifier; IOMMU DMA ops unavailable on bus '%s'\n",
 908                         bus->name);
 909                 kfree(nb);
 910         }
 911         return ret;
 912 }
 913
 914 static int __init __iommu_dma_init(void)
 915 {
 916         int ret;
 917
 918         ret = iommu_dma_init();
 919         if (!ret)
 920                 ret = register_iommu_dma_ops_notifier(&platform_bus_type);
 921         if (!ret)
 922                 ret = register_iommu_dma_ops_notifier(&amba_bustype);
 923 #ifdef CONFIG_PCI
 924         if (!ret)
 925                 ret = register_iommu_dma_ops_notifier(&pci_bus_type);
 926 #endif
 927         return ret;
 928 }
 929 arch_initcall(__iommu_dma_init);
 930
 931 static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 932                                   const struct iommu_ops *ops)
 933 {
 934         struct iommu_group *group;
 935
 936         if (!ops)
 937                 return;
 938         /*
 939          * TODO: As a concession to the future, we're ready to handle being
 940          * called both early and late (i.e. after bus_add_device). Once all
 941          * the platform bus code is reworked to call us late and the notifier
 942          * junk above goes away, move the body of do_iommu_attach here.
 943          */
 944         group = iommu_group_get(dev);
 945         if (group) {
 946                 do_iommu_attach(dev, ops, dma_base, size);
 947                 iommu_group_put(group);
 948         } else {
 949                 queue_iommu_attach(dev, ops, dma_base, size);
 950         }
 951 }
 952
 953 void arch_teardown_dma_ops(struct device *dev)
 954 {
 955         dev->archdata.dma_ops = NULL;
 956 }
 957
 958 #else
 959
 960 static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 961                                   const struct iommu_ops *iommu)
 962 { }
 963
 964 #endif  /* CONFIG_IOMMU_DMA */
 965
 966 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 967                         const struct iommu_ops *iommu, bool coherent)
 968 {
 969         if (!dev->archdata.dma_ops)
 970                 dev->archdata.dma_ops = &swiotlb_dma_ops;
 971
 972         dev->archdata.dma_coherent = coherent;
 973         __iommu_setup_dma_ops(dev, dma_base, size, iommu);
 974 }