2 * SWIOTLB-based DMA API implementation
4 * Copyright (C) 2012 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/gfp.h>
21 #include <linux/acpi.h>
22 #include <linux/bootmem.h>
23 #include <linux/cache.h>
24 #include <linux/export.h>
25 #include <linux/slab.h>
26 #include <linux/genalloc.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dma-contiguous.h>
29 #include <linux/vmalloc.h>
30 #include <linux/swiotlb.h>
32 #include <asm/cacheflush.h>
34 static int swiotlb __ro_after_init;
36 static pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot,
39 if (!coherent || (attrs & DMA_ATTR_WRITE_COMBINE))
40 return pgprot_writecombine(prot);
44 static struct gen_pool *atomic_pool;
46 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
47 static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
49 static int __init early_coherent_pool(char *p)
51 atomic_pool_size = memparse(p, &p);
54 early_param("coherent_pool", early_coherent_pool);
56 static void *__alloc_from_pool(size_t size, struct page **ret_page, gfp_t flags)
62 WARN(1, "coherent pool not initialised!\n");
66 val = gen_pool_alloc(atomic_pool, size);
68 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
70 *ret_page = phys_to_page(phys);
78 static bool __in_atomic_pool(void *start, size_t size)
80 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
83 static int __free_from_pool(void *start, size_t size)
85 if (!__in_atomic_pool(start, size))
88 gen_pool_free(atomic_pool, (unsigned long)start, size);
93 static void *__dma_alloc_coherent(struct device *dev, size_t size,
94 dma_addr_t *dma_handle, gfp_t flags,
98 WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
102 if (IS_ENABLED(CONFIG_ZONE_DMA) &&
103 dev->coherent_dma_mask <= DMA_BIT_MASK(32))
105 if (dev_get_cma_area(dev) && gfpflags_allow_blocking(flags)) {
109 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
110 get_order(size), flags);
114 *dma_handle = phys_to_dma(dev, page_to_phys(page));
115 addr = page_address(page);
116 memset(addr, 0, size);
119 return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
123 static void __dma_free_coherent(struct device *dev, size_t size,
124 void *vaddr, dma_addr_t dma_handle,
128 phys_addr_t paddr = dma_to_phys(dev, dma_handle);
131 WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
135 freed = dma_release_from_contiguous(dev,
139 swiotlb_free_coherent(dev, size, vaddr, dma_handle);
142 static void *__dma_alloc(struct device *dev, size_t size,
143 dma_addr_t *dma_handle, gfp_t flags,
147 void *ptr, *coherent_ptr;
148 bool coherent = is_device_dma_coherent(dev);
149 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, false);
151 size = PAGE_ALIGN(size);
153 if (!coherent && !gfpflags_allow_blocking(flags)) {
154 struct page *page = NULL;
155 void *addr = __alloc_from_pool(size, &page, flags);
158 *dma_handle = phys_to_dma(dev, page_to_phys(page));
163 ptr = __dma_alloc_coherent(dev, size, dma_handle, flags, attrs);
167 /* no need for non-cacheable mapping if coherent */
171 /* remove any dirty cache lines on the kernel alias */
172 __dma_flush_area(ptr, size);
174 /* create a coherent mapping */
175 page = virt_to_page(ptr);
176 coherent_ptr = dma_common_contiguous_remap(page, size, VM_USERMAP,
184 __dma_free_coherent(dev, size, ptr, *dma_handle, attrs);
186 *dma_handle = DMA_ERROR_CODE;
190 static void __dma_free(struct device *dev, size_t size,
191 void *vaddr, dma_addr_t dma_handle,
194 void *swiotlb_addr = phys_to_virt(dma_to_phys(dev, dma_handle));
196 size = PAGE_ALIGN(size);
198 if (!is_device_dma_coherent(dev)) {
199 if (__free_from_pool(vaddr, size))
203 __dma_free_coherent(dev, size, swiotlb_addr, dma_handle, attrs);
206 static dma_addr_t __swiotlb_map_page(struct device *dev, struct page *page,
207 unsigned long offset, size_t size,
208 enum dma_data_direction dir,
213 dev_addr = swiotlb_map_page(dev, page, offset, size, dir, attrs);
214 if (!is_device_dma_coherent(dev) &&
215 (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
216 __dma_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
222 static void __swiotlb_unmap_page(struct device *dev, dma_addr_t dev_addr,
223 size_t size, enum dma_data_direction dir,
226 if (!is_device_dma_coherent(dev) &&
227 (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
228 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
229 swiotlb_unmap_page(dev, dev_addr, size, dir, attrs);
232 static int __swiotlb_map_sg_attrs(struct device *dev, struct scatterlist *sgl,
233 int nelems, enum dma_data_direction dir,
236 struct scatterlist *sg;
239 ret = swiotlb_map_sg_attrs(dev, sgl, nelems, dir, attrs);
240 if (!is_device_dma_coherent(dev) &&
241 (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
242 for_each_sg(sgl, sg, ret, i)
243 __dma_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
249 static void __swiotlb_unmap_sg_attrs(struct device *dev,
250 struct scatterlist *sgl, int nelems,
251 enum dma_data_direction dir,
254 struct scatterlist *sg;
257 if (!is_device_dma_coherent(dev) &&
258 (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
259 for_each_sg(sgl, sg, nelems, i)
260 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
262 swiotlb_unmap_sg_attrs(dev, sgl, nelems, dir, attrs);
265 static void __swiotlb_sync_single_for_cpu(struct device *dev,
266 dma_addr_t dev_addr, size_t size,
267 enum dma_data_direction dir)
269 if (!is_device_dma_coherent(dev))
270 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
271 swiotlb_sync_single_for_cpu(dev, dev_addr, size, dir);
274 static void __swiotlb_sync_single_for_device(struct device *dev,
275 dma_addr_t dev_addr, size_t size,
276 enum dma_data_direction dir)
278 swiotlb_sync_single_for_device(dev, dev_addr, size, dir);
279 if (!is_device_dma_coherent(dev))
280 __dma_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
283 static void __swiotlb_sync_sg_for_cpu(struct device *dev,
284 struct scatterlist *sgl, int nelems,
285 enum dma_data_direction dir)
287 struct scatterlist *sg;
290 if (!is_device_dma_coherent(dev))
291 for_each_sg(sgl, sg, nelems, i)
292 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
294 swiotlb_sync_sg_for_cpu(dev, sgl, nelems, dir);
297 static void __swiotlb_sync_sg_for_device(struct device *dev,
298 struct scatterlist *sgl, int nelems,
299 enum dma_data_direction dir)
301 struct scatterlist *sg;
304 swiotlb_sync_sg_for_device(dev, sgl, nelems, dir);
305 if (!is_device_dma_coherent(dev))
306 for_each_sg(sgl, sg, nelems, i)
307 __dma_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
311 static int __swiotlb_mmap_pfn(struct vm_area_struct *vma,
312 unsigned long pfn, size_t size)
315 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >>
317 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
318 unsigned long off = vma->vm_pgoff;
320 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
321 ret = remap_pfn_range(vma, vma->vm_start,
323 vma->vm_end - vma->vm_start,
330 static int __swiotlb_mmap(struct device *dev,
331 struct vm_area_struct *vma,
332 void *cpu_addr, dma_addr_t dma_addr, size_t size,
336 unsigned long pfn = dma_to_phys(dev, dma_addr) >> PAGE_SHIFT;
338 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot,
339 is_device_dma_coherent(dev));
341 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
344 return __swiotlb_mmap_pfn(vma, pfn, size);
347 static int __swiotlb_get_sgtable_page(struct sg_table *sgt,
348 struct page *page, size_t size)
350 int ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
353 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
358 static int __swiotlb_get_sgtable(struct device *dev, struct sg_table *sgt,
359 void *cpu_addr, dma_addr_t handle, size_t size,
362 struct page *page = phys_to_page(dma_to_phys(dev, handle));
364 return __swiotlb_get_sgtable_page(sgt, page, size);
367 static int __swiotlb_dma_supported(struct device *hwdev, u64 mask)
370 return swiotlb_dma_supported(hwdev, mask);
374 static int __swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t addr)
377 return swiotlb_dma_mapping_error(hwdev, addr);
381 static const struct dma_map_ops swiotlb_dma_ops = {
382 .alloc = __dma_alloc,
384 .mmap = __swiotlb_mmap,
385 .get_sgtable = __swiotlb_get_sgtable,
386 .map_page = __swiotlb_map_page,
387 .unmap_page = __swiotlb_unmap_page,
388 .map_sg = __swiotlb_map_sg_attrs,
389 .unmap_sg = __swiotlb_unmap_sg_attrs,
390 .sync_single_for_cpu = __swiotlb_sync_single_for_cpu,
391 .sync_single_for_device = __swiotlb_sync_single_for_device,
392 .sync_sg_for_cpu = __swiotlb_sync_sg_for_cpu,
393 .sync_sg_for_device = __swiotlb_sync_sg_for_device,
394 .dma_supported = __swiotlb_dma_supported,
395 .mapping_error = __swiotlb_dma_mapping_error,
398 static int __init atomic_pool_init(void)
400 pgprot_t prot = __pgprot(PROT_NORMAL_NC);
401 unsigned long nr_pages = atomic_pool_size >> PAGE_SHIFT;
404 unsigned int pool_size_order = get_order(atomic_pool_size);
406 if (dev_get_cma_area(NULL))
407 page = dma_alloc_from_contiguous(NULL, nr_pages,
408 pool_size_order, GFP_KERNEL);
410 page = alloc_pages(GFP_DMA, pool_size_order);
414 void *page_addr = page_address(page);
416 memset(page_addr, 0, atomic_pool_size);
417 __dma_flush_area(page_addr, atomic_pool_size);
419 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
423 addr = dma_common_contiguous_remap(page, atomic_pool_size,
424 VM_USERMAP, prot, atomic_pool_init);
427 goto destroy_genpool;
429 ret = gen_pool_add_virt(atomic_pool, (unsigned long)addr,
431 atomic_pool_size, -1);
435 gen_pool_set_algo(atomic_pool,
436 gen_pool_first_fit_order_align,
439 pr_info("DMA: preallocated %zu KiB pool for atomic allocations\n",
440 atomic_pool_size / 1024);
446 dma_common_free_remap(addr, atomic_pool_size, VM_USERMAP);
448 gen_pool_destroy(atomic_pool);
451 if (!dma_release_from_contiguous(NULL, page, nr_pages))
452 __free_pages(page, pool_size_order);
454 pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n",
455 atomic_pool_size / 1024);
459 /********************************************
460 * The following APIs are for dummy DMA ops *
461 ********************************************/
463 static void *__dummy_alloc(struct device *dev, size_t size,
464 dma_addr_t *dma_handle, gfp_t flags,
470 static void __dummy_free(struct device *dev, size_t size,
471 void *vaddr, dma_addr_t dma_handle,
476 static int __dummy_mmap(struct device *dev,
477 struct vm_area_struct *vma,
478 void *cpu_addr, dma_addr_t dma_addr, size_t size,
484 static dma_addr_t __dummy_map_page(struct device *dev, struct page *page,
485 unsigned long offset, size_t size,
486 enum dma_data_direction dir,
489 return DMA_ERROR_CODE;
492 static void __dummy_unmap_page(struct device *dev, dma_addr_t dev_addr,
493 size_t size, enum dma_data_direction dir,
498 static int __dummy_map_sg(struct device *dev, struct scatterlist *sgl,
499 int nelems, enum dma_data_direction dir,
505 static void __dummy_unmap_sg(struct device *dev,
506 struct scatterlist *sgl, int nelems,
507 enum dma_data_direction dir,
512 static void __dummy_sync_single(struct device *dev,
513 dma_addr_t dev_addr, size_t size,
514 enum dma_data_direction dir)
518 static void __dummy_sync_sg(struct device *dev,
519 struct scatterlist *sgl, int nelems,
520 enum dma_data_direction dir)
524 static int __dummy_mapping_error(struct device *hwdev, dma_addr_t dma_addr)
529 static int __dummy_dma_supported(struct device *hwdev, u64 mask)
534 const struct dma_map_ops dummy_dma_ops = {
535 .alloc = __dummy_alloc,
536 .free = __dummy_free,
537 .mmap = __dummy_mmap,
538 .map_page = __dummy_map_page,
539 .unmap_page = __dummy_unmap_page,
540 .map_sg = __dummy_map_sg,
541 .unmap_sg = __dummy_unmap_sg,
542 .sync_single_for_cpu = __dummy_sync_single,
543 .sync_single_for_device = __dummy_sync_single,
544 .sync_sg_for_cpu = __dummy_sync_sg,
545 .sync_sg_for_device = __dummy_sync_sg,
546 .mapping_error = __dummy_mapping_error,
547 .dma_supported = __dummy_dma_supported,
549 EXPORT_SYMBOL(dummy_dma_ops);
551 static int __init arm64_dma_init(void)
553 if (swiotlb_force == SWIOTLB_FORCE ||
554 max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT))
557 return atomic_pool_init();
559 arch_initcall(arm64_dma_init);
561 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
563 static int __init dma_debug_do_init(void)
565 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
568 fs_initcall(dma_debug_do_init);
571 #ifdef CONFIG_IOMMU_DMA
572 #include <linux/dma-iommu.h>
573 #include <linux/platform_device.h>
574 #include <linux/amba/bus.h>
576 /* Thankfully, all cache ops are by VA so we can ignore phys here */
577 static void flush_page(struct device *dev, const void *virt, phys_addr_t phys)
579 __dma_flush_area(virt, PAGE_SIZE);
582 static void *__iommu_alloc_attrs(struct device *dev, size_t size,
583 dma_addr_t *handle, gfp_t gfp,
586 bool coherent = is_device_dma_coherent(dev);
587 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
588 size_t iosize = size;
591 if (WARN(!dev, "cannot create IOMMU mapping for unknown device\n"))
594 size = PAGE_ALIGN(size);
597 * Some drivers rely on this, and we probably don't want the
598 * possibility of stale kernel data being read by devices anyway.
602 if (!gfpflags_allow_blocking(gfp)) {
605 * In atomic context we can't remap anything, so we'll only
606 * get the virtually contiguous buffer we need by way of a
607 * physically contiguous allocation.
610 page = alloc_pages(gfp, get_order(size));
611 addr = page ? page_address(page) : NULL;
613 addr = __alloc_from_pool(size, &page, gfp);
618 *handle = iommu_dma_map_page(dev, page, 0, iosize, ioprot);
619 if (iommu_dma_mapping_error(dev, *handle)) {
621 __free_pages(page, get_order(size));
623 __free_from_pool(addr, size);
626 } else if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
627 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, coherent);
630 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
631 get_order(size), gfp);
635 *handle = iommu_dma_map_page(dev, page, 0, iosize, ioprot);
636 if (iommu_dma_mapping_error(dev, *handle)) {
637 dma_release_from_contiguous(dev, page,
642 __dma_flush_area(page_to_virt(page), iosize);
644 addr = dma_common_contiguous_remap(page, size, VM_USERMAP,
646 __builtin_return_address(0));
648 iommu_dma_unmap_page(dev, *handle, iosize, 0, attrs);
649 dma_release_from_contiguous(dev, page,
653 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, coherent);
656 pages = iommu_dma_alloc(dev, iosize, gfp, attrs, ioprot,
661 addr = dma_common_pages_remap(pages, size, VM_USERMAP, prot,
662 __builtin_return_address(0));
664 iommu_dma_free(dev, pages, iosize, handle);
669 static void __iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
670 dma_addr_t handle, unsigned long attrs)
672 size_t iosize = size;
674 size = PAGE_ALIGN(size);
676 * @cpu_addr will be one of 4 things depending on how it was allocated:
677 * - A remapped array of pages for contiguous allocations.
678 * - A remapped array of pages from iommu_dma_alloc(), for all
679 * non-atomic allocations.
680 * - A non-cacheable alias from the atomic pool, for atomic
681 * allocations by non-coherent devices.
682 * - A normal lowmem address, for atomic allocations by
684 * Hence how dodgy the below logic looks...
686 if (__in_atomic_pool(cpu_addr, size)) {
687 iommu_dma_unmap_page(dev, handle, iosize, 0, 0);
688 __free_from_pool(cpu_addr, size);
689 } else if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
690 struct page *page = vmalloc_to_page(cpu_addr);
692 iommu_dma_unmap_page(dev, handle, iosize, 0, attrs);
693 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
694 dma_common_free_remap(cpu_addr, size, VM_USERMAP);
695 } else if (is_vmalloc_addr(cpu_addr)){
696 struct vm_struct *area = find_vm_area(cpu_addr);
698 if (WARN_ON(!area || !area->pages))
700 iommu_dma_free(dev, area->pages, iosize, &handle);
701 dma_common_free_remap(cpu_addr, size, VM_USERMAP);
703 iommu_dma_unmap_page(dev, handle, iosize, 0, 0);
704 __free_pages(virt_to_page(cpu_addr), get_order(size));
708 static int __iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
709 void *cpu_addr, dma_addr_t dma_addr, size_t size,
712 struct vm_struct *area;
715 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot,
716 is_device_dma_coherent(dev));
718 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
721 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
723 * DMA_ATTR_FORCE_CONTIGUOUS allocations are always remapped,
724 * hence in the vmalloc space.
726 unsigned long pfn = vmalloc_to_pfn(cpu_addr);
727 return __swiotlb_mmap_pfn(vma, pfn, size);
730 area = find_vm_area(cpu_addr);
731 if (WARN_ON(!area || !area->pages))
734 return iommu_dma_mmap(area->pages, size, vma);
737 static int __iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
738 void *cpu_addr, dma_addr_t dma_addr,
739 size_t size, unsigned long attrs)
741 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
742 struct vm_struct *area = find_vm_area(cpu_addr);
744 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
746 * DMA_ATTR_FORCE_CONTIGUOUS allocations are always remapped,
747 * hence in the vmalloc space.
749 struct page *page = vmalloc_to_page(cpu_addr);
750 return __swiotlb_get_sgtable_page(sgt, page, size);
753 if (WARN_ON(!area || !area->pages))
756 return sg_alloc_table_from_pages(sgt, area->pages, count, 0, size,
760 static void __iommu_sync_single_for_cpu(struct device *dev,
761 dma_addr_t dev_addr, size_t size,
762 enum dma_data_direction dir)
766 if (is_device_dma_coherent(dev))
769 phys = iommu_iova_to_phys(iommu_get_domain_for_dev(dev), dev_addr);
770 __dma_unmap_area(phys_to_virt(phys), size, dir);
773 static void __iommu_sync_single_for_device(struct device *dev,
774 dma_addr_t dev_addr, size_t size,
775 enum dma_data_direction dir)
779 if (is_device_dma_coherent(dev))
782 phys = iommu_iova_to_phys(iommu_get_domain_for_dev(dev), dev_addr);
783 __dma_map_area(phys_to_virt(phys), size, dir);
786 static dma_addr_t __iommu_map_page(struct device *dev, struct page *page,
787 unsigned long offset, size_t size,
788 enum dma_data_direction dir,
791 bool coherent = is_device_dma_coherent(dev);
792 int prot = dma_info_to_prot(dir, coherent, attrs);
793 dma_addr_t dev_addr = iommu_dma_map_page(dev, page, offset, size, prot);
795 if (!iommu_dma_mapping_error(dev, dev_addr) &&
796 (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
797 __iommu_sync_single_for_device(dev, dev_addr, size, dir);
802 static void __iommu_unmap_page(struct device *dev, dma_addr_t dev_addr,
803 size_t size, enum dma_data_direction dir,
806 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
807 __iommu_sync_single_for_cpu(dev, dev_addr, size, dir);
809 iommu_dma_unmap_page(dev, dev_addr, size, dir, attrs);
812 static void __iommu_sync_sg_for_cpu(struct device *dev,
813 struct scatterlist *sgl, int nelems,
814 enum dma_data_direction dir)
816 struct scatterlist *sg;
819 if (is_device_dma_coherent(dev))
822 for_each_sg(sgl, sg, nelems, i)
823 __dma_unmap_area(sg_virt(sg), sg->length, dir);
826 static void __iommu_sync_sg_for_device(struct device *dev,
827 struct scatterlist *sgl, int nelems,
828 enum dma_data_direction dir)
830 struct scatterlist *sg;
833 if (is_device_dma_coherent(dev))
836 for_each_sg(sgl, sg, nelems, i)
837 __dma_map_area(sg_virt(sg), sg->length, dir);
840 static int __iommu_map_sg_attrs(struct device *dev, struct scatterlist *sgl,
841 int nelems, enum dma_data_direction dir,
844 bool coherent = is_device_dma_coherent(dev);
846 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
847 __iommu_sync_sg_for_device(dev, sgl, nelems, dir);
849 return iommu_dma_map_sg(dev, sgl, nelems,
850 dma_info_to_prot(dir, coherent, attrs));
853 static void __iommu_unmap_sg_attrs(struct device *dev,
854 struct scatterlist *sgl, int nelems,
855 enum dma_data_direction dir,
858 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
859 __iommu_sync_sg_for_cpu(dev, sgl, nelems, dir);
861 iommu_dma_unmap_sg(dev, sgl, nelems, dir, attrs);
864 static const struct dma_map_ops iommu_dma_ops = {
865 .alloc = __iommu_alloc_attrs,
866 .free = __iommu_free_attrs,
867 .mmap = __iommu_mmap_attrs,
868 .get_sgtable = __iommu_get_sgtable,
869 .map_page = __iommu_map_page,
870 .unmap_page = __iommu_unmap_page,
871 .map_sg = __iommu_map_sg_attrs,
872 .unmap_sg = __iommu_unmap_sg_attrs,
873 .sync_single_for_cpu = __iommu_sync_single_for_cpu,
874 .sync_single_for_device = __iommu_sync_single_for_device,
875 .sync_sg_for_cpu = __iommu_sync_sg_for_cpu,
876 .sync_sg_for_device = __iommu_sync_sg_for_device,
877 .map_resource = iommu_dma_map_resource,
878 .unmap_resource = iommu_dma_unmap_resource,
879 .mapping_error = iommu_dma_mapping_error,
883 * TODO: Right now __iommu_setup_dma_ops() gets called too early to do
884 * everything it needs to - the device is only partially created and the
885 * IOMMU driver hasn't seen it yet, so it can't have a group. Thus we
886 * need this delayed attachment dance. Once IOMMU probe ordering is sorted
887 * to move the arch_setup_dma_ops() call later, all the notifier bits below
888 * become unnecessary, and will go away.
890 struct iommu_dma_notifier_data {
891 struct list_head list;
893 const struct iommu_ops *ops;
897 static LIST_HEAD(iommu_dma_masters);
898 static DEFINE_MUTEX(iommu_dma_notifier_lock);
900 static bool do_iommu_attach(struct device *dev, const struct iommu_ops *ops,
901 u64 dma_base, u64 size)
903 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
906 * If the IOMMU driver has the DMA domain support that we require,
907 * then the IOMMU core will have already configured a group for this
908 * device, and allocated the default domain for that group.
913 if (domain->type == IOMMU_DOMAIN_DMA) {
914 if (iommu_dma_init_domain(domain, dma_base, size, dev))
917 dev->dma_ops = &iommu_dma_ops;
922 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
927 static void queue_iommu_attach(struct device *dev, const struct iommu_ops *ops,
928 u64 dma_base, u64 size)
930 struct iommu_dma_notifier_data *iommudata;
932 iommudata = kzalloc(sizeof(*iommudata), GFP_KERNEL);
936 iommudata->dev = dev;
937 iommudata->ops = ops;
938 iommudata->dma_base = dma_base;
939 iommudata->size = size;
941 mutex_lock(&iommu_dma_notifier_lock);
942 list_add(&iommudata->list, &iommu_dma_masters);
943 mutex_unlock(&iommu_dma_notifier_lock);
946 static int __iommu_attach_notifier(struct notifier_block *nb,
947 unsigned long action, void *data)
949 struct iommu_dma_notifier_data *master, *tmp;
951 if (action != BUS_NOTIFY_BIND_DRIVER)
954 mutex_lock(&iommu_dma_notifier_lock);
955 list_for_each_entry_safe(master, tmp, &iommu_dma_masters, list) {
956 if (data == master->dev && do_iommu_attach(master->dev,
957 master->ops, master->dma_base, master->size)) {
958 list_del(&master->list);
963 mutex_unlock(&iommu_dma_notifier_lock);
967 static int __init register_iommu_dma_ops_notifier(struct bus_type *bus)
969 struct notifier_block *nb = kzalloc(sizeof(*nb), GFP_KERNEL);
975 nb->notifier_call = __iommu_attach_notifier;
977 ret = bus_register_notifier(bus, nb);
979 pr_warn("Failed to register DMA domain notifier; IOMMU DMA ops unavailable on bus '%s'\n",
986 static int __init __iommu_dma_init(void)
990 ret = iommu_dma_init();
992 ret = register_iommu_dma_ops_notifier(&platform_bus_type);
994 ret = register_iommu_dma_ops_notifier(&amba_bustype);
997 ret = register_iommu_dma_ops_notifier(&pci_bus_type);
1001 arch_initcall(__iommu_dma_init);
1003 static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
1004 const struct iommu_ops *ops)
1006 struct iommu_group *group;
1011 * TODO: As a concession to the future, we're ready to handle being
1012 * called both early and late (i.e. after bus_add_device). Once all
1013 * the platform bus code is reworked to call us late and the notifier
1014 * junk above goes away, move the body of do_iommu_attach here.
1016 group = iommu_group_get(dev);
1018 do_iommu_attach(dev, ops, dma_base, size);
1019 iommu_group_put(group);
1021 queue_iommu_attach(dev, ops, dma_base, size);
1025 void arch_teardown_dma_ops(struct device *dev)
1027 dev->dma_ops = NULL;
1032 static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
1033 const struct iommu_ops *iommu)
1036 #endif /* CONFIG_IOMMU_DMA */
1038 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
1039 const struct iommu_ops *iommu, bool coherent)
1042 dev->dma_ops = &swiotlb_dma_ops;
1044 dev->archdata.dma_coherent = coherent;
1045 __iommu_setup_dma_ops(dev, dma_base, size, iommu);
1048 if (xen_initial_domain()) {
1049 dev->archdata.dev_dma_ops = dev->dma_ops;
1050 dev->dma_ops = xen_dma_ops;