11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
27 select HAVE_KERNEL_GZIP if RAMKERNEL
28 select HAVE_KERNEL_BZIP2 if RAMKERNEL
29 select HAVE_KERNEL_LZMA if RAMKERNEL
30 select HAVE_KERNEL_LZO if RAMKERNEL
32 select ARCH_WANT_OPTIONAL_GPIOLIB
33 select HAVE_GENERIC_HARDIRQS
34 select GENERIC_IRQ_PROBE
35 select IRQ_PER_CPU if SMP
47 config GENERIC_FIND_NEXT_BIT
53 config FORCE_MAX_ZONEORDER
57 config GENERIC_CALIBRATE_DELAY
60 config LOCKDEP_SUPPORT
63 config STACKTRACE_SUPPORT
66 config TRACE_IRQFLAGS_SUPPORT
71 source "kernel/Kconfig.preempt"
73 source "kernel/Kconfig.freezer"
75 menu "Blackfin Processor Options"
77 comment "Processor and Board Settings"
86 BF512 Processor Support.
91 BF514 Processor Support.
96 BF516 Processor Support.
101 BF518 Processor Support.
106 BF522 Processor Support.
111 BF523 Processor Support.
116 BF524 Processor Support.
121 BF525 Processor Support.
126 BF526 Processor Support.
131 BF527 Processor Support.
136 BF531 Processor Support.
141 BF532 Processor Support.
146 BF533 Processor Support.
151 BF534 Processor Support.
156 BF536 Processor Support.
161 BF537 Processor Support.
166 BF538 Processor Support.
171 BF539 Processor Support.
176 BF542 Processor Support.
181 BF542 Processor Support.
186 BF544 Processor Support.
191 BF544 Processor Support.
196 BF547 Processor Support.
201 BF547 Processor Support.
206 BF548 Processor Support.
211 BF548 Processor Support.
216 BF549 Processor Support.
221 BF549 Processor Support.
226 BF561 Processor Support.
232 select TICKSOURCE_CORETMR
233 bool "Symmetric multi-processing support"
235 This enables support for systems with more than one CPU,
236 like the dual core BF561. If you have a system with only one
237 CPU, say N. If you have a system with more than one CPU, say Y.
239 If you don't know what to do here, say N.
247 bool "Support for hot-pluggable CPUs"
248 depends on SMP && HOTPLUG
251 config HAVE_LEGACY_PER_CPU_AREA
257 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
258 default 2 if (BF537 || BF536 || BF534)
259 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
260 default 4 if (BF538 || BF539)
264 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
265 default 3 if (BF537 || BF536 || BF534 || BF54xM)
266 default 5 if (BF561 || BF538 || BF539)
267 default 6 if (BF533 || BF532 || BF531)
271 default BF_REV_0_0 if (BF51x || BF52x)
272 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
273 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
277 depends on (BF51x || BF52x || (BF54x && !BF54xM))
281 depends on (BF51x || BF52x || (BF54x && !BF54xM))
285 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
289 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
293 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
297 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
301 depends on (BF533 || BF532 || BF531)
313 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
316 config MEM_MT48LC64M4A2FB_7E
318 depends on (BFIN533_STAMP)
321 config MEM_MT48LC16M16A2TG_75
323 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
324 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
325 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
326 || BFIN527_BLUETECHNIX_CM)
329 config MEM_MT48LC32M8A2_75
331 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
334 config MEM_MT48LC8M32B2B5_7
336 depends on (BFIN561_BLUETECHNIX_CM)
339 config MEM_MT48LC32M16A2TG_75
341 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
344 config MEM_MT48H32M16LFCJ_75
346 depends on (BFIN526_EZBRD)
349 source "arch/blackfin/mach-bf518/Kconfig"
350 source "arch/blackfin/mach-bf527/Kconfig"
351 source "arch/blackfin/mach-bf533/Kconfig"
352 source "arch/blackfin/mach-bf561/Kconfig"
353 source "arch/blackfin/mach-bf537/Kconfig"
354 source "arch/blackfin/mach-bf538/Kconfig"
355 source "arch/blackfin/mach-bf548/Kconfig"
357 menu "Board customizations"
360 bool "Default bootloader kernel arguments"
363 string "Initial kernel command string"
364 depends on CMDLINE_BOOL
365 default "console=ttyBF0,57600"
367 If you don't have a boot loader capable of passing a command line string
368 to the kernel, you may specify one here. As a minimum, you should specify
369 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
372 hex "Kernel load address for booting"
374 range 0x1000 0x20000000
376 This option allows you to set the load address of the kernel.
377 This can be useful if you are on a board which has a small amount
378 of memory or you wish to reserve some memory at the beginning of
381 Note that you need to keep this value above 4k (0x1000) as this
382 memory region is used to capture NULL pointer references as well
383 as some core kernel functions.
386 hex "Kernel ROM Base"
389 range 0x20000000 0x20400000 if !(BF54x || BF561)
390 range 0x20000000 0x30000000 if (BF54x || BF561)
392 Make sure your ROM base does not include any file-header
393 information that is prepended to the kernel.
395 For example, the bootable U-Boot format (created with
396 mkimage) has a 64 byte header (0x40). So while the image
397 you write to flash might start at say 0x20080000, you have
398 to add 0x40 to get the kernel's ROM base as it will come
401 comment "Clock/PLL Setup"
404 int "Frequency of the crystal on the board in Hz"
405 default "10000000" if BFIN532_IP0X
406 default "11059200" if BFIN533_STAMP
407 default "24576000" if PNAV10
408 default "25000000" # most people use this
409 default "27000000" if BFIN533_EZKIT
410 default "30000000" if BFIN561_EZKIT
411 default "24000000" if BFIN527_AD7160EVAL
413 The frequency of CLKIN crystal oscillator on the board in Hz.
414 Warning: This value should match the crystal on the board. Otherwise,
415 peripherals won't work properly.
417 config BFIN_KERNEL_CLOCK
418 bool "Re-program Clocks while Kernel boots?"
421 This option decides if kernel clocks are re-programed from the
422 bootloader settings. If the clocks are not set, the SDRAM settings
423 are also not changed, and the Bootloader does 100% of the hardware
428 depends on BFIN_KERNEL_CLOCK
433 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
436 If this is set the clock will be divided by 2, before it goes to the PLL.
440 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
442 default "22" if BFIN533_EZKIT
443 default "45" if BFIN533_STAMP
444 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
445 default "22" if BFIN533_BLUETECHNIX_CM
446 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
447 default "20" if BFIN561_EZKIT
448 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
449 default "25" if BFIN527_AD7160EVAL
451 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
452 PLL Frequency = (Crystal Frequency) * (this setting)
455 prompt "Core Clock Divider"
456 depends on BFIN_KERNEL_CLOCK
459 This sets the frequency of the core. It can be 1, 2, 4 or 8
460 Core Frequency = (PLL frequency) / (this setting)
476 int "System Clock Divider"
477 depends on BFIN_KERNEL_CLOCK
481 This sets the frequency of the system clock (including SDRAM or DDR).
482 This can be between 1 and 15
483 System Clock = (PLL frequency) / (this setting)
486 prompt "DDR SDRAM Chip Type"
487 depends on BFIN_KERNEL_CLOCK
489 default MEM_MT46V32M16_5B
491 config MEM_MT46V32M16_6T
494 config MEM_MT46V32M16_5B
499 prompt "DDR/SDRAM Timing"
500 depends on BFIN_KERNEL_CLOCK
501 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
503 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
504 The calculated SDRAM timing parameters may not be 100%
505 accurate - This option is therefore marked experimental.
507 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
508 bool "Calculate Timings (EXPERIMENTAL)"
509 depends on EXPERIMENTAL
511 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
512 bool "Provide accurate Timings based on target SCLK"
514 Please consult the Blackfin Hardware Reference Manuals as well
515 as the memory device datasheet.
516 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
519 menu "Memory Init Control"
520 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
537 config MEM_EBIU_DDRQUE
554 # Max & Min Speeds for various Chips
558 default 400000000 if BF512
559 default 400000000 if BF514
560 default 400000000 if BF516
561 default 400000000 if BF518
562 default 400000000 if BF522
563 default 600000000 if BF523
564 default 400000000 if BF524
565 default 600000000 if BF525
566 default 400000000 if BF526
567 default 600000000 if BF527
568 default 400000000 if BF531
569 default 400000000 if BF532
570 default 750000000 if BF533
571 default 500000000 if BF534
572 default 400000000 if BF536
573 default 600000000 if BF537
574 default 533333333 if BF538
575 default 533333333 if BF539
576 default 600000000 if BF542
577 default 533333333 if BF544
578 default 600000000 if BF547
579 default 600000000 if BF548
580 default 533333333 if BF549
581 default 600000000 if BF561
595 comment "Kernel Timer/Scheduler"
597 source kernel/Kconfig.hz
599 config GENERIC_CLOCKEVENTS
600 bool "Generic clock events"
603 menu "Clock event device"
604 depends on GENERIC_CLOCKEVENTS
605 config TICKSOURCE_GPTMR0
610 config TICKSOURCE_CORETMR
616 depends on GENERIC_CLOCKEVENTS
617 config CYCLES_CLOCKSOURCE
620 depends on !BFIN_SCRATCH_REG_CYCLES
623 If you say Y here, you will enable support for using the 'cycles'
624 registers as a clock source. Doing so means you will be unable to
625 safely write to the 'cycles' register during runtime. You will
626 still be able to read it (such as for performance monitoring), but
627 writing the registers will most likely crash the kernel.
629 config GPTMR0_CLOCKSOURCE
632 depends on !TICKSOURCE_GPTMR0
635 config ARCH_USES_GETTIMEOFFSET
636 depends on !GENERIC_CLOCKEVENTS
639 source kernel/time/Kconfig
644 prompt "Blackfin Exception Scratch Register"
645 default BFIN_SCRATCH_REG_RETN
647 Select the resource to reserve for the Exception handler:
648 - RETN: Non-Maskable Interrupt (NMI)
649 - RETE: Exception Return (JTAG/ICE)
650 - CYCLES: Performance counter
652 If you are unsure, please select "RETN".
654 config BFIN_SCRATCH_REG_RETN
657 Use the RETN register in the Blackfin exception handler
658 as a stack scratch register. This means you cannot
659 safely use NMI on the Blackfin while running Linux, but
660 you can debug the system with a JTAG ICE and use the
661 CYCLES performance registers.
663 If you are unsure, please select "RETN".
665 config BFIN_SCRATCH_REG_RETE
668 Use the RETE register in the Blackfin exception handler
669 as a stack scratch register. This means you cannot
670 safely use a JTAG ICE while debugging a Blackfin board,
671 but you can safely use the CYCLES performance registers
674 If you are unsure, please select "RETN".
676 config BFIN_SCRATCH_REG_CYCLES
679 Use the CYCLES register in the Blackfin exception handler
680 as a stack scratch register. This means you cannot
681 safely use the CYCLES performance registers on a Blackfin
682 board at anytime, but you can debug the system with a JTAG
685 If you are unsure, please select "RETN".
692 menu "Blackfin Kernel Optimizations"
694 comment "Memory Optimizations"
697 bool "Locate interrupt entry code in L1 Memory"
701 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
702 into L1 instruction memory. (less latency)
704 config EXCPT_IRQ_SYSC_L1
705 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
709 If enabled, the entire ASM lowlevel exception and interrupt entry code
710 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
714 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
718 If enabled, the frequently called do_irq dispatcher function is linked
719 into L1 instruction memory. (less latency)
721 config CORE_TIMER_IRQ_L1
722 bool "Locate frequently called timer_interrupt() function in L1 Memory"
726 If enabled, the frequently called timer_interrupt() function is linked
727 into L1 instruction memory. (less latency)
730 bool "Locate frequently idle function in L1 Memory"
734 If enabled, the frequently called idle function is linked
735 into L1 instruction memory. (less latency)
738 bool "Locate kernel schedule function in L1 Memory"
742 If enabled, the frequently called kernel schedule is linked
743 into L1 instruction memory. (less latency)
745 config ARITHMETIC_OPS_L1
746 bool "Locate kernel owned arithmetic functions in L1 Memory"
750 If enabled, arithmetic functions are linked
751 into L1 instruction memory. (less latency)
754 bool "Locate access_ok function in L1 Memory"
758 If enabled, the access_ok function is linked
759 into L1 instruction memory. (less latency)
762 bool "Locate memset function in L1 Memory"
766 If enabled, the memset function is linked
767 into L1 instruction memory. (less latency)
770 bool "Locate memcpy function in L1 Memory"
774 If enabled, the memcpy function is linked
775 into L1 instruction memory. (less latency)
778 bool "locate strcmp function in L1 Memory"
782 If enabled, the strcmp function is linked
783 into L1 instruction memory (less latency).
786 bool "locate strncmp function in L1 Memory"
790 If enabled, the strncmp function is linked
791 into L1 instruction memory (less latency).
794 bool "locate strcpy function in L1 Memory"
798 If enabled, the strcpy function is linked
799 into L1 instruction memory (less latency).
802 bool "locate strncpy function in L1 Memory"
806 If enabled, the strncpy function is linked
807 into L1 instruction memory (less latency).
809 config SYS_BFIN_SPINLOCK_L1
810 bool "Locate sys_bfin_spinlock function in L1 Memory"
814 If enabled, sys_bfin_spinlock function is linked
815 into L1 instruction memory. (less latency)
817 config IP_CHECKSUM_L1
818 bool "Locate IP Checksum function in L1 Memory"
822 If enabled, the IP Checksum function is linked
823 into L1 instruction memory. (less latency)
825 config CACHELINE_ALIGNED_L1
826 bool "Locate cacheline_aligned data to L1 Data Memory"
829 depends on !SMP && !BF531
831 If enabled, cacheline_aligned data is linked
832 into L1 data memory. (less latency)
834 config SYSCALL_TAB_L1
835 bool "Locate Syscall Table L1 Data Memory"
837 depends on !SMP && !BF531
839 If enabled, the Syscall LUT is linked
840 into L1 data memory. (less latency)
842 config CPLB_SWITCH_TAB_L1
843 bool "Locate CPLB Switch Tables L1 Data Memory"
845 depends on !SMP && !BF531
847 If enabled, the CPLB Switch Tables are linked
848 into L1 data memory. (less latency)
850 config ICACHE_FLUSH_L1
851 bool "Locate icache flush funcs in L1 Inst Memory"
855 If enabled, the Blackfin icache flushing functions are linked
856 into L1 instruction memory.
858 Note that this might be required to address anomalies, but
859 these functions are pretty small, so it shouldn't be too bad.
860 If you are using a processor affected by an anomaly, the build
861 system will double check for you and prevent it.
863 config DCACHE_FLUSH_L1
864 bool "Locate dcache flush funcs in L1 Inst Memory"
868 If enabled, the Blackfin dcache flushing functions are linked
869 into L1 instruction memory.
872 bool "Support locating application stack in L1 Scratch Memory"
876 If enabled the application stack can be located in L1
877 scratch memory (less latency).
879 Currently only works with FLAT binaries.
881 config EXCEPTION_L1_SCRATCH
882 bool "Locate exception stack in L1 Scratch Memory"
884 depends on !SMP && !APP_STACK_L1
886 Whenever an exception occurs, use the L1 Scratch memory for
887 stack storage. You cannot place the stacks of FLAT binaries
888 in L1 when using this option.
890 If you don't use L1 Scratch, then you should say Y here.
892 comment "Speed Optimizations"
893 config BFIN_INS_LOWOVERHEAD
894 bool "ins[bwl] low overhead, higher interrupt latency"
898 Reads on the Blackfin are speculative. In Blackfin terms, this means
899 they can be interrupted at any time (even after they have been issued
900 on to the external bus), and re-issued after the interrupt occurs.
901 For memory - this is not a big deal, since memory does not change if
904 If a FIFO is sitting on the end of the read, it will see two reads,
905 when the core only sees one since the FIFO receives both the read
906 which is cancelled (and not delivered to the core) and the one which
907 is re-issued (which is delivered to the core).
909 To solve this, interrupts are turned off before reads occur to
910 I/O space. This option controls which the overhead/latency of
911 controlling interrupts during this time
912 "n" turns interrupts off every read
913 (higher overhead, but lower interrupt latency)
914 "y" turns interrupts off every loop
915 (low overhead, but longer interrupt latency)
917 default behavior is to leave this set to on (type "Y"). If you are experiencing
918 interrupt latency issues, it is safe and OK to turn this off.
923 prompt "Kernel executes from"
925 Choose the memory type that the kernel will be running in.
930 The kernel will be resident in RAM when running.
935 The kernel will be resident in FLASH/ROM when running.
939 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
948 tristate "Enable Blackfin General Purpose Timers API"
951 Enable support for the General Purpose Timers API. If you
954 To compile this driver as a module, choose M here: the module
955 will be called gptimers.
958 prompt "Uncached DMA region"
959 default DMA_UNCACHED_1M
960 config DMA_UNCACHED_4M
961 bool "Enable 4M DMA region"
962 config DMA_UNCACHED_2M
963 bool "Enable 2M DMA region"
964 config DMA_UNCACHED_1M
965 bool "Enable 1M DMA region"
966 config DMA_UNCACHED_512K
967 bool "Enable 512K DMA region"
968 config DMA_UNCACHED_256K
969 bool "Enable 256K DMA region"
970 config DMA_UNCACHED_128K
971 bool "Enable 128K DMA region"
972 config DMA_UNCACHED_NONE
973 bool "Disable DMA region"
977 comment "Cache Support"
982 config BFIN_EXTMEM_ICACHEABLE
983 bool "Enable ICACHE for external memory"
984 depends on BFIN_ICACHE
986 config BFIN_L2_ICACHEABLE
987 bool "Enable ICACHE for L2 SRAM"
988 depends on BFIN_ICACHE
989 depends on BF54x || BF561
995 config BFIN_DCACHE_BANKA
996 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
997 depends on BFIN_DCACHE && !BF531
999 config BFIN_EXTMEM_DCACHEABLE
1000 bool "Enable DCACHE for external memory"
1001 depends on BFIN_DCACHE
1004 prompt "External memory DCACHE policy"
1005 depends on BFIN_EXTMEM_DCACHEABLE
1006 default BFIN_EXTMEM_WRITEBACK if !SMP
1007 default BFIN_EXTMEM_WRITETHROUGH if SMP
1008 config BFIN_EXTMEM_WRITEBACK
1013 Cached data will be written back to SDRAM only when needed.
1014 This can give a nice increase in performance, but beware of
1015 broken drivers that do not properly invalidate/flush their
1018 Write Through Policy:
1019 Cached data will always be written back to SDRAM when the
1020 cache is updated. This is a completely safe setting, but
1021 performance is worse than Write Back.
1023 If you are unsure of the options and you want to be safe,
1024 then go with Write Through.
1026 config BFIN_EXTMEM_WRITETHROUGH
1027 bool "Write through"
1030 Cached data will be written back to SDRAM only when needed.
1031 This can give a nice increase in performance, but beware of
1032 broken drivers that do not properly invalidate/flush their
1035 Write Through Policy:
1036 Cached data will always be written back to SDRAM when the
1037 cache is updated. This is a completely safe setting, but
1038 performance is worse than Write Back.
1040 If you are unsure of the options and you want to be safe,
1041 then go with Write Through.
1045 config BFIN_L2_DCACHEABLE
1046 bool "Enable DCACHE for L2 SRAM"
1047 depends on BFIN_DCACHE
1048 depends on (BF54x || BF561) && !SMP
1051 prompt "L2 SRAM DCACHE policy"
1052 depends on BFIN_L2_DCACHEABLE
1053 default BFIN_L2_WRITEBACK
1054 config BFIN_L2_WRITEBACK
1057 config BFIN_L2_WRITETHROUGH
1058 bool "Write through"
1062 comment "Memory Protection Unit"
1064 bool "Enable the memory protection unit (EXPERIMENTAL)"
1067 Use the processor's MPU to protect applications from accessing
1068 memory they do not own. This comes at a performance penalty
1069 and is recommended only for debugging.
1071 comment "Asynchronous Memory Configuration"
1073 menu "EBIU_AMGCTL Global Control"
1075 bool "Enable CLKOUT"
1079 bool "DMA has priority over core for ext. accesses"
1084 bool "Bank 0 16 bit packing enable"
1089 bool "Bank 1 16 bit packing enable"
1094 bool "Bank 2 16 bit packing enable"
1099 bool "Bank 3 16 bit packing enable"
1103 prompt "Enable Asynchronous Memory Banks"
1107 bool "Disable All Banks"
1110 bool "Enable Bank 0"
1112 config C_AMBEN_B0_B1
1113 bool "Enable Bank 0 & 1"
1115 config C_AMBEN_B0_B1_B2
1116 bool "Enable Bank 0 & 1 & 2"
1119 bool "Enable All Banks"
1123 menu "EBIU_AMBCTL Control"
1125 hex "Bank 0 (AMBCTL0.L)"
1128 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1129 used to control the Asynchronous Memory Bank 0 settings.
1132 hex "Bank 1 (AMBCTL0.H)"
1134 default 0x5558 if BF54x
1136 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1137 used to control the Asynchronous Memory Bank 1 settings.
1140 hex "Bank 2 (AMBCTL1.L)"
1143 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1144 used to control the Asynchronous Memory Bank 2 settings.
1147 hex "Bank 3 (AMBCTL1.H)"
1150 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1151 used to control the Asynchronous Memory Bank 3 settings.
1155 config EBIU_MBSCTLVAL
1156 hex "EBIU Bank Select Control Register"
1161 hex "Flash Memory Mode Control Register"
1166 hex "Flash Memory Bank Control Register"
1171 #############################################################################
1172 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1178 Support for PCI bus.
1180 source "drivers/pci/Kconfig"
1182 source "drivers/pcmcia/Kconfig"
1184 source "drivers/pci/hotplug/Kconfig"
1188 menu "Executable file formats"
1190 source "fs/Kconfig.binfmt"
1194 menu "Power management options"
1196 source "kernel/power/Kconfig"
1198 config ARCH_SUSPEND_POSSIBLE
1202 prompt "Standby Power Saving Mode"
1204 default PM_BFIN_SLEEP_DEEPER
1205 config PM_BFIN_SLEEP_DEEPER
1208 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1209 power dissipation by disabling the clock to the processor core (CCLK).
1210 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1211 to 0.85 V to provide the greatest power savings, while preserving the
1213 The PLL and system clock (SCLK) continue to operate at a very low
1214 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1215 the SDRAM is put into Self Refresh Mode. Typically an external event
1216 such as GPIO interrupt or RTC activity wakes up the processor.
1217 Various Peripherals such as UART, SPORT, PPI may not function as
1218 normal during Sleep Deeper, due to the reduced SCLK frequency.
1219 When in the sleep mode, system DMA access to L1 memory is not supported.
1221 If unsure, select "Sleep Deeper".
1223 config PM_BFIN_SLEEP
1226 Sleep Mode (High Power Savings) - The sleep mode reduces power
1227 dissipation by disabling the clock to the processor core (CCLK).
1228 The PLL and system clock (SCLK), however, continue to operate in
1229 this mode. Typically an external event or RTC activity will wake
1230 up the processor. When in the sleep mode, system DMA access to L1
1231 memory is not supported.
1233 If unsure, select "Sleep Deeper".
1236 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1239 config PM_BFIN_WAKE_PH6
1240 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1241 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1244 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1246 config PM_BFIN_WAKE_GP
1247 bool "Allow Wake-Up from GPIOs"
1248 depends on PM && BF54x
1251 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1252 (all processors, except ADSP-BF549). This option sets
1253 the general-purpose wake-up enable (GPWE) control bit to enable
1254 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1255 On ADSP-BF549 this option enables the the same functionality on the
1256 /MRXON pin also PH7.
1260 menu "CPU Frequency scaling"
1262 source "drivers/cpufreq/Kconfig"
1264 config BFIN_CPU_FREQ
1267 select CPU_FREQ_TABLE
1271 bool "CPU Voltage scaling"
1272 depends on EXPERIMENTAL
1276 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1277 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1278 manuals. There is a theoretical risk that during VDDINT transitions
1283 source "net/Kconfig"
1285 source "drivers/Kconfig"
1287 source "drivers/firmware/Kconfig"
1291 source "arch/blackfin/Kconfig.debug"
1293 source "security/Kconfig"
1295 source "crypto/Kconfig"
1297 source "lib/Kconfig"