2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
34 config GENERIC_FIND_NEXT_BIT
38 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
46 config GENERIC_IRQ_PROBE
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
67 source "kernel/Kconfig.preempt"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF522 Processor Support.
85 BF523 Processor Support.
90 BF524 Processor Support.
95 BF525 Processor Support.
100 BF526 Processor Support.
105 BF527 Processor Support.
110 BF531 Processor Support.
115 BF532 Processor Support.
120 BF533 Processor Support.
125 BF534 Processor Support.
130 BF536 Processor Support.
135 BF537 Processor Support.
140 BF542 Processor Support.
145 BF544 Processor Support.
150 BF547 Processor Support.
155 BF548 Processor Support.
160 BF549 Processor Support.
165 BF561 Processor Support.
171 default BF_REV_0_1 if (BF52x || BF54x)
172 default BF_REV_0_2 if (BF534 || BF536 || BF537)
173 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
177 depends on (BF52x || BF54x)
181 depends on (BF52x || BF54x)
185 depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
189 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
193 depends on (BF561 || BF533 || BF532 || BF531)
197 depends on (BF561 || BF533 || BF532 || BF531)
201 depends on (BF533 || BF532 || BF531)
213 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
218 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
223 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
226 config MEM_GENERIC_BOARD
228 depends on GENERIC_BOARD
231 config MEM_MT48LC64M4A2FB_7E
233 depends on (BFIN533_STAMP)
236 config MEM_MT48LC16M16A2TG_75
238 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
239 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
240 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
243 config MEM_MT48LC32M8A2_75
245 depends on (BFIN537_STAMP || PNAV10)
248 config MEM_MT48LC8M32B2B5_7
250 depends on (BFIN561_BLUETECHNIX_CM)
253 config MEM_MT48LC32M16A2TG_75
255 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
258 source "arch/blackfin/mach-bf527/Kconfig"
259 source "arch/blackfin/mach-bf533/Kconfig"
260 source "arch/blackfin/mach-bf561/Kconfig"
261 source "arch/blackfin/mach-bf537/Kconfig"
262 source "arch/blackfin/mach-bf548/Kconfig"
264 menu "Board customizations"
267 bool "Default bootloader kernel arguments"
270 string "Initial kernel command string"
271 depends on CMDLINE_BOOL
272 default "console=ttyBF0,57600"
274 If you don't have a boot loader capable of passing a command line string
275 to the kernel, you may specify one here. As a minimum, you should specify
276 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
279 hex "Kernel load address for booting"
281 range 0x1000 0x20000000
283 This option allows you to set the load address of the kernel.
284 This can be useful if you are on a board which has a small amount
285 of memory or you wish to reserve some memory at the beginning of
288 Note that you need to keep this value above 4k (0x1000) as this
289 memory region is used to capture NULL pointer references as well
290 as some core kernel functions.
293 hex "Kernel ROM Base"
295 range 0x20000000 0x20400000 if !(BF54x || BF561)
296 range 0x20000000 0x30000000 if (BF54x || BF561)
299 comment "Clock/PLL Setup"
302 int "Frequency of the crystal on the board in Hz"
303 default "11059200" if BFIN533_STAMP
304 default "27000000" if BFIN533_EZKIT
305 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
306 default "30000000" if BFIN561_EZKIT
307 default "24576000" if PNAV10
308 default "10000000" if BFIN532_IP0X
310 The frequency of CLKIN crystal oscillator on the board in Hz.
311 Warning: This value should match the crystal on the board. Otherwise,
312 peripherals won't work properly.
314 config BFIN_KERNEL_CLOCK
315 bool "Re-program Clocks while Kernel boots?"
318 This option decides if kernel clocks are re-programed from the
319 bootloader settings. If the clocks are not set, the SDRAM settings
320 are also not changed, and the Bootloader does 100% of the hardware
325 depends on BFIN_KERNEL_CLOCK
330 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
333 If this is set the clock will be divided by 2, before it goes to the PLL.
337 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
339 default "22" if BFIN533_EZKIT
340 default "45" if BFIN533_STAMP
341 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
342 default "22" if BFIN533_BLUETECHNIX_CM
343 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
344 default "20" if BFIN561_EZKIT
345 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
347 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
348 PLL Frequency = (Crystal Frequency) * (this setting)
351 prompt "Core Clock Divider"
352 depends on BFIN_KERNEL_CLOCK
355 This sets the frequency of the core. It can be 1, 2, 4 or 8
356 Core Frequency = (PLL frequency) / (this setting)
372 int "System Clock Divider"
373 depends on BFIN_KERNEL_CLOCK
377 This sets the frequency of the system clock (including SDRAM or DDR).
378 This can be between 1 and 15
379 System Clock = (PLL frequency) / (this setting)
382 prompt "DDR SDRAM Chip Type"
383 depends on BFIN_KERNEL_CLOCK
385 default MEM_MT46V32M16_5B
387 config MEM_MT46V32M16_6T
390 config MEM_MT46V32M16_5B
395 int "Max SDRAM Memory Size in MBytes"
399 This is the max memory size that the kernel will create CPLB
400 tables for. Your system will not be able to handle any more.
403 # Max & Min Speeds for various Chips
407 default 600000000 if BF522
408 default 400000000 if BF523
409 default 400000000 if BF524
410 default 600000000 if BF525
411 default 400000000 if BF526
412 default 600000000 if BF527
413 default 400000000 if BF531
414 default 400000000 if BF532
415 default 750000000 if BF533
416 default 500000000 if BF534
417 default 400000000 if BF536
418 default 600000000 if BF537
419 default 533333333 if BF538
420 default 533333333 if BF539
421 default 600000000 if BF542
422 default 533333333 if BF544
423 default 600000000 if BF547
424 default 600000000 if BF548
425 default 533333333 if BF549
426 default 600000000 if BF561
440 comment "Kernel Timer/Scheduler"
442 source kernel/Kconfig.hz
448 config GENERIC_CLOCKEVENTS
449 bool "Generic clock events"
450 depends on GENERIC_TIME
453 config CYCLES_CLOCKSOURCE
454 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
455 depends on EXPERIMENTAL
456 depends on GENERIC_CLOCKEVENTS
457 depends on !BFIN_SCRATCH_REG_CYCLES
460 If you say Y here, you will enable support for using the 'cycles'
461 registers as a clock source. Doing so means you will be unable to
462 safely write to the 'cycles' register during runtime. You will
463 still be able to read it (such as for performance monitoring), but
464 writing the registers will most likely crash the kernel.
466 source kernel/time/Kconfig
471 prompt "Blackfin Exception Scratch Register"
472 default BFIN_SCRATCH_REG_RETN
474 Select the resource to reserve for the Exception handler:
475 - RETN: Non-Maskable Interrupt (NMI)
476 - RETE: Exception Return (JTAG/ICE)
477 - CYCLES: Performance counter
479 If you are unsure, please select "RETN".
481 config BFIN_SCRATCH_REG_RETN
484 Use the RETN register in the Blackfin exception handler
485 as a stack scratch register. This means you cannot
486 safely use NMI on the Blackfin while running Linux, but
487 you can debug the system with a JTAG ICE and use the
488 CYCLES performance registers.
490 If you are unsure, please select "RETN".
492 config BFIN_SCRATCH_REG_RETE
495 Use the RETE register in the Blackfin exception handler
496 as a stack scratch register. This means you cannot
497 safely use a JTAG ICE while debugging a Blackfin board,
498 but you can safely use the CYCLES performance registers
501 If you are unsure, please select "RETN".
503 config BFIN_SCRATCH_REG_CYCLES
506 Use the CYCLES register in the Blackfin exception handler
507 as a stack scratch register. This means you cannot
508 safely use the CYCLES performance registers on a Blackfin
509 board at anytime, but you can debug the system with a JTAG
512 If you are unsure, please select "RETN".
519 menu "Blackfin Kernel Optimizations"
521 comment "Memory Optimizations"
524 bool "Locate interrupt entry code in L1 Memory"
527 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
528 into L1 instruction memory. (less latency)
530 config EXCPT_IRQ_SYSC_L1
531 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
534 If enabled, the entire ASM lowlevel exception and interrupt entry code
535 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
539 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
542 If enabled, the frequently called do_irq dispatcher function is linked
543 into L1 instruction memory. (less latency)
545 config CORE_TIMER_IRQ_L1
546 bool "Locate frequently called timer_interrupt() function in L1 Memory"
549 If enabled, the frequently called timer_interrupt() function is linked
550 into L1 instruction memory. (less latency)
553 bool "Locate frequently idle function in L1 Memory"
556 If enabled, the frequently called idle function is linked
557 into L1 instruction memory. (less latency)
560 bool "Locate kernel schedule function in L1 Memory"
563 If enabled, the frequently called kernel schedule is linked
564 into L1 instruction memory. (less latency)
566 config ARITHMETIC_OPS_L1
567 bool "Locate kernel owned arithmetic functions in L1 Memory"
570 If enabled, arithmetic functions are linked
571 into L1 instruction memory. (less latency)
574 bool "Locate access_ok function in L1 Memory"
577 If enabled, the access_ok function is linked
578 into L1 instruction memory. (less latency)
581 bool "Locate memset function in L1 Memory"
584 If enabled, the memset function is linked
585 into L1 instruction memory. (less latency)
588 bool "Locate memcpy function in L1 Memory"
591 If enabled, the memcpy function is linked
592 into L1 instruction memory. (less latency)
594 config SYS_BFIN_SPINLOCK_L1
595 bool "Locate sys_bfin_spinlock function in L1 Memory"
598 If enabled, sys_bfin_spinlock function is linked
599 into L1 instruction memory. (less latency)
601 config IP_CHECKSUM_L1
602 bool "Locate IP Checksum function in L1 Memory"
605 If enabled, the IP Checksum function is linked
606 into L1 instruction memory. (less latency)
608 config CACHELINE_ALIGNED_L1
609 bool "Locate cacheline_aligned data to L1 Data Memory"
614 If enabled, cacheline_anligned data is linked
615 into L1 data memory. (less latency)
617 config SYSCALL_TAB_L1
618 bool "Locate Syscall Table L1 Data Memory"
622 If enabled, the Syscall LUT is linked
623 into L1 data memory. (less latency)
625 config CPLB_SWITCH_TAB_L1
626 bool "Locate CPLB Switch Tables L1 Data Memory"
630 If enabled, the CPLB Switch Tables are linked
631 into L1 data memory. (less latency)
634 bool "Support locating application stack in L1 Scratch Memory"
637 If enabled the application stack can be located in L1
638 scratch memory (less latency).
640 Currently only works with FLAT binaries.
642 comment "Speed Optimizations"
643 config BFIN_INS_LOWOVERHEAD
644 bool "ins[bwl] low overhead, higher interrupt latency"
647 Reads on the Blackfin are speculative. In Blackfin terms, this means
648 they can be interrupted at any time (even after they have been issued
649 on to the external bus), and re-issued after the interrupt occurs.
650 For memory - this is not a big deal, since memory does not change if
653 If a FIFO is sitting on the end of the read, it will see two reads,
654 when the core only sees one since the FIFO receives both the read
655 which is cancelled (and not delivered to the core) and the one which
656 is re-issued (which is delivered to the core).
658 To solve this, interrupts are turned off before reads occur to
659 I/O space. This option controls which the overhead/latency of
660 controlling interrupts during this time
661 "n" turns interrupts off every read
662 (higher overhead, but lower interrupt latency)
663 "y" turns interrupts off every loop
664 (low overhead, but longer interrupt latency)
666 default behavior is to leave this set to on (type "Y"). If you are experiencing
667 interrupt latency issues, it is safe and OK to turn this off.
673 prompt "Kernel executes from"
675 Choose the memory type that the kernel will be running in.
680 The kernel will be resident in RAM when running.
685 The kernel will be resident in FLASH/ROM when running.
692 tristate "Enable Blackfin General Purpose Timers API"
695 Enable support for the General Purpose Timers API. If you
698 To compile this driver as a module, choose M here: the module
699 will be called gptimers.ko.
702 bool "Enable DMA Support"
703 depends on (BF52x || BF53x || BF561 || BF54x)
706 DMA driver for BF5xx.
709 prompt "Uncached SDRAM region"
710 default DMA_UNCACHED_1M
711 depends on BFIN_DMA_5XX
712 config DMA_UNCACHED_4M
713 bool "Enable 4M DMA region"
714 config DMA_UNCACHED_2M
715 bool "Enable 2M DMA region"
716 config DMA_UNCACHED_1M
717 bool "Enable 1M DMA region"
718 config DMA_UNCACHED_NONE
719 bool "Disable DMA region"
723 comment "Cache Support"
728 config BFIN_DCACHE_BANKA
729 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
730 depends on BFIN_DCACHE && !BF531
732 config BFIN_ICACHE_LOCK
733 bool "Enable Instruction Cache Locking"
737 depends on BFIN_DCACHE
743 Cached data will be written back to SDRAM only when needed.
744 This can give a nice increase in performance, but beware of
745 broken drivers that do not properly invalidate/flush their
748 Write Through Policy:
749 Cached data will always be written back to SDRAM when the
750 cache is updated. This is a completely safe setting, but
751 performance is worse than Write Back.
753 If you are unsure of the options and you want to be safe,
754 then go with Write Through.
760 Cached data will be written back to SDRAM only when needed.
761 This can give a nice increase in performance, but beware of
762 broken drivers that do not properly invalidate/flush their
765 Write Through Policy:
766 Cached data will always be written back to SDRAM when the
767 cache is updated. This is a completely safe setting, but
768 performance is worse than Write Back.
770 If you are unsure of the options and you want to be safe,
771 then go with Write Through.
775 config BFIN_L2_CACHEABLE
777 depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
780 Select to make L2 SRAM cacheable in L1 data and instruction cache.
783 bool "Enable the memory protection unit (EXPERIMENTAL)"
786 Use the processor's MPU to protect applications from accessing
787 memory they do not own. This comes at a performance penalty
788 and is recommended only for debugging.
790 comment "Asynchonous Memory Configuration"
792 menu "EBIU_AMGCTL Global Control"
798 bool "DMA has priority over core for ext. accesses"
803 bool "Bank 0 16 bit packing enable"
808 bool "Bank 1 16 bit packing enable"
813 bool "Bank 2 16 bit packing enable"
818 bool "Bank 3 16 bit packing enable"
822 prompt"Enable Asynchonous Memory Banks"
826 bool "Disable All Banks"
832 bool "Enable Bank 0 & 1"
834 config C_AMBEN_B0_B1_B2
835 bool "Enable Bank 0 & 1 & 2"
838 bool "Enable All Banks"
842 menu "EBIU_AMBCTL Control"
850 default 0x5558 if BF54x
861 config EBIU_MBSCTLVAL
862 hex "EBIU Bank Select Control Register"
867 hex "Flash Memory Mode Control Register"
872 hex "Flash Memory Bank Control Register"
877 #############################################################################
878 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
886 source "drivers/pci/Kconfig"
889 bool "Support for hot-pluggable device"
891 Say Y here if you want to plug devices into your computer while
892 the system is running, and be able to use them quickly. In many
893 cases, the devices can likewise be unplugged at any time too.
895 One well known example of this is PCMCIA- or PC-cards, credit-card
896 size devices such as network cards, modems or hard drives which are
897 plugged into slots found on all modern laptop computers. Another
898 example, used on modern desktops as well as laptops, is USB.
900 Enable HOTPLUG and build a modular kernel. Get agent software
901 (from <http://linux-hotplug.sourceforge.net/>) and install it.
902 Then your kernel will automatically call out to a user mode "policy
903 agent" (/sbin/hotplug) to load modules and set up software needed
904 to use devices as you hotplug them.
906 source "drivers/pcmcia/Kconfig"
908 source "drivers/pci/hotplug/Kconfig"
912 menu "Executable file formats"
914 source "fs/Kconfig.binfmt"
918 menu "Power management options"
919 source "kernel/power/Kconfig"
921 config ARCH_SUSPEND_POSSIBLE
926 prompt "Standby Power Saving Mode"
928 default PM_BFIN_SLEEP_DEEPER
929 config PM_BFIN_SLEEP_DEEPER
932 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
933 power dissipation by disabling the clock to the processor core (CCLK).
934 Furthermore, Standby sets the internal power supply voltage (VDDINT)
935 to 0.85 V to provide the greatest power savings, while preserving the
937 The PLL and system clock (SCLK) continue to operate at a very low
938 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
939 the SDRAM is put into Self Refresh Mode. Typically an external event
940 such as GPIO interrupt or RTC activity wakes up the processor.
941 Various Peripherals such as UART, SPORT, PPI may not function as
942 normal during Sleep Deeper, due to the reduced SCLK frequency.
943 When in the sleep mode, system DMA access to L1 memory is not supported.
945 If unsure, select "Sleep Deeper".
950 Sleep Mode (High Power Savings) - The sleep mode reduces power
951 dissipation by disabling the clock to the processor core (CCLK).
952 The PLL and system clock (SCLK), however, continue to operate in
953 this mode. Typically an external event or RTC activity will wake
954 up the processor. When in the sleep mode, system DMA access to L1
955 memory is not supported.
957 If unsure, select "Sleep Deeper".
960 config PM_WAKEUP_BY_GPIO
961 bool "Allow Wakeup from Standby by GPIO"
963 config PM_WAKEUP_GPIO_NUMBER
966 depends on PM_WAKEUP_BY_GPIO
967 default 2 if BFIN537_STAMP
970 prompt "GPIO Polarity"
971 depends on PM_WAKEUP_BY_GPIO
972 default PM_WAKEUP_GPIO_POLAR_H
973 config PM_WAKEUP_GPIO_POLAR_H
975 config PM_WAKEUP_GPIO_POLAR_L
977 config PM_WAKEUP_GPIO_POLAR_EDGE_F
979 config PM_WAKEUP_GPIO_POLAR_EDGE_R
981 config PM_WAKEUP_GPIO_POLAR_EDGE_B
985 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
988 config PM_BFIN_WAKE_PH6
989 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
990 depends on PM && (BF52x || BF534 || BF536 || BF537)
993 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
995 config PM_BFIN_WAKE_GP
996 bool "Allow Wake-Up from GPIOs"
997 depends on PM && BF54x
1000 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1003 menu "CPU Frequency scaling"
1005 source "drivers/cpufreq/Kconfig"
1008 bool "CPU Voltage scaling"
1009 depends on EXPERIMENTAL
1013 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1014 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1015 manuals. There is a theoretical risk that during VDDINT transitions
1020 source "net/Kconfig"
1022 source "drivers/Kconfig"
1026 source "arch/blackfin/Kconfig.debug"
1028 source "security/Kconfig"
1030 source "crypto/Kconfig"
1032 source "lib/Kconfig"