11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
27 select HAVE_KERNEL_GZIP if RAMKERNEL
28 select HAVE_KERNEL_BZIP2 if RAMKERNEL
29 select HAVE_KERNEL_LZMA if RAMKERNEL
30 select HAVE_KERNEL_LZO if RAMKERNEL
32 select ARCH_WANT_OPTIONAL_GPIOLIB
33 select HAVE_GENERIC_HARDIRQS
34 select GENERIC_ATOMIC64
35 select GENERIC_IRQ_PROBE
36 select IRQ_PER_CPU if SMP
37 select GENERIC_HARDIRQS_NO_DEPRECATED
49 config GENERIC_FIND_NEXT_BIT
55 config FORCE_MAX_ZONEORDER
59 config GENERIC_CALIBRATE_DELAY
62 config LOCKDEP_SUPPORT
65 config STACKTRACE_SUPPORT
68 config TRACE_IRQFLAGS_SUPPORT
73 source "kernel/Kconfig.preempt"
75 source "kernel/Kconfig.freezer"
77 menu "Blackfin Processor Options"
79 comment "Processor and Board Settings"
88 BF512 Processor Support.
93 BF514 Processor Support.
98 BF516 Processor Support.
103 BF518 Processor Support.
108 BF522 Processor Support.
113 BF523 Processor Support.
118 BF524 Processor Support.
123 BF525 Processor Support.
128 BF526 Processor Support.
133 BF527 Processor Support.
138 BF531 Processor Support.
143 BF532 Processor Support.
148 BF533 Processor Support.
153 BF534 Processor Support.
158 BF536 Processor Support.
163 BF537 Processor Support.
168 BF538 Processor Support.
173 BF539 Processor Support.
178 BF542 Processor Support.
183 BF542 Processor Support.
188 BF544 Processor Support.
193 BF544 Processor Support.
198 BF547 Processor Support.
203 BF547 Processor Support.
208 BF548 Processor Support.
213 BF548 Processor Support.
218 BF549 Processor Support.
223 BF549 Processor Support.
228 BF561 Processor Support.
234 select TICKSOURCE_CORETMR
235 bool "Symmetric multi-processing support"
237 This enables support for systems with more than one CPU,
238 like the dual core BF561. If you have a system with only one
239 CPU, say N. If you have a system with more than one CPU, say Y.
241 If you don't know what to do here, say N.
249 bool "Support for hot-pluggable CPUs"
250 depends on SMP && HOTPLUG
253 config HAVE_LEGACY_PER_CPU_AREA
259 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
260 default 2 if (BF537 || BF536 || BF534)
261 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
262 default 4 if (BF538 || BF539)
266 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
267 default 3 if (BF537 || BF536 || BF534 || BF54xM)
268 default 5 if (BF561 || BF538 || BF539)
269 default 6 if (BF533 || BF532 || BF531)
273 default BF_REV_0_0 if (BF51x || BF52x)
274 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
275 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
279 depends on (BF51x || BF52x || (BF54x && !BF54xM))
283 depends on (BF51x || BF52x || (BF54x && !BF54xM))
287 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
291 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
295 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
299 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
303 depends on (BF533 || BF532 || BF531)
315 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
318 config MEM_MT48LC64M4A2FB_7E
320 depends on (BFIN533_STAMP)
323 config MEM_MT48LC16M16A2TG_75
325 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
326 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
327 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
328 || BFIN527_BLUETECHNIX_CM)
331 config MEM_MT48LC32M8A2_75
333 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
336 config MEM_MT48LC8M32B2B5_7
338 depends on (BFIN561_BLUETECHNIX_CM)
341 config MEM_MT48LC32M16A2TG_75
343 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
346 config MEM_MT48H32M16LFCJ_75
348 depends on (BFIN526_EZBRD)
351 source "arch/blackfin/mach-bf518/Kconfig"
352 source "arch/blackfin/mach-bf527/Kconfig"
353 source "arch/blackfin/mach-bf533/Kconfig"
354 source "arch/blackfin/mach-bf561/Kconfig"
355 source "arch/blackfin/mach-bf537/Kconfig"
356 source "arch/blackfin/mach-bf538/Kconfig"
357 source "arch/blackfin/mach-bf548/Kconfig"
359 menu "Board customizations"
362 bool "Default bootloader kernel arguments"
365 string "Initial kernel command string"
366 depends on CMDLINE_BOOL
367 default "console=ttyBF0,57600"
369 If you don't have a boot loader capable of passing a command line string
370 to the kernel, you may specify one here. As a minimum, you should specify
371 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
374 hex "Kernel load address for booting"
376 range 0x1000 0x20000000
378 This option allows you to set the load address of the kernel.
379 This can be useful if you are on a board which has a small amount
380 of memory or you wish to reserve some memory at the beginning of
383 Note that you need to keep this value above 4k (0x1000) as this
384 memory region is used to capture NULL pointer references as well
385 as some core kernel functions.
388 hex "Kernel ROM Base"
391 range 0x20000000 0x20400000 if !(BF54x || BF561)
392 range 0x20000000 0x30000000 if (BF54x || BF561)
394 Make sure your ROM base does not include any file-header
395 information that is prepended to the kernel.
397 For example, the bootable U-Boot format (created with
398 mkimage) has a 64 byte header (0x40). So while the image
399 you write to flash might start at say 0x20080000, you have
400 to add 0x40 to get the kernel's ROM base as it will come
403 comment "Clock/PLL Setup"
406 int "Frequency of the crystal on the board in Hz"
407 default "10000000" if BFIN532_IP0X
408 default "11059200" if BFIN533_STAMP
409 default "24576000" if PNAV10
410 default "25000000" # most people use this
411 default "27000000" if BFIN533_EZKIT
412 default "30000000" if BFIN561_EZKIT
413 default "24000000" if BFIN527_AD7160EVAL
415 The frequency of CLKIN crystal oscillator on the board in Hz.
416 Warning: This value should match the crystal on the board. Otherwise,
417 peripherals won't work properly.
419 config BFIN_KERNEL_CLOCK
420 bool "Re-program Clocks while Kernel boots?"
423 This option decides if kernel clocks are re-programed from the
424 bootloader settings. If the clocks are not set, the SDRAM settings
425 are also not changed, and the Bootloader does 100% of the hardware
430 depends on BFIN_KERNEL_CLOCK
435 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
438 If this is set the clock will be divided by 2, before it goes to the PLL.
442 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
444 default "22" if BFIN533_EZKIT
445 default "45" if BFIN533_STAMP
446 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
447 default "22" if BFIN533_BLUETECHNIX_CM
448 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
449 default "20" if BFIN561_EZKIT
450 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
451 default "25" if BFIN527_AD7160EVAL
453 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
454 PLL Frequency = (Crystal Frequency) * (this setting)
457 prompt "Core Clock Divider"
458 depends on BFIN_KERNEL_CLOCK
461 This sets the frequency of the core. It can be 1, 2, 4 or 8
462 Core Frequency = (PLL frequency) / (this setting)
478 int "System Clock Divider"
479 depends on BFIN_KERNEL_CLOCK
483 This sets the frequency of the system clock (including SDRAM or DDR).
484 This can be between 1 and 15
485 System Clock = (PLL frequency) / (this setting)
488 prompt "DDR SDRAM Chip Type"
489 depends on BFIN_KERNEL_CLOCK
491 default MEM_MT46V32M16_5B
493 config MEM_MT46V32M16_6T
496 config MEM_MT46V32M16_5B
501 prompt "DDR/SDRAM Timing"
502 depends on BFIN_KERNEL_CLOCK
503 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
505 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
506 The calculated SDRAM timing parameters may not be 100%
507 accurate - This option is therefore marked experimental.
509 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
510 bool "Calculate Timings (EXPERIMENTAL)"
511 depends on EXPERIMENTAL
513 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
514 bool "Provide accurate Timings based on target SCLK"
516 Please consult the Blackfin Hardware Reference Manuals as well
517 as the memory device datasheet.
518 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
521 menu "Memory Init Control"
522 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
539 config MEM_EBIU_DDRQUE
556 # Max & Min Speeds for various Chips
560 default 400000000 if BF512
561 default 400000000 if BF514
562 default 400000000 if BF516
563 default 400000000 if BF518
564 default 400000000 if BF522
565 default 600000000 if BF523
566 default 400000000 if BF524
567 default 600000000 if BF525
568 default 400000000 if BF526
569 default 600000000 if BF527
570 default 400000000 if BF531
571 default 400000000 if BF532
572 default 750000000 if BF533
573 default 500000000 if BF534
574 default 400000000 if BF536
575 default 600000000 if BF537
576 default 533333333 if BF538
577 default 533333333 if BF539
578 default 600000000 if BF542
579 default 533333333 if BF544
580 default 600000000 if BF547
581 default 600000000 if BF548
582 default 533333333 if BF549
583 default 600000000 if BF561
597 comment "Kernel Timer/Scheduler"
599 source kernel/Kconfig.hz
601 config GENERIC_CLOCKEVENTS
602 bool "Generic clock events"
605 menu "Clock event device"
606 depends on GENERIC_CLOCKEVENTS
607 config TICKSOURCE_GPTMR0
612 config TICKSOURCE_CORETMR
618 depends on GENERIC_CLOCKEVENTS
619 config CYCLES_CLOCKSOURCE
622 depends on !BFIN_SCRATCH_REG_CYCLES
625 If you say Y here, you will enable support for using the 'cycles'
626 registers as a clock source. Doing so means you will be unable to
627 safely write to the 'cycles' register during runtime. You will
628 still be able to read it (such as for performance monitoring), but
629 writing the registers will most likely crash the kernel.
631 config GPTMR0_CLOCKSOURCE
634 depends on !TICKSOURCE_GPTMR0
637 config ARCH_USES_GETTIMEOFFSET
638 depends on !GENERIC_CLOCKEVENTS
641 source kernel/time/Kconfig
646 prompt "Blackfin Exception Scratch Register"
647 default BFIN_SCRATCH_REG_RETN
649 Select the resource to reserve for the Exception handler:
650 - RETN: Non-Maskable Interrupt (NMI)
651 - RETE: Exception Return (JTAG/ICE)
652 - CYCLES: Performance counter
654 If you are unsure, please select "RETN".
656 config BFIN_SCRATCH_REG_RETN
659 Use the RETN register in the Blackfin exception handler
660 as a stack scratch register. This means you cannot
661 safely use NMI on the Blackfin while running Linux, but
662 you can debug the system with a JTAG ICE and use the
663 CYCLES performance registers.
665 If you are unsure, please select "RETN".
667 config BFIN_SCRATCH_REG_RETE
670 Use the RETE register in the Blackfin exception handler
671 as a stack scratch register. This means you cannot
672 safely use a JTAG ICE while debugging a Blackfin board,
673 but you can safely use the CYCLES performance registers
676 If you are unsure, please select "RETN".
678 config BFIN_SCRATCH_REG_CYCLES
681 Use the CYCLES register in the Blackfin exception handler
682 as a stack scratch register. This means you cannot
683 safely use the CYCLES performance registers on a Blackfin
684 board at anytime, but you can debug the system with a JTAG
687 If you are unsure, please select "RETN".
694 menu "Blackfin Kernel Optimizations"
696 comment "Memory Optimizations"
699 bool "Locate interrupt entry code in L1 Memory"
703 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
704 into L1 instruction memory. (less latency)
706 config EXCPT_IRQ_SYSC_L1
707 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
711 If enabled, the entire ASM lowlevel exception and interrupt entry code
712 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
716 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
720 If enabled, the frequently called do_irq dispatcher function is linked
721 into L1 instruction memory. (less latency)
723 config CORE_TIMER_IRQ_L1
724 bool "Locate frequently called timer_interrupt() function in L1 Memory"
728 If enabled, the frequently called timer_interrupt() function is linked
729 into L1 instruction memory. (less latency)
732 bool "Locate frequently idle function in L1 Memory"
736 If enabled, the frequently called idle function is linked
737 into L1 instruction memory. (less latency)
740 bool "Locate kernel schedule function in L1 Memory"
744 If enabled, the frequently called kernel schedule is linked
745 into L1 instruction memory. (less latency)
747 config ARITHMETIC_OPS_L1
748 bool "Locate kernel owned arithmetic functions in L1 Memory"
752 If enabled, arithmetic functions are linked
753 into L1 instruction memory. (less latency)
756 bool "Locate access_ok function in L1 Memory"
760 If enabled, the access_ok function is linked
761 into L1 instruction memory. (less latency)
764 bool "Locate memset function in L1 Memory"
768 If enabled, the memset function is linked
769 into L1 instruction memory. (less latency)
772 bool "Locate memcpy function in L1 Memory"
776 If enabled, the memcpy function is linked
777 into L1 instruction memory. (less latency)
780 bool "locate strcmp function in L1 Memory"
784 If enabled, the strcmp function is linked
785 into L1 instruction memory (less latency).
788 bool "locate strncmp function in L1 Memory"
792 If enabled, the strncmp function is linked
793 into L1 instruction memory (less latency).
796 bool "locate strcpy function in L1 Memory"
800 If enabled, the strcpy function is linked
801 into L1 instruction memory (less latency).
804 bool "locate strncpy function in L1 Memory"
808 If enabled, the strncpy function is linked
809 into L1 instruction memory (less latency).
811 config SYS_BFIN_SPINLOCK_L1
812 bool "Locate sys_bfin_spinlock function in L1 Memory"
816 If enabled, sys_bfin_spinlock function is linked
817 into L1 instruction memory. (less latency)
819 config IP_CHECKSUM_L1
820 bool "Locate IP Checksum function in L1 Memory"
824 If enabled, the IP Checksum function is linked
825 into L1 instruction memory. (less latency)
827 config CACHELINE_ALIGNED_L1
828 bool "Locate cacheline_aligned data to L1 Data Memory"
831 depends on !SMP && !BF531
833 If enabled, cacheline_aligned data is linked
834 into L1 data memory. (less latency)
836 config SYSCALL_TAB_L1
837 bool "Locate Syscall Table L1 Data Memory"
839 depends on !SMP && !BF531
841 If enabled, the Syscall LUT is linked
842 into L1 data memory. (less latency)
844 config CPLB_SWITCH_TAB_L1
845 bool "Locate CPLB Switch Tables L1 Data Memory"
847 depends on !SMP && !BF531
849 If enabled, the CPLB Switch Tables are linked
850 into L1 data memory. (less latency)
852 config ICACHE_FLUSH_L1
853 bool "Locate icache flush funcs in L1 Inst Memory"
856 If enabled, the Blackfin icache flushing functions are linked
857 into L1 instruction memory.
859 Note that this might be required to address anomalies, but
860 these functions are pretty small, so it shouldn't be too bad.
861 If you are using a processor affected by an anomaly, the build
862 system will double check for you and prevent it.
864 config DCACHE_FLUSH_L1
865 bool "Locate dcache flush funcs in L1 Inst Memory"
869 If enabled, the Blackfin dcache flushing functions are linked
870 into L1 instruction memory.
873 bool "Support locating application stack in L1 Scratch Memory"
877 If enabled the application stack can be located in L1
878 scratch memory (less latency).
880 Currently only works with FLAT binaries.
882 config EXCEPTION_L1_SCRATCH
883 bool "Locate exception stack in L1 Scratch Memory"
885 depends on !SMP && !APP_STACK_L1
887 Whenever an exception occurs, use the L1 Scratch memory for
888 stack storage. You cannot place the stacks of FLAT binaries
889 in L1 when using this option.
891 If you don't use L1 Scratch, then you should say Y here.
893 comment "Speed Optimizations"
894 config BFIN_INS_LOWOVERHEAD
895 bool "ins[bwl] low overhead, higher interrupt latency"
899 Reads on the Blackfin are speculative. In Blackfin terms, this means
900 they can be interrupted at any time (even after they have been issued
901 on to the external bus), and re-issued after the interrupt occurs.
902 For memory - this is not a big deal, since memory does not change if
905 If a FIFO is sitting on the end of the read, it will see two reads,
906 when the core only sees one since the FIFO receives both the read
907 which is cancelled (and not delivered to the core) and the one which
908 is re-issued (which is delivered to the core).
910 To solve this, interrupts are turned off before reads occur to
911 I/O space. This option controls which the overhead/latency of
912 controlling interrupts during this time
913 "n" turns interrupts off every read
914 (higher overhead, but lower interrupt latency)
915 "y" turns interrupts off every loop
916 (low overhead, but longer interrupt latency)
918 default behavior is to leave this set to on (type "Y"). If you are experiencing
919 interrupt latency issues, it is safe and OK to turn this off.
924 prompt "Kernel executes from"
926 Choose the memory type that the kernel will be running in.
931 The kernel will be resident in RAM when running.
936 The kernel will be resident in FLASH/ROM when running.
940 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
949 tristate "Enable Blackfin General Purpose Timers API"
952 Enable support for the General Purpose Timers API. If you
955 To compile this driver as a module, choose M here: the module
956 will be called gptimers.
959 prompt "Uncached DMA region"
960 default DMA_UNCACHED_1M
961 config DMA_UNCACHED_4M
962 bool "Enable 4M DMA region"
963 config DMA_UNCACHED_2M
964 bool "Enable 2M DMA region"
965 config DMA_UNCACHED_1M
966 bool "Enable 1M DMA region"
967 config DMA_UNCACHED_512K
968 bool "Enable 512K DMA region"
969 config DMA_UNCACHED_256K
970 bool "Enable 256K DMA region"
971 config DMA_UNCACHED_128K
972 bool "Enable 128K DMA region"
973 config DMA_UNCACHED_NONE
974 bool "Disable DMA region"
978 comment "Cache Support"
983 config BFIN_EXTMEM_ICACHEABLE
984 bool "Enable ICACHE for external memory"
985 depends on BFIN_ICACHE
987 config BFIN_L2_ICACHEABLE
988 bool "Enable ICACHE for L2 SRAM"
989 depends on BFIN_ICACHE
990 depends on BF54x || BF561
996 config BFIN_DCACHE_BANKA
997 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
998 depends on BFIN_DCACHE && !BF531
1000 config BFIN_EXTMEM_DCACHEABLE
1001 bool "Enable DCACHE for external memory"
1002 depends on BFIN_DCACHE
1005 prompt "External memory DCACHE policy"
1006 depends on BFIN_EXTMEM_DCACHEABLE
1007 default BFIN_EXTMEM_WRITEBACK if !SMP
1008 default BFIN_EXTMEM_WRITETHROUGH if SMP
1009 config BFIN_EXTMEM_WRITEBACK
1014 Cached data will be written back to SDRAM only when needed.
1015 This can give a nice increase in performance, but beware of
1016 broken drivers that do not properly invalidate/flush their
1019 Write Through Policy:
1020 Cached data will always be written back to SDRAM when the
1021 cache is updated. This is a completely safe setting, but
1022 performance is worse than Write Back.
1024 If you are unsure of the options and you want to be safe,
1025 then go with Write Through.
1027 config BFIN_EXTMEM_WRITETHROUGH
1028 bool "Write through"
1031 Cached data will be written back to SDRAM only when needed.
1032 This can give a nice increase in performance, but beware of
1033 broken drivers that do not properly invalidate/flush their
1036 Write Through Policy:
1037 Cached data will always be written back to SDRAM when the
1038 cache is updated. This is a completely safe setting, but
1039 performance is worse than Write Back.
1041 If you are unsure of the options and you want to be safe,
1042 then go with Write Through.
1046 config BFIN_L2_DCACHEABLE
1047 bool "Enable DCACHE for L2 SRAM"
1048 depends on BFIN_DCACHE
1049 depends on (BF54x || BF561) && !SMP
1052 prompt "L2 SRAM DCACHE policy"
1053 depends on BFIN_L2_DCACHEABLE
1054 default BFIN_L2_WRITEBACK
1055 config BFIN_L2_WRITEBACK
1058 config BFIN_L2_WRITETHROUGH
1059 bool "Write through"
1063 comment "Memory Protection Unit"
1065 bool "Enable the memory protection unit (EXPERIMENTAL)"
1068 Use the processor's MPU to protect applications from accessing
1069 memory they do not own. This comes at a performance penalty
1070 and is recommended only for debugging.
1072 comment "Asynchronous Memory Configuration"
1074 menu "EBIU_AMGCTL Global Control"
1076 bool "Enable CLKOUT"
1080 bool "DMA has priority over core for ext. accesses"
1085 bool "Bank 0 16 bit packing enable"
1090 bool "Bank 1 16 bit packing enable"
1095 bool "Bank 2 16 bit packing enable"
1100 bool "Bank 3 16 bit packing enable"
1104 prompt "Enable Asynchronous Memory Banks"
1108 bool "Disable All Banks"
1111 bool "Enable Bank 0"
1113 config C_AMBEN_B0_B1
1114 bool "Enable Bank 0 & 1"
1116 config C_AMBEN_B0_B1_B2
1117 bool "Enable Bank 0 & 1 & 2"
1120 bool "Enable All Banks"
1124 menu "EBIU_AMBCTL Control"
1126 hex "Bank 0 (AMBCTL0.L)"
1129 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1130 used to control the Asynchronous Memory Bank 0 settings.
1133 hex "Bank 1 (AMBCTL0.H)"
1135 default 0x5558 if BF54x
1137 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1138 used to control the Asynchronous Memory Bank 1 settings.
1141 hex "Bank 2 (AMBCTL1.L)"
1144 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1145 used to control the Asynchronous Memory Bank 2 settings.
1148 hex "Bank 3 (AMBCTL1.H)"
1151 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1152 used to control the Asynchronous Memory Bank 3 settings.
1156 config EBIU_MBSCTLVAL
1157 hex "EBIU Bank Select Control Register"
1162 hex "Flash Memory Mode Control Register"
1167 hex "Flash Memory Bank Control Register"
1172 #############################################################################
1173 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1179 Support for PCI bus.
1181 source "drivers/pci/Kconfig"
1183 source "drivers/pcmcia/Kconfig"
1185 source "drivers/pci/hotplug/Kconfig"
1189 menu "Executable file formats"
1191 source "fs/Kconfig.binfmt"
1195 menu "Power management options"
1197 source "kernel/power/Kconfig"
1199 config ARCH_SUSPEND_POSSIBLE
1203 prompt "Standby Power Saving Mode"
1205 default PM_BFIN_SLEEP_DEEPER
1206 config PM_BFIN_SLEEP_DEEPER
1209 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1210 power dissipation by disabling the clock to the processor core (CCLK).
1211 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1212 to 0.85 V to provide the greatest power savings, while preserving the
1214 The PLL and system clock (SCLK) continue to operate at a very low
1215 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1216 the SDRAM is put into Self Refresh Mode. Typically an external event
1217 such as GPIO interrupt or RTC activity wakes up the processor.
1218 Various Peripherals such as UART, SPORT, PPI may not function as
1219 normal during Sleep Deeper, due to the reduced SCLK frequency.
1220 When in the sleep mode, system DMA access to L1 memory is not supported.
1222 If unsure, select "Sleep Deeper".
1224 config PM_BFIN_SLEEP
1227 Sleep Mode (High Power Savings) - The sleep mode reduces power
1228 dissipation by disabling the clock to the processor core (CCLK).
1229 The PLL and system clock (SCLK), however, continue to operate in
1230 this mode. Typically an external event or RTC activity will wake
1231 up the processor. When in the sleep mode, system DMA access to L1
1232 memory is not supported.
1234 If unsure, select "Sleep Deeper".
1237 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1240 config PM_BFIN_WAKE_PH6
1241 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1242 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1245 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1247 config PM_BFIN_WAKE_GP
1248 bool "Allow Wake-Up from GPIOs"
1249 depends on PM && BF54x
1252 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1253 (all processors, except ADSP-BF549). This option sets
1254 the general-purpose wake-up enable (GPWE) control bit to enable
1255 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1256 On ADSP-BF549 this option enables the the same functionality on the
1257 /MRXON pin also PH7.
1261 menu "CPU Frequency scaling"
1263 source "drivers/cpufreq/Kconfig"
1265 config BFIN_CPU_FREQ
1268 select CPU_FREQ_TABLE
1272 bool "CPU Voltage scaling"
1273 depends on EXPERIMENTAL
1277 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1278 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1279 manuals. There is a theoretical risk that during VDDINT transitions
1284 source "net/Kconfig"
1286 source "drivers/Kconfig"
1288 source "drivers/firmware/Kconfig"
1292 source "arch/blackfin/Kconfig.debug"
1294 source "security/Kconfig"
1296 source "crypto/Kconfig"
1298 source "lib/Kconfig"