2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
29 select ARCH_WANT_OPTIONAL_GPIOLIB
35 config GENERIC_FIND_NEXT_BIT
39 config GENERIC_HWEIGHT
43 config GENERIC_HARDIRQS
47 config GENERIC_IRQ_PROBE
55 config FORCE_MAX_ZONEORDER
59 config GENERIC_CALIBRATE_DELAY
69 source "kernel/Kconfig.preempt"
71 source "kernel/Kconfig.freezer"
73 menu "Blackfin Processor Options"
75 comment "Processor and Board Settings"
84 BF512 Processor Support.
89 BF514 Processor Support.
94 BF516 Processor Support.
99 BF518 Processor Support.
104 BF522 Processor Support.
109 BF523 Processor Support.
114 BF524 Processor Support.
119 BF525 Processor Support.
124 BF526 Processor Support.
129 BF527 Processor Support.
134 BF531 Processor Support.
139 BF532 Processor Support.
144 BF533 Processor Support.
149 BF534 Processor Support.
154 BF536 Processor Support.
159 BF537 Processor Support.
164 BF538 Processor Support.
169 BF539 Processor Support.
174 BF542 Processor Support.
179 BF544 Processor Support.
184 BF547 Processor Support.
189 BF548 Processor Support.
194 BF549 Processor Support.
199 BF561 Processor Support.
205 bool "Symmetric multi-processing support"
207 This enables support for systems with more than one CPU,
208 like the dual core BF561. If you have a system with only one
209 CPU, say N. If you have a system with more than one CPU, say Y.
211 If you don't know what to do here, say N.
223 config TICK_SOURCE_SYSTMR0
231 default 0 if (BF51x || BF52x || BF54x)
232 default 2 if (BF537 || BF536 || BF534)
233 default 3 if (BF561 ||BF533 || BF532 || BF531)
234 default 4 if (BF538 || BF539)
238 default 2 if (BF51x || BF52x || BF54x)
239 default 3 if (BF537 || BF536 || BF534)
240 default 5 if (BF561 || BF538 || BF539)
241 default 6 if (BF533 || BF532 || BF531)
245 default BF_REV_0_1 if (BF51x || BF52x || BF54x)
246 default BF_REV_0_2 if (BF534 || BF536 || BF537)
247 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
251 depends on (BF51x || BF52x || BF54x)
255 depends on (BF52x || BF54x)
259 depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
263 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
267 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
271 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
275 depends on (BF533 || BF532 || BF531)
287 depends on (BF512 || BF514 || BF516 || BF518)
292 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
297 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
302 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
305 config MEM_GENERIC_BOARD
307 depends on GENERIC_BOARD
310 config MEM_MT48LC64M4A2FB_7E
312 depends on (BFIN533_STAMP)
315 config MEM_MT48LC16M16A2TG_75
317 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
318 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
319 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
322 config MEM_MT48LC32M8A2_75
324 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
327 config MEM_MT48LC8M32B2B5_7
329 depends on (BFIN561_BLUETECHNIX_CM)
332 config MEM_MT48LC32M16A2TG_75
334 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
337 source "arch/blackfin/mach-bf518/Kconfig"
338 source "arch/blackfin/mach-bf527/Kconfig"
339 source "arch/blackfin/mach-bf533/Kconfig"
340 source "arch/blackfin/mach-bf561/Kconfig"
341 source "arch/blackfin/mach-bf537/Kconfig"
342 source "arch/blackfin/mach-bf538/Kconfig"
343 source "arch/blackfin/mach-bf548/Kconfig"
345 menu "Board customizations"
348 bool "Default bootloader kernel arguments"
351 string "Initial kernel command string"
352 depends on CMDLINE_BOOL
353 default "console=ttyBF0,57600"
355 If you don't have a boot loader capable of passing a command line string
356 to the kernel, you may specify one here. As a minimum, you should specify
357 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
360 hex "Kernel load address for booting"
362 range 0x1000 0x20000000
364 This option allows you to set the load address of the kernel.
365 This can be useful if you are on a board which has a small amount
366 of memory or you wish to reserve some memory at the beginning of
369 Note that you need to keep this value above 4k (0x1000) as this
370 memory region is used to capture NULL pointer references as well
371 as some core kernel functions.
374 hex "Kernel ROM Base"
376 range 0x20000000 0x20400000 if !(BF54x || BF561)
377 range 0x20000000 0x30000000 if (BF54x || BF561)
380 comment "Clock/PLL Setup"
383 int "Frequency of the crystal on the board in Hz"
384 default "11059200" if BFIN533_STAMP
385 default "27000000" if BFIN533_EZKIT
386 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
387 default "30000000" if BFIN561_EZKIT
388 default "24576000" if PNAV10
389 default "10000000" if BFIN532_IP0X
391 The frequency of CLKIN crystal oscillator on the board in Hz.
392 Warning: This value should match the crystal on the board. Otherwise,
393 peripherals won't work properly.
395 config BFIN_KERNEL_CLOCK
396 bool "Re-program Clocks while Kernel boots?"
399 This option decides if kernel clocks are re-programed from the
400 bootloader settings. If the clocks are not set, the SDRAM settings
401 are also not changed, and the Bootloader does 100% of the hardware
406 depends on BFIN_KERNEL_CLOCK
411 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
414 If this is set the clock will be divided by 2, before it goes to the PLL.
418 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
420 default "22" if BFIN533_EZKIT
421 default "45" if BFIN533_STAMP
422 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
423 default "22" if BFIN533_BLUETECHNIX_CM
424 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
425 default "20" if BFIN561_EZKIT
426 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
428 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
429 PLL Frequency = (Crystal Frequency) * (this setting)
432 prompt "Core Clock Divider"
433 depends on BFIN_KERNEL_CLOCK
436 This sets the frequency of the core. It can be 1, 2, 4 or 8
437 Core Frequency = (PLL frequency) / (this setting)
453 int "System Clock Divider"
454 depends on BFIN_KERNEL_CLOCK
458 This sets the frequency of the system clock (including SDRAM or DDR).
459 This can be between 1 and 15
460 System Clock = (PLL frequency) / (this setting)
463 prompt "DDR SDRAM Chip Type"
464 depends on BFIN_KERNEL_CLOCK
466 default MEM_MT46V32M16_5B
468 config MEM_MT46V32M16_6T
471 config MEM_MT46V32M16_5B
476 int "Max SDRAM Memory Size in MBytes"
480 This is the max memory size that the kernel will create CPLB
481 tables for. Your system will not be able to handle any more.
484 # Max & Min Speeds for various Chips
488 default 400000000 if BF512
489 default 400000000 if BF514
490 default 400000000 if BF516
491 default 400000000 if BF518
492 default 600000000 if BF522
493 default 400000000 if BF523
494 default 400000000 if BF524
495 default 600000000 if BF525
496 default 400000000 if BF526
497 default 600000000 if BF527
498 default 400000000 if BF531
499 default 400000000 if BF532
500 default 750000000 if BF533
501 default 500000000 if BF534
502 default 400000000 if BF536
503 default 600000000 if BF537
504 default 533333333 if BF538
505 default 533333333 if BF539
506 default 600000000 if BF542
507 default 533333333 if BF544
508 default 600000000 if BF547
509 default 600000000 if BF548
510 default 533333333 if BF549
511 default 600000000 if BF561
525 comment "Kernel Timer/Scheduler"
527 source kernel/Kconfig.hz
534 config GENERIC_CLOCKEVENTS
535 bool "Generic clock events"
536 depends on GENERIC_TIME
539 config CYCLES_CLOCKSOURCE
540 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
541 depends on EXPERIMENTAL
542 depends on GENERIC_CLOCKEVENTS
543 depends on !BFIN_SCRATCH_REG_CYCLES
546 If you say Y here, you will enable support for using the 'cycles'
547 registers as a clock source. Doing so means you will be unable to
548 safely write to the 'cycles' register during runtime. You will
549 still be able to read it (such as for performance monitoring), but
550 writing the registers will most likely crash the kernel.
552 source kernel/time/Kconfig
557 prompt "Blackfin Exception Scratch Register"
558 default BFIN_SCRATCH_REG_RETN
560 Select the resource to reserve for the Exception handler:
561 - RETN: Non-Maskable Interrupt (NMI)
562 - RETE: Exception Return (JTAG/ICE)
563 - CYCLES: Performance counter
565 If you are unsure, please select "RETN".
567 config BFIN_SCRATCH_REG_RETN
570 Use the RETN register in the Blackfin exception handler
571 as a stack scratch register. This means you cannot
572 safely use NMI on the Blackfin while running Linux, but
573 you can debug the system with a JTAG ICE and use the
574 CYCLES performance registers.
576 If you are unsure, please select "RETN".
578 config BFIN_SCRATCH_REG_RETE
581 Use the RETE register in the Blackfin exception handler
582 as a stack scratch register. This means you cannot
583 safely use a JTAG ICE while debugging a Blackfin board,
584 but you can safely use the CYCLES performance registers
587 If you are unsure, please select "RETN".
589 config BFIN_SCRATCH_REG_CYCLES
592 Use the CYCLES register in the Blackfin exception handler
593 as a stack scratch register. This means you cannot
594 safely use the CYCLES performance registers on a Blackfin
595 board at anytime, but you can debug the system with a JTAG
598 If you are unsure, please select "RETN".
605 menu "Blackfin Kernel Optimizations"
608 comment "Memory Optimizations"
611 bool "Locate interrupt entry code in L1 Memory"
614 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
615 into L1 instruction memory. (less latency)
617 config EXCPT_IRQ_SYSC_L1
618 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
621 If enabled, the entire ASM lowlevel exception and interrupt entry code
622 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
626 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
629 If enabled, the frequently called do_irq dispatcher function is linked
630 into L1 instruction memory. (less latency)
632 config CORE_TIMER_IRQ_L1
633 bool "Locate frequently called timer_interrupt() function in L1 Memory"
636 If enabled, the frequently called timer_interrupt() function is linked
637 into L1 instruction memory. (less latency)
640 bool "Locate frequently idle function in L1 Memory"
643 If enabled, the frequently called idle function is linked
644 into L1 instruction memory. (less latency)
647 bool "Locate kernel schedule function in L1 Memory"
650 If enabled, the frequently called kernel schedule is linked
651 into L1 instruction memory. (less latency)
653 config ARITHMETIC_OPS_L1
654 bool "Locate kernel owned arithmetic functions in L1 Memory"
657 If enabled, arithmetic functions are linked
658 into L1 instruction memory. (less latency)
661 bool "Locate access_ok function in L1 Memory"
664 If enabled, the access_ok function is linked
665 into L1 instruction memory. (less latency)
668 bool "Locate memset function in L1 Memory"
671 If enabled, the memset function is linked
672 into L1 instruction memory. (less latency)
675 bool "Locate memcpy function in L1 Memory"
678 If enabled, the memcpy function is linked
679 into L1 instruction memory. (less latency)
681 config SYS_BFIN_SPINLOCK_L1
682 bool "Locate sys_bfin_spinlock function in L1 Memory"
685 If enabled, sys_bfin_spinlock function is linked
686 into L1 instruction memory. (less latency)
688 config IP_CHECKSUM_L1
689 bool "Locate IP Checksum function in L1 Memory"
692 If enabled, the IP Checksum function is linked
693 into L1 instruction memory. (less latency)
695 config CACHELINE_ALIGNED_L1
696 bool "Locate cacheline_aligned data to L1 Data Memory"
701 If enabled, cacheline_anligned data is linked
702 into L1 data memory. (less latency)
704 config SYSCALL_TAB_L1
705 bool "Locate Syscall Table L1 Data Memory"
709 If enabled, the Syscall LUT is linked
710 into L1 data memory. (less latency)
712 config CPLB_SWITCH_TAB_L1
713 bool "Locate CPLB Switch Tables L1 Data Memory"
717 If enabled, the CPLB Switch Tables are linked
718 into L1 data memory. (less latency)
721 bool "Support locating application stack in L1 Scratch Memory"
724 If enabled the application stack can be located in L1
725 scratch memory (less latency).
727 Currently only works with FLAT binaries.
729 config EXCEPTION_L1_SCRATCH
730 bool "Locate exception stack in L1 Scratch Memory"
732 depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
734 Whenever an exception occurs, use the L1 Scratch memory for
735 stack storage. You cannot place the stacks of FLAT binaries
736 in L1 when using this option.
738 If you don't use L1 Scratch, then you should say Y here.
740 comment "Speed Optimizations"
741 config BFIN_INS_LOWOVERHEAD
742 bool "ins[bwl] low overhead, higher interrupt latency"
745 Reads on the Blackfin are speculative. In Blackfin terms, this means
746 they can be interrupted at any time (even after they have been issued
747 on to the external bus), and re-issued after the interrupt occurs.
748 For memory - this is not a big deal, since memory does not change if
751 If a FIFO is sitting on the end of the read, it will see two reads,
752 when the core only sees one since the FIFO receives both the read
753 which is cancelled (and not delivered to the core) and the one which
754 is re-issued (which is delivered to the core).
756 To solve this, interrupts are turned off before reads occur to
757 I/O space. This option controls which the overhead/latency of
758 controlling interrupts during this time
759 "n" turns interrupts off every read
760 (higher overhead, but lower interrupt latency)
761 "y" turns interrupts off every loop
762 (low overhead, but longer interrupt latency)
764 default behavior is to leave this set to on (type "Y"). If you are experiencing
765 interrupt latency issues, it is safe and OK to turn this off.
770 prompt "Kernel executes from"
772 Choose the memory type that the kernel will be running in.
777 The kernel will be resident in RAM when running.
782 The kernel will be resident in FLASH/ROM when running.
789 tristate "Enable Blackfin General Purpose Timers API"
792 Enable support for the General Purpose Timers API. If you
795 To compile this driver as a module, choose M here: the module
796 will be called gptimers.ko.
799 prompt "Uncached DMA region"
800 default DMA_UNCACHED_1M
801 config DMA_UNCACHED_4M
802 bool "Enable 4M DMA region"
803 config DMA_UNCACHED_2M
804 bool "Enable 2M DMA region"
805 config DMA_UNCACHED_1M
806 bool "Enable 1M DMA region"
807 config DMA_UNCACHED_NONE
808 bool "Disable DMA region"
812 comment "Cache Support"
817 config BFIN_DCACHE_BANKA
818 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
819 depends on BFIN_DCACHE && !BF531
821 config BFIN_ICACHE_LOCK
822 bool "Enable Instruction Cache Locking"
826 depends on BFIN_DCACHE
827 default BFIN_WB if !SMP
828 default BFIN_WT if SMP
834 Cached data will be written back to SDRAM only when needed.
835 This can give a nice increase in performance, but beware of
836 broken drivers that do not properly invalidate/flush their
839 Write Through Policy:
840 Cached data will always be written back to SDRAM when the
841 cache is updated. This is a completely safe setting, but
842 performance is worse than Write Back.
844 If you are unsure of the options and you want to be safe,
845 then go with Write Through.
851 Cached data will be written back to SDRAM only when needed.
852 This can give a nice increase in performance, but beware of
853 broken drivers that do not properly invalidate/flush their
856 Write Through Policy:
857 Cached data will always be written back to SDRAM when the
858 cache is updated. This is a completely safe setting, but
859 performance is worse than Write Back.
861 If you are unsure of the options and you want to be safe,
862 then go with Write Through.
866 config BFIN_L2_CACHEABLE
868 depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
871 Select to make L2 SRAM cacheable in L1 data and instruction cache.
874 bool "Enable the memory protection unit (EXPERIMENTAL)"
877 Use the processor's MPU to protect applications from accessing
878 memory they do not own. This comes at a performance penalty
879 and is recommended only for debugging.
881 comment "Asynchonous Memory Configuration"
883 menu "EBIU_AMGCTL Global Control"
889 bool "DMA has priority over core for ext. accesses"
894 bool "Bank 0 16 bit packing enable"
899 bool "Bank 1 16 bit packing enable"
904 bool "Bank 2 16 bit packing enable"
909 bool "Bank 3 16 bit packing enable"
913 prompt"Enable Asynchonous Memory Banks"
917 bool "Disable All Banks"
923 bool "Enable Bank 0 & 1"
925 config C_AMBEN_B0_B1_B2
926 bool "Enable Bank 0 & 1 & 2"
929 bool "Enable All Banks"
933 menu "EBIU_AMBCTL Control"
941 default 0x5558 if BF54x
952 config EBIU_MBSCTLVAL
953 hex "EBIU Bank Select Control Register"
958 hex "Flash Memory Mode Control Register"
963 hex "Flash Memory Bank Control Register"
968 #############################################################################
969 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
977 source "drivers/pci/Kconfig"
980 bool "Support for hot-pluggable device"
982 Say Y here if you want to plug devices into your computer while
983 the system is running, and be able to use them quickly. In many
984 cases, the devices can likewise be unplugged at any time too.
986 One well known example of this is PCMCIA- or PC-cards, credit-card
987 size devices such as network cards, modems or hard drives which are
988 plugged into slots found on all modern laptop computers. Another
989 example, used on modern desktops as well as laptops, is USB.
991 Enable HOTPLUG and build a modular kernel. Get agent software
992 (from <http://linux-hotplug.sourceforge.net/>) and install it.
993 Then your kernel will automatically call out to a user mode "policy
994 agent" (/sbin/hotplug) to load modules and set up software needed
995 to use devices as you hotplug them.
997 source "drivers/pcmcia/Kconfig"
999 source "drivers/pci/hotplug/Kconfig"
1003 menu "Executable file formats"
1005 source "fs/Kconfig.binfmt"
1009 menu "Power management options"
1010 source "kernel/power/Kconfig"
1012 config ARCH_SUSPEND_POSSIBLE
1017 prompt "Standby Power Saving Mode"
1019 default PM_BFIN_SLEEP_DEEPER
1020 config PM_BFIN_SLEEP_DEEPER
1023 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1024 power dissipation by disabling the clock to the processor core (CCLK).
1025 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1026 to 0.85 V to provide the greatest power savings, while preserving the
1028 The PLL and system clock (SCLK) continue to operate at a very low
1029 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1030 the SDRAM is put into Self Refresh Mode. Typically an external event
1031 such as GPIO interrupt or RTC activity wakes up the processor.
1032 Various Peripherals such as UART, SPORT, PPI may not function as
1033 normal during Sleep Deeper, due to the reduced SCLK frequency.
1034 When in the sleep mode, system DMA access to L1 memory is not supported.
1036 If unsure, select "Sleep Deeper".
1038 config PM_BFIN_SLEEP
1041 Sleep Mode (High Power Savings) - The sleep mode reduces power
1042 dissipation by disabling the clock to the processor core (CCLK).
1043 The PLL and system clock (SCLK), however, continue to operate in
1044 this mode. Typically an external event or RTC activity will wake
1045 up the processor. When in the sleep mode, system DMA access to L1
1046 memory is not supported.
1048 If unsure, select "Sleep Deeper".
1051 config PM_WAKEUP_BY_GPIO
1052 bool "Allow Wakeup from Standby by GPIO"
1054 config PM_WAKEUP_GPIO_NUMBER
1057 depends on PM_WAKEUP_BY_GPIO
1061 prompt "GPIO Polarity"
1062 depends on PM_WAKEUP_BY_GPIO
1063 default PM_WAKEUP_GPIO_POLAR_H
1064 config PM_WAKEUP_GPIO_POLAR_H
1066 config PM_WAKEUP_GPIO_POLAR_L
1068 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1070 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1072 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1076 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1079 config PM_BFIN_WAKE_PH6
1080 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1081 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1084 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1086 config PM_BFIN_WAKE_GP
1087 bool "Allow Wake-Up from GPIOs"
1088 depends on PM && BF54x
1091 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1094 menu "CPU Frequency scaling"
1096 source "drivers/cpufreq/Kconfig"
1098 config BFIN_CPU_FREQ
1101 select CPU_FREQ_TABLE
1105 bool "CPU Voltage scaling"
1106 depends on EXPERIMENTAL
1110 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1111 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1112 manuals. There is a theoretical risk that during VDDINT transitions
1117 source "net/Kconfig"
1119 source "drivers/Kconfig"
1123 source "arch/blackfin/Kconfig.debug"
1125 source "security/Kconfig"
1127 source "crypto/Kconfig"
1129 source "lib/Kconfig"