2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
22 select HAVE_FUNCTION_GRAPH_TRACER
23 select HAVE_FUNCTION_TRACER
25 select HAVE_KERNEL_GZIP
26 select HAVE_KERNEL_BZIP2
27 select HAVE_KERNEL_LZMA
29 select ARCH_WANT_OPTIONAL_GPIOLIB
38 config GENERIC_FIND_NEXT_BIT
41 config GENERIC_HWEIGHT
44 config GENERIC_HARDIRQS
47 config GENERIC_IRQ_PROBE
53 config FORCE_MAX_ZONEORDER
57 config GENERIC_CALIBRATE_DELAY
60 config LOCKDEP_SUPPORT
63 config STACKTRACE_SUPPORT
66 config TRACE_IRQFLAGS_SUPPORT
71 source "kernel/Kconfig.preempt"
73 source "kernel/Kconfig.freezer"
75 menu "Blackfin Processor Options"
77 comment "Processor and Board Settings"
86 BF512 Processor Support.
91 BF514 Processor Support.
96 BF516 Processor Support.
101 BF518 Processor Support.
106 BF522 Processor Support.
111 BF523 Processor Support.
116 BF524 Processor Support.
121 BF525 Processor Support.
126 BF526 Processor Support.
131 BF527 Processor Support.
136 BF531 Processor Support.
141 BF532 Processor Support.
146 BF533 Processor Support.
151 BF534 Processor Support.
156 BF536 Processor Support.
161 BF537 Processor Support.
166 BF538 Processor Support.
171 BF539 Processor Support.
176 BF542 Processor Support.
181 BF542 Processor Support.
186 BF544 Processor Support.
191 BF544 Processor Support.
196 BF547 Processor Support.
201 BF547 Processor Support.
206 BF548 Processor Support.
211 BF548 Processor Support.
216 BF549 Processor Support.
221 BF549 Processor Support.
226 BF561 Processor Support.
233 bool "Symmetric multi-processing support"
235 This enables support for systems with more than one CPU,
236 like the dual core BF561. If you have a system with only one
237 CPU, say N. If you have a system with more than one CPU, say Y.
239 If you don't know what to do here, say N.
253 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
254 default 2 if (BF537 || BF536 || BF534)
255 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
256 default 4 if (BF538 || BF539)
260 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
261 default 3 if (BF537 || BF536 || BF534 || BF54xM)
262 default 5 if (BF561 || BF538 || BF539)
263 default 6 if (BF533 || BF532 || BF531)
267 default BF_REV_0_0 if (BF51x || BF52x)
268 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
269 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
273 depends on (BF51x || BF52x || (BF54x && !BF54xM))
277 depends on (BF51x || BF52x || (BF54x && !BF54xM))
281 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
285 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
289 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
293 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
297 depends on (BF533 || BF532 || BF531)
309 depends on (BF512 || BF514 || BF516 || BF518)
314 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
319 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
324 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
329 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
332 config MEM_GENERIC_BOARD
334 depends on GENERIC_BOARD
337 config MEM_MT48LC64M4A2FB_7E
339 depends on (BFIN533_STAMP)
342 config MEM_MT48LC16M16A2TG_75
344 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
345 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
346 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
347 || BFIN527_BLUETECHNIX_CM)
350 config MEM_MT48LC32M8A2_75
352 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
355 config MEM_MT48LC8M32B2B5_7
357 depends on (BFIN561_BLUETECHNIX_CM)
360 config MEM_MT48LC32M16A2TG_75
362 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
365 config MEM_MT48LC32M8A2_75
367 depends on (BFIN518F_EZBRD)
370 config MEM_MT48H32M16LFCJ_75
372 depends on (BFIN526_EZBRD)
375 source "arch/blackfin/mach-bf518/Kconfig"
376 source "arch/blackfin/mach-bf527/Kconfig"
377 source "arch/blackfin/mach-bf533/Kconfig"
378 source "arch/blackfin/mach-bf561/Kconfig"
379 source "arch/blackfin/mach-bf537/Kconfig"
380 source "arch/blackfin/mach-bf538/Kconfig"
381 source "arch/blackfin/mach-bf548/Kconfig"
383 menu "Board customizations"
386 bool "Default bootloader kernel arguments"
389 string "Initial kernel command string"
390 depends on CMDLINE_BOOL
391 default "console=ttyBF0,57600"
393 If you don't have a boot loader capable of passing a command line string
394 to the kernel, you may specify one here. As a minimum, you should specify
395 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
398 hex "Kernel load address for booting"
400 range 0x1000 0x20000000
402 This option allows you to set the load address of the kernel.
403 This can be useful if you are on a board which has a small amount
404 of memory or you wish to reserve some memory at the beginning of
407 Note that you need to keep this value above 4k (0x1000) as this
408 memory region is used to capture NULL pointer references as well
409 as some core kernel functions.
412 hex "Kernel ROM Base"
415 range 0x20000000 0x20400000 if !(BF54x || BF561)
416 range 0x20000000 0x30000000 if (BF54x || BF561)
419 comment "Clock/PLL Setup"
422 int "Frequency of the crystal on the board in Hz"
423 default "10000000" if BFIN532_IP0X
424 default "11059200" if BFIN533_STAMP
425 default "24576000" if PNAV10
426 default "25000000" # most people use this
427 default "27000000" if BFIN533_EZKIT
428 default "30000000" if BFIN561_EZKIT
430 The frequency of CLKIN crystal oscillator on the board in Hz.
431 Warning: This value should match the crystal on the board. Otherwise,
432 peripherals won't work properly.
434 config BFIN_KERNEL_CLOCK
435 bool "Re-program Clocks while Kernel boots?"
438 This option decides if kernel clocks are re-programed from the
439 bootloader settings. If the clocks are not set, the SDRAM settings
440 are also not changed, and the Bootloader does 100% of the hardware
445 depends on BFIN_KERNEL_CLOCK
450 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
453 If this is set the clock will be divided by 2, before it goes to the PLL.
457 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
459 default "22" if BFIN533_EZKIT
460 default "45" if BFIN533_STAMP
461 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
462 default "22" if BFIN533_BLUETECHNIX_CM
463 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
464 default "20" if BFIN561_EZKIT
465 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
467 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
468 PLL Frequency = (Crystal Frequency) * (this setting)
471 prompt "Core Clock Divider"
472 depends on BFIN_KERNEL_CLOCK
475 This sets the frequency of the core. It can be 1, 2, 4 or 8
476 Core Frequency = (PLL frequency) / (this setting)
492 int "System Clock Divider"
493 depends on BFIN_KERNEL_CLOCK
497 This sets the frequency of the system clock (including SDRAM or DDR).
498 This can be between 1 and 15
499 System Clock = (PLL frequency) / (this setting)
502 prompt "DDR SDRAM Chip Type"
503 depends on BFIN_KERNEL_CLOCK
505 default MEM_MT46V32M16_5B
507 config MEM_MT46V32M16_6T
510 config MEM_MT46V32M16_5B
515 prompt "DDR/SDRAM Timing"
516 depends on BFIN_KERNEL_CLOCK
517 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
519 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
520 The calculated SDRAM timing parameters may not be 100%
521 accurate - This option is therefore marked experimental.
523 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
524 bool "Calculate Timings (EXPERIMENTAL)"
525 depends on EXPERIMENTAL
527 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
528 bool "Provide accurate Timings based on target SCLK"
530 Please consult the Blackfin Hardware Reference Manuals as well
531 as the memory device datasheet.
532 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
535 menu "Memory Init Control"
536 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
553 config MEM_EBIU_DDRQUE
570 # Max & Min Speeds for various Chips
574 default 400000000 if BF512
575 default 400000000 if BF514
576 default 400000000 if BF516
577 default 400000000 if BF518
578 default 400000000 if BF522
579 default 600000000 if BF523
580 default 400000000 if BF524
581 default 600000000 if BF525
582 default 400000000 if BF526
583 default 600000000 if BF527
584 default 400000000 if BF531
585 default 400000000 if BF532
586 default 750000000 if BF533
587 default 500000000 if BF534
588 default 400000000 if BF536
589 default 600000000 if BF537
590 default 533333333 if BF538
591 default 533333333 if BF539
592 default 600000000 if BF542
593 default 533333333 if BF544
594 default 600000000 if BF547
595 default 600000000 if BF548
596 default 533333333 if BF549
597 default 600000000 if BF561
611 comment "Kernel Timer/Scheduler"
613 source kernel/Kconfig.hz
619 config GENERIC_CLOCKEVENTS
620 bool "Generic clock events"
621 depends on GENERIC_TIME
625 prompt "Kernel Tick Source"
626 depends on GENERIC_CLOCKEVENTS
627 default TICKSOURCE_CORETMR
629 config TICKSOURCE_GPTMR0
630 bool "Gptimer0 (SCLK domain)"
633 config TICKSOURCE_CORETMR
634 bool "Core timer (CCLK domain)"
638 config CYCLES_CLOCKSOURCE
639 bool "Use 'CYCLES' as a clocksource"
640 depends on GENERIC_CLOCKEVENTS
641 depends on !BFIN_SCRATCH_REG_CYCLES
644 If you say Y here, you will enable support for using the 'cycles'
645 registers as a clock source. Doing so means you will be unable to
646 safely write to the 'cycles' register during runtime. You will
647 still be able to read it (such as for performance monitoring), but
648 writing the registers will most likely crash the kernel.
650 config GPTMR0_CLOCKSOURCE
651 bool "Use GPTimer0 as a clocksource"
653 depends on GENERIC_CLOCKEVENTS
654 depends on !TICKSOURCE_GPTMR0
656 source kernel/time/Kconfig
661 prompt "Blackfin Exception Scratch Register"
662 default BFIN_SCRATCH_REG_RETN
664 Select the resource to reserve for the Exception handler:
665 - RETN: Non-Maskable Interrupt (NMI)
666 - RETE: Exception Return (JTAG/ICE)
667 - CYCLES: Performance counter
669 If you are unsure, please select "RETN".
671 config BFIN_SCRATCH_REG_RETN
674 Use the RETN register in the Blackfin exception handler
675 as a stack scratch register. This means you cannot
676 safely use NMI on the Blackfin while running Linux, but
677 you can debug the system with a JTAG ICE and use the
678 CYCLES performance registers.
680 If you are unsure, please select "RETN".
682 config BFIN_SCRATCH_REG_RETE
685 Use the RETE register in the Blackfin exception handler
686 as a stack scratch register. This means you cannot
687 safely use a JTAG ICE while debugging a Blackfin board,
688 but you can safely use the CYCLES performance registers
691 If you are unsure, please select "RETN".
693 config BFIN_SCRATCH_REG_CYCLES
696 Use the CYCLES register in the Blackfin exception handler
697 as a stack scratch register. This means you cannot
698 safely use the CYCLES performance registers on a Blackfin
699 board at anytime, but you can debug the system with a JTAG
702 If you are unsure, please select "RETN".
709 menu "Blackfin Kernel Optimizations"
712 comment "Memory Optimizations"
715 bool "Locate interrupt entry code in L1 Memory"
718 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
719 into L1 instruction memory. (less latency)
721 config EXCPT_IRQ_SYSC_L1
722 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
725 If enabled, the entire ASM lowlevel exception and interrupt entry code
726 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
730 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
733 If enabled, the frequently called do_irq dispatcher function is linked
734 into L1 instruction memory. (less latency)
736 config CORE_TIMER_IRQ_L1
737 bool "Locate frequently called timer_interrupt() function in L1 Memory"
740 If enabled, the frequently called timer_interrupt() function is linked
741 into L1 instruction memory. (less latency)
744 bool "Locate frequently idle function in L1 Memory"
747 If enabled, the frequently called idle function is linked
748 into L1 instruction memory. (less latency)
751 bool "Locate kernel schedule function in L1 Memory"
754 If enabled, the frequently called kernel schedule is linked
755 into L1 instruction memory. (less latency)
757 config ARITHMETIC_OPS_L1
758 bool "Locate kernel owned arithmetic functions in L1 Memory"
761 If enabled, arithmetic functions are linked
762 into L1 instruction memory. (less latency)
765 bool "Locate access_ok function in L1 Memory"
768 If enabled, the access_ok function is linked
769 into L1 instruction memory. (less latency)
772 bool "Locate memset function in L1 Memory"
775 If enabled, the memset function is linked
776 into L1 instruction memory. (less latency)
779 bool "Locate memcpy function in L1 Memory"
782 If enabled, the memcpy function is linked
783 into L1 instruction memory. (less latency)
785 config SYS_BFIN_SPINLOCK_L1
786 bool "Locate sys_bfin_spinlock function in L1 Memory"
789 If enabled, sys_bfin_spinlock function is linked
790 into L1 instruction memory. (less latency)
792 config IP_CHECKSUM_L1
793 bool "Locate IP Checksum function in L1 Memory"
796 If enabled, the IP Checksum function is linked
797 into L1 instruction memory. (less latency)
799 config CACHELINE_ALIGNED_L1
800 bool "Locate cacheline_aligned data to L1 Data Memory"
805 If enabled, cacheline_aligned data is linked
806 into L1 data memory. (less latency)
808 config SYSCALL_TAB_L1
809 bool "Locate Syscall Table L1 Data Memory"
813 If enabled, the Syscall LUT is linked
814 into L1 data memory. (less latency)
816 config CPLB_SWITCH_TAB_L1
817 bool "Locate CPLB Switch Tables L1 Data Memory"
821 If enabled, the CPLB Switch Tables are linked
822 into L1 data memory. (less latency)
825 bool "Support locating application stack in L1 Scratch Memory"
828 If enabled the application stack can be located in L1
829 scratch memory (less latency).
831 Currently only works with FLAT binaries.
833 config EXCEPTION_L1_SCRATCH
834 bool "Locate exception stack in L1 Scratch Memory"
836 depends on !APP_STACK_L1
838 Whenever an exception occurs, use the L1 Scratch memory for
839 stack storage. You cannot place the stacks of FLAT binaries
840 in L1 when using this option.
842 If you don't use L1 Scratch, then you should say Y here.
844 comment "Speed Optimizations"
845 config BFIN_INS_LOWOVERHEAD
846 bool "ins[bwl] low overhead, higher interrupt latency"
849 Reads on the Blackfin are speculative. In Blackfin terms, this means
850 they can be interrupted at any time (even after they have been issued
851 on to the external bus), and re-issued after the interrupt occurs.
852 For memory - this is not a big deal, since memory does not change if
855 If a FIFO is sitting on the end of the read, it will see two reads,
856 when the core only sees one since the FIFO receives both the read
857 which is cancelled (and not delivered to the core) and the one which
858 is re-issued (which is delivered to the core).
860 To solve this, interrupts are turned off before reads occur to
861 I/O space. This option controls which the overhead/latency of
862 controlling interrupts during this time
863 "n" turns interrupts off every read
864 (higher overhead, but lower interrupt latency)
865 "y" turns interrupts off every loop
866 (low overhead, but longer interrupt latency)
868 default behavior is to leave this set to on (type "Y"). If you are experiencing
869 interrupt latency issues, it is safe and OK to turn this off.
874 prompt "Kernel executes from"
876 Choose the memory type that the kernel will be running in.
881 The kernel will be resident in RAM when running.
886 The kernel will be resident in FLASH/ROM when running.
893 tristate "Enable Blackfin General Purpose Timers API"
896 Enable support for the General Purpose Timers API. If you
899 To compile this driver as a module, choose M here: the module
900 will be called gptimers.
903 prompt "Uncached DMA region"
904 default DMA_UNCACHED_1M
905 config DMA_UNCACHED_4M
906 bool "Enable 4M DMA region"
907 config DMA_UNCACHED_2M
908 bool "Enable 2M DMA region"
909 config DMA_UNCACHED_1M
910 bool "Enable 1M DMA region"
911 config DMA_UNCACHED_NONE
912 bool "Disable DMA region"
916 comment "Cache Support"
921 config BFIN_EXTMEM_ICACHEABLE
922 bool "Enable ICACHE for external memory"
923 depends on BFIN_ICACHE
925 config BFIN_L2_ICACHEABLE
926 bool "Enable ICACHE for L2 SRAM"
927 depends on BFIN_ICACHE
928 depends on BF54x || BF561
934 config BFIN_DCACHE_BANKA
935 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
936 depends on BFIN_DCACHE && !BF531
938 config BFIN_EXTMEM_DCACHEABLE
939 bool "Enable DCACHE for external memory"
940 depends on BFIN_DCACHE
943 prompt "External memory DCACHE policy"
944 depends on BFIN_EXTMEM_DCACHEABLE
945 default BFIN_EXTMEM_WRITEBACK if !SMP
946 default BFIN_EXTMEM_WRITETHROUGH if SMP
947 config BFIN_EXTMEM_WRITEBACK
952 Cached data will be written back to SDRAM only when needed.
953 This can give a nice increase in performance, but beware of
954 broken drivers that do not properly invalidate/flush their
957 Write Through Policy:
958 Cached data will always be written back to SDRAM when the
959 cache is updated. This is a completely safe setting, but
960 performance is worse than Write Back.
962 If you are unsure of the options and you want to be safe,
963 then go with Write Through.
965 config BFIN_EXTMEM_WRITETHROUGH
969 Cached data will be written back to SDRAM only when needed.
970 This can give a nice increase in performance, but beware of
971 broken drivers that do not properly invalidate/flush their
974 Write Through Policy:
975 Cached data will always be written back to SDRAM when the
976 cache is updated. This is a completely safe setting, but
977 performance is worse than Write Back.
979 If you are unsure of the options and you want to be safe,
980 then go with Write Through.
984 config BFIN_L2_DCACHEABLE
985 bool "Enable DCACHE for L2 SRAM"
986 depends on BFIN_DCACHE
987 depends on (BF54x || BF561) && !SMP
990 prompt "L2 SRAM DCACHE policy"
991 depends on BFIN_L2_DCACHEABLE
992 default BFIN_L2_WRITEBACK
993 config BFIN_L2_WRITEBACK
996 config BFIN_L2_WRITETHROUGH
1001 comment "Memory Protection Unit"
1003 bool "Enable the memory protection unit (EXPERIMENTAL)"
1006 Use the processor's MPU to protect applications from accessing
1007 memory they do not own. This comes at a performance penalty
1008 and is recommended only for debugging.
1010 comment "Asynchronous Memory Configuration"
1012 menu "EBIU_AMGCTL Global Control"
1014 bool "Enable CLKOUT"
1018 bool "DMA has priority over core for ext. accesses"
1023 bool "Bank 0 16 bit packing enable"
1028 bool "Bank 1 16 bit packing enable"
1033 bool "Bank 2 16 bit packing enable"
1038 bool "Bank 3 16 bit packing enable"
1042 prompt "Enable Asynchronous Memory Banks"
1046 bool "Disable All Banks"
1049 bool "Enable Bank 0"
1051 config C_AMBEN_B0_B1
1052 bool "Enable Bank 0 & 1"
1054 config C_AMBEN_B0_B1_B2
1055 bool "Enable Bank 0 & 1 & 2"
1058 bool "Enable All Banks"
1062 menu "EBIU_AMBCTL Control"
1064 hex "Bank 0 (AMBCTL0.L)"
1067 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1068 used to control the Asynchronous Memory Bank 0 settings.
1071 hex "Bank 1 (AMBCTL0.H)"
1073 default 0x5558 if BF54x
1075 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1076 used to control the Asynchronous Memory Bank 1 settings.
1079 hex "Bank 2 (AMBCTL1.L)"
1082 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1083 used to control the Asynchronous Memory Bank 2 settings.
1086 hex "Bank 3 (AMBCTL1.H)"
1089 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1090 used to control the Asynchronous Memory Bank 3 settings.
1094 config EBIU_MBSCTLVAL
1095 hex "EBIU Bank Select Control Register"
1100 hex "Flash Memory Mode Control Register"
1105 hex "Flash Memory Bank Control Register"
1110 #############################################################################
1111 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1117 Support for PCI bus.
1119 source "drivers/pci/Kconfig"
1122 bool "Support for hot-pluggable device"
1124 Say Y here if you want to plug devices into your computer while
1125 the system is running, and be able to use them quickly. In many
1126 cases, the devices can likewise be unplugged at any time too.
1128 One well known example of this is PCMCIA- or PC-cards, credit-card
1129 size devices such as network cards, modems or hard drives which are
1130 plugged into slots found on all modern laptop computers. Another
1131 example, used on modern desktops as well as laptops, is USB.
1133 Enable HOTPLUG and build a modular kernel. Get agent software
1134 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1135 Then your kernel will automatically call out to a user mode "policy
1136 agent" (/sbin/hotplug) to load modules and set up software needed
1137 to use devices as you hotplug them.
1139 source "drivers/pcmcia/Kconfig"
1141 source "drivers/pci/hotplug/Kconfig"
1145 menu "Executable file formats"
1147 source "fs/Kconfig.binfmt"
1151 menu "Power management options"
1154 source "kernel/power/Kconfig"
1156 config ARCH_SUSPEND_POSSIBLE
1160 prompt "Standby Power Saving Mode"
1162 default PM_BFIN_SLEEP_DEEPER
1163 config PM_BFIN_SLEEP_DEEPER
1166 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1167 power dissipation by disabling the clock to the processor core (CCLK).
1168 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1169 to 0.85 V to provide the greatest power savings, while preserving the
1171 The PLL and system clock (SCLK) continue to operate at a very low
1172 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1173 the SDRAM is put into Self Refresh Mode. Typically an external event
1174 such as GPIO interrupt or RTC activity wakes up the processor.
1175 Various Peripherals such as UART, SPORT, PPI may not function as
1176 normal during Sleep Deeper, due to the reduced SCLK frequency.
1177 When in the sleep mode, system DMA access to L1 memory is not supported.
1179 If unsure, select "Sleep Deeper".
1181 config PM_BFIN_SLEEP
1184 Sleep Mode (High Power Savings) - The sleep mode reduces power
1185 dissipation by disabling the clock to the processor core (CCLK).
1186 The PLL and system clock (SCLK), however, continue to operate in
1187 this mode. Typically an external event or RTC activity will wake
1188 up the processor. When in the sleep mode, system DMA access to L1
1189 memory is not supported.
1191 If unsure, select "Sleep Deeper".
1194 config PM_WAKEUP_BY_GPIO
1195 bool "Allow Wakeup from Standby by GPIO"
1196 depends on PM && !BF54x
1198 config PM_WAKEUP_GPIO_NUMBER
1201 depends on PM_WAKEUP_BY_GPIO
1205 prompt "GPIO Polarity"
1206 depends on PM_WAKEUP_BY_GPIO
1207 default PM_WAKEUP_GPIO_POLAR_H
1208 config PM_WAKEUP_GPIO_POLAR_H
1210 config PM_WAKEUP_GPIO_POLAR_L
1212 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1214 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1216 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1220 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1223 config PM_BFIN_WAKE_PH6
1224 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1225 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1228 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1230 config PM_BFIN_WAKE_GP
1231 bool "Allow Wake-Up from GPIOs"
1232 depends on PM && BF54x
1235 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1236 (all processors, except ADSP-BF549). This option sets
1237 the general-purpose wake-up enable (GPWE) control bit to enable
1238 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1239 On ADSP-BF549 this option enables the the same functionality on the
1240 /MRXON pin also PH7.
1244 menu "CPU Frequency scaling"
1247 source "drivers/cpufreq/Kconfig"
1249 config BFIN_CPU_FREQ
1252 select CPU_FREQ_TABLE
1256 bool "CPU Voltage scaling"
1257 depends on EXPERIMENTAL
1261 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1262 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1263 manuals. There is a theoretical risk that during VDDINT transitions
1268 source "net/Kconfig"
1270 source "drivers/Kconfig"
1274 source "arch/blackfin/Kconfig.debug"
1276 source "security/Kconfig"
1278 source "crypto/Kconfig"
1280 source "lib/Kconfig"